PRELIMINARY ICS841S02I PCI EXPRESS™ CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS841S02I is a PLL-based clock generator ICS specifically designed for PCI_Express™Clock HiPerClockS™ Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. • Two 0.7V current mode differential HCSL output pairs • Crystal oscillator interface, 25MHz • Output frequency: 100MHz • RMS period jitter: 3ps (maximum) • Output skew: 35ps (maximum) • Cycle-to-cyle jitter: 35ps (maximum) • I2C support with readback capabilities up to 400kHz The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%. • Spread Spectrum for electromagnetic interference (EMI) reduction • 3.3V operating supply mode • -40°C to 85°C ambient operating temperature The ICS841S02I is available in both standard and lead-free 20-Lead TSSOP packages. • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT 25MHz XTAL_IN OSC PLL Divider Network SRCT[1:2] SRCC[1:2] XTAL_OUT SRCT1 SRCC1 VSS_SRC VDD_SRC VSS_SRC IREF SDATA Pullup SCLK Pullup VSS_SRC VDD_SRC SRCT2 SRCC2 I2C Logic IREF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD_SRC SDATA SCLK nc XTAL_OUT XTAL_IN VDD_REF VSS_REF VDDA VSSA ICS841S02I 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 1 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1, 7, 9 VSS_SRC Power Type Description Ground for core and SRC outputs. 2 , 8, 20 VDD_SRC Power Power supply for core and SRC outputs. 3, 4 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels. 5, 6 SRCT1, SRCC1 Output 10 IREF Input 11 VSSA Power Differential output pair. HCSL interface levels. A fixed precision resistor (475W) from this pin to ground provides a reference current used for differential current-mode SRCCx, SRCTx clock outputs. Analog ground pin. 12 VDDA Power Power supply for PLL. 13 VSS_REF Power Ground for crystal interface 14 VDD_REF Power Power supply for crystal interface. Crystal oscillator interface. XTAL_IN is the input. 15, 16 XTAL_IN, XTAL_OUT Input XTAL_OUT is the output. 17 nc Unused No connect. SMBus compatible SCLK. This pin has an internal pullup resistor, 18 SCLK Input Pullup but is in high impedance in powerdown mode. LVCMOS/LVTTL interface levels. SMBus compatible SDATA. This pin has an internal pullup resistor, Input/ 19 SDATA Pullup but is in high impedance in powerdown mode. Output LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ COUT Output Pin Capacitance LIN Pin Inductance IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 3 2 5 pF 7 nH ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY SERIAL DATA INTERFACE DATA PROTOCOL To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). TABLE 3A. COMMAND CODE DEFINITION BIT 7 6:5 4:0 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. Chip select address, set to "00" to access device. Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be "00000". TABLE 3B. BLOCK READ AND BLOCK WRITE PROTOCOL BIT 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Description = Block Write Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR BIT 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 3 Description = Block Read Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat star t Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data Byte 1 from slave - 8 bits Acknowledge Data Byte 2 from slave - 8 bits Acknowledge Data Bytes from Slave / Acknowledges Data Byte N from slave - 8 bits Not Acknowledge ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY TABLE 3C. BYTE READ AND BYTE WRITE PROTOCOL BIT 1 2:8 9 10 11:18 19 20:27 28 29 Description = Byte Write Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop BI T 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Description = Byte Read Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat star t Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits Not Acknowledge Stop CONTROL REGISTERS TABLE 4A. BYTE 0:CONTROL REGISTER 0 BIT 7 6 5 @Pup 0 1 1 Name Reser ved Reser ved Reser ved 4 1 SRC[T/C]2 3 1 SRC[T/C]1 2 1 0 1 0 0 Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable Reser ved Reser ved Reser ved IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 4 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR TABLE 4B. BYTE 1:CONTROL REGISTER 1 BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved @Pup 1 0 1 0 1 1 1 1 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved TABLE 4C. BYTE 2:CONTROL REGISTER 2 Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved TABLE 4D. BYTE 3:CONTROL REGISTER 3 BIT 7 6 5 4 3 2 1 0 PRELIMINARY BIT @Pup Name 7 1 SRCT/C 6 5 4 3 1 1 0 1 Reser ved Reser ved Reser ved Reser ved 2 0 SRC 1 0 1 1 Reser ved Reser ved Description Spread Spectrum Selection 0 = -0.35%, 1 = -0.50% Reser ved Reser ved Reser ved Reser ved SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Reser ved Reser ved TABLE 4E. BYTE 4:CONTROL REGISTER 4 Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved TABLE 4F. BYTE 5:CONTROL REGISTER 5 BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 5 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY TABLE 4G. BYTE 6:CONTROL REGISTER 6 BIT @Pup Name 7 0 TEST_SEL 6 0 TEST_MODE 5 4 3 2 1 0 0 1 0 0 1 1 Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N TEST Clock Mode Entr y Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved TABLE 4H. BYTE 7:CONTROL REGISTER 7 BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Description Revision Code Bit Revision Code Bit Revision Code Bit Revision Code Bit Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 3 2 1 0 6 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 4.6V Inputs, VI -0.5V to VDD_REF + 0.5 V Outputs, VO -0.5V to VDD_SRC + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) -65°C to 150°C Storage Temperature, TSTG TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD_REF Power Supply Voltage Test Conditions 3.135 3. 3 3.465 V VDDA Analog Supply Voltage VDD_REF – 0.25 3.3 VDD_REF V VDD_SRC Core/SRC Supply Voltage 3.135 3.3 3.465 V IDD_REF Cr ystal Supply Current 8 mA IDD_SRC Core/SRC Supply Current 140 mA IDDA Analog Supply Current 25 mA Maximum Units V 1.0 V TABLE 5B. DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIHSMBUS Input High Voltage SDATA, SCLK VILSMBUS SDATA, SCLK Input Low Voltage Test Conditions IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V IIL Input Low Current SDATA, SCLK VDD = 3.465V, VIN = 0V IOH Output Current IOZ High Impedance Leakage Current IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR Minimum Typical 2.2 5 -150 14 -10 7 µA µA mA 10 µA ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY TABLE 6. AC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum 25 Units fref Frequency sclk SCLK Frequency 400 kHz 50 ppm 0 ppm odc XTAL Frequency Tolerance; NOTE 1 External Reference SRCT/SRCC Duty Cycle; NOTE 2, 7 tsk(o) SRCT/C to SRCT/C Clock Skew; NOTE 2, 7 47 53 % 35 ps tPERIOD Average Period; NOTE 3 10.0533 ns tjit(cc) SRCT/C Cycle-to-Cycle Jitter ; NOTE 2, 7 35 ps tjit(per) Period Jitter, RMS; NOTE 2, 7 3 ps 700 ps 20 % tR / tF SRCT/SRCC Rise/Fall Time; NOTE 4 tRFM Rise/Fall Time Matching; NOTE 5 tDC XTAL_IN Duty Cycle; NOTE 6 ΔtR / tF Rise/Fall Time Variation VHIGH Voltage High VLOW Voltage Low VOX Output Crossover Voltage VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage 9.9970 MHz 175 47.5 520 52.5 % 125 ps 800 mv 550 mV VHIGH + 0.3 V -150 @ 0.7V Swing 250 -0.3 mv V Ring Back Voltage 0.2 V VRB NOTE 1: With recommended cr ystal. NOTE 2: Measured at crossing point VOX. NOTE 3: Measured at crossing point VOX at 100MHz. NOTE 4: Measured from VOL = 0.175V to VOH = 0.525V. NOTE 5: Determined as a fraction of 2*(tR – tF) / (tR + tF). NOTE 6: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within specification NOTE 7: Measured using a 50Ω to GND termination. IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 8 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION 3.3V±5% 3.3V±5% 100Ω 33Ω Measurement Point SRCC1:2 VDDA 49.9Ω 2pF 100Ω 33Ω GND SRCT1:2 Measurement Point 49.9Ω ➤ HCSL tcycle n ➤ tcycle n+1 ➤ tjit(cc) = tcycle n – tcycle n+1 1000 Cycles 2pF 475Ω ➤ VDD_REF, VDD_SRC 0V 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements CYCLE-TO-CYCLE JITTER VOH nSRCx VREF SRCx VOL nSRCy SRCy tsk(o) Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) RMS PERIOD JITTER OUTPUT SKEW Rise Edge Rate Clock Period (Differential) Positive Duty Cycle (Differential) Fall Edge Rate Negative Duty Cycle (Differential) VIH = +150mV 0.0V VIL = -150mV 0.0V Q/nQ Q/nQ DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME 9 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION, CONTINUED TSTABLE nQ VRB VIH = +150mV VRB = +100mV 0.0V VRB = -100mV VIL = -150mV VCROSS_DELTA = 140mV Q Q/nQ VRB TSTABLE DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK SE MEASUREMENT POINTS FOR DELTA CROSS POINT nQ nQ tFALL tRISE VCROSS_MEDIAN +75mV VCROSS_MEDIAN VCROSS_MEDIAN VCROSS_MEDIAN -75mV Q Q SE MEASUREMENT POINTS FOR RISE/FALL TIME MATCHING VMAX = 1.15V nQ VCROSS_MAX = 550mV VCROSS_MIN = 250mV Q VMIN = -0.30V SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 10 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841S02I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD_SRC, VDDA and VDD_REF should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD_SRC pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING USING THE ON-BOARD CRYSTAL OSCILLATOR are typical values for the recommended crystal as show in Table 7. The specific values may be adjusted to trim the frequency for the individual board layouts if desired. The ICS841S02I features a fully integrated Pierce oscillator to minimize system implementation costs. The recommended operation of the ICS841S02I is with a 25MHz, 18pF parallel resonant crystal. See Table 7 for complete crystal specifications. The crystal and optional trim capacitors should be located as close to the ICS841S02I XTAL_IN and XTAL_OUT pins as possible to minimize board level parasitics. For proper operation, a minimum of 10pF capacitance on each crystal pin is required. The capacitor values shown in Figure 2 TABLE 7. RECOMMENDED CRYSTAL SPECIFICATIONS Parameter Value Crystal Cut Fundamental AT Cut Resonance Parallel Resonance Shunt Capacitance (CL) 5-7pF Load Capacitance (CO) 18pF Equivalent Series Resistance (ESR) 20-50Ω XT AL_IN 33pF TBD 25MHz XTAL_OUT 18pF TBD FIGURE 2. CRYSTAL OSCILLATOR WITH TRIM CAPACITOR IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 11 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. HCSL OUTPUTs All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. OUTPUT DRIVER CURRENT The ICS841S02I outputs are HCSL current drive with the current being set with a resistor from I REF to ground. For a 50Ω pc board trace, the drive current would typically be set with a RREF of 475Ω which products an IREF of 2.32mA. The IREF is multiplied by a current mirror to an output drive of 6*2.32mA or 13.92mA. See Figure 3 for current mirror and output drive details. IREF RREF RL FIGURE 3. HCSL CURRENT MIRROR RL AND IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR OUTPUT DRIVE 12 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY RECOMMENDED TERMINATION Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. FIGURE 4A. RECOMMENDED TERMINATION Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. FIGURE 4B. RECOMMENDED TERMINATION IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 13 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS841S02I is: 1874 IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 14 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N A MAX 20 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 15 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS841S02BGI ICS841S02BGI 20 Lead TSSOP tube -40°C to 85°C ICS841S02BGIT ICS841S02BGI 20 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS841S02BGILF ICS841S02BIL 20 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS841S02BGILFT ICS841S02BIL 20 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an"LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ PCI EXPRESS CLOCK GENERATOR 16 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA