Revised August 2001 74LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25Ω Series Resistors in A Port Outputs General Description Features The LVT162245 and LVTH162245 contains sixteen noninverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. ■ Input and output interface capability to systems at 5V VCC The LVT162245 and LVTH162245 are designed with equivalent 25Ω series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162245 and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH162245), also available without bushold feature (74LVT162245). ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ A Port outputs include equivalent series resistance of 25Ω making external termination resistors unnecessary and reducing overshoot and undershoot ■ A Port outputs source/sink ±12 mA. B Port outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 162245 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V ■ Also packaged in plastic Fine Pitch Ball Grid Array (FBGA) Ordering Code: Order Number 74LVT162245GX (Note 1) Package Number BGA54A (Preliminary) Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVT162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 74LVT162245MEAX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVT162245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 74LVT162245MTDX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] 74LVTH162245GX (Note 1) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVTH162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 74LVTH162245MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVTH162245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 74LVTH162245MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Note 1: BGA package available in Tape and Reel only. © 2001 Fairchild Semiconductor Corporation DS012446 www.fairchildsemi.com 74LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25Ω Series Resistors in A Port Outputs January 1999 74LVT162245 • 74LVTH162245 Logic Symbol Connection Diagrams Pin Descriptions Pin Names Pin Assignments for SSOP and TSSOP Description OEn Output Enable Input (Active LOW) T/Rn Transmit/Receive Input A0–A15 Side A Inputs/3-STATE Outputs B0–B15 Side B Inputs/3-STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A B0 NC T/R1 OE1 NC A0 B B2 B1 NC NC A1 A2 C B4 B3 VCC VCC A3 A4 D B6 B5 GND GND A5 A6 E B8 B7 GND GND A7 A8 F B10 B9 GND GND A9 A10 G B12 B11 VCC VCC A11 A12 H B14 B13 NC NC A13 A14 J B15 NC T/R2 OE2 NC A15 Truth Tables Inputs OE1 Pin Assignment for FBGA T/R1 Outputs L L L H Bus B0–B7 Data to Bus A0–A7 Bus A0–A7 Data to Bus B0–B7 H X HIGH-Z State on A0–A7, B0–B7 Inputs OE2 T/R2 L L L H Bus A8–A15 Data to Bus B8–B15 H X HIGH-Z State on A8–A15, B8–B15 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance (Top Thru View) www.fairchildsemi.com 2 Outputs Bus B8–B15 Data to Bus A8–A15 The LVT162245 and LVTH162245 contain sixteen noninverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identi- cally, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVT162245 • 74LVTH162245 Functional Description 74LVT162245 • 74LVTH162245 Absolute Maximum Ratings(Note 2) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current IOL LOW-Level Output Current TA Free Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max 2.7 3.6 V 0 5.5 V B Port −32 A Port −12 B Port 64 A Port 12 Units mA mA −40 +85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol (V) VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage A Port B Port II(HOLD) Bushold Input Minimum Drive (Note 4) II(OD) Bushold Input Over-Drive (Note 4) Current to Change State II Input Current Data Pins Power Off Leakage Current www.fairchildsemi.com −1.2 0.8 2.0 VCC−0.2 2.7 2.4 3.0 2.0 Units V II = −18 mA VO ≤ 0.1V or V VO ≥ VCC − 0.1V V IOH = −12 mA V IOH = −100 µA V 0.8 V 2.7 0.2 V 2.7 0.5 3.0 0.4 3.0 0.5 3.0 0.55 75 3.0 500 3.6 10 3.6 ±1 −5 3.6 V 4 IOL = 12 mA IOL = 100 µA IOL = 16 mA IOL = 32 mA VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V µA VI = 0V or VCC VI = 0V VI = VCC 1 ±100 0 IOH = −32 mA IOL = 64 mA µA −500 IOH = −8 mA IOL = 24 mA µA −75 Conditions V 3.0 3.0 Control Pins IOFF 2.7–3.6 Max 2.0 3.0 A Port Output LOW Voltage Min 2.7 B Port VOL TA = −40°C to +85°C VCC Parameter µA 0V ≤ VI or VO ≤ 5.5V Symbol (Continued) TA = −40°C to +85°C VCC Parameter (V) IPU/PD Power Up/Down 3-STATE Current Min Units Conditions Max 0–1.5V ±100 µA VO = 0.5V to 3.0V VI = GND to VCC IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.0V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.6V (Note 4) (Note 4) IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < V O ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA ∆ICC Increase in Power Supply Current 3.6 0.2 mA (Note 7) VCC ≤ V O ≤ 5.5V, Outputs Disabled One Input at VCC − 0.6V Other Inputs at VCC or GND Note 4: Applies to Bushold versions only (74LVTH162245). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 8) TA = 25°C VCC (V) Min Typ Max Units Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 9) Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. 5 www.fairchildsemi.com 74LVT162245 • 74LVTH162245 DC Electrical Characteristics 74LVT162245 • 74LVTH162245 AC Electrical Characteristics TA = −40°C to +85°C Symbol tPLH CL = 50 pF, RL = 500Ω Parameter VCC = 3.3V ± 0.3V Propagation Delay Data to A Port Output tPHL Propagation Delay Data to B Port Output tPLH tPHL tPZH Output Enable Time for A Port Output tPZL Output Enable Time for B Port Output tPZH tPZL Output Disable Time for A Port Output tPHZ tPLZ tPHZ Output Disable Time for B Port Output tPLZ tOSHL A Port Output to Output Skew tOSLH (Note 10) tOSHL B Port Output to Output Skew tOSLH (Note 10) Units VCC = 2.7V Min Max Min Max 1.0 4.0 1.0 4.6 1.0 3.7 1.0 4.1 1.0 3.5 1.0 3.9 1.0 3.5 1.0 3.9 1.0 5.3 1.0 6.3 1.0 5.6 1.0 7.2 1.0 4.6 1.0 5.4 1.0 5.3 1.0 6.9 1.5 5.6 1.5 6.3 1.5 5.5 1.5 5.5 1.5 5.4 1.5 6.1 1.5 5.1 1.5 5.4 ns ns ns ns ns ns 1.0 1.0 ns 1.0 1.0 ns Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol (Note 11) Typical Units CIN Input Capacitance Parameter VCC = 0V, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 6 74LVT162245 • 74LVTH162245 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.com 74LVT162245 • 74LVTH162245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A www.fairchildsemi.com 8 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25Ω Series Resistors in A Port Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)