LTC3541-3 High Efficiency Buck + VLDO Regulator FEATURES DESCRIPTIO High Efficiency 500mA Buck Plus 300mA VLDO Regulator Auto Start-Up Powers VLDO/Linear Regulator Output Prior to Buck Output ■ Independent 500mA High Efficiency Buck (VIN: 2.7V to 5.5V) ■ 300mA VLDO Regulator with 30mA Standalone Mode ■ No External Schottky Diodes Required ■ Fixed Buck Output Voltage: 1.8V ■ VLDO Input Voltage Range (LV : 1.675V to 5.5V) IN ■ Fixed VLDO Output Voltage: 1.575V ■ Selectable Fixed Frequency, Pulse-Skip Operation or Burst Mode® Operation ■ Short-Circuit Protected ■ Current Mode Operation for Excellent Line and Load Transient Response ■ Shutdown Current: <3µA ■ Constant Frequency Operation: 2.25MHz ■ Low Dropout Buck Operation: 100% Duty Cycle ■ Small, Thermally Enhanced, 10-Lead (3mm × 3mm) DFN Package The LTC®3541-3 combines a synchronous buck DC/ DC converter with a very low dropout linear regulator (VLDOTM regulator) and internal feedback resistor networks to provide two output voltages from a single input voltage with minimum external components. When configured for dual output operation, the LTC3541-3’s auto start-up feature will bring the 1.575V VLDO/linear regulator output into regulation in a controlled manner prior to enabling the 1.8V buck output without the need for external pin control. The 300mA VLDO/linear regulator output will source only 30mA until the buck output achieves regulation. The input voltage range is ideally suited for applications powered from a Li-Ion battery and 5V or 3.3V rails. U ■ U APPLICATIO S ■ ■ ■ ■ ■ Digital Cameras Cellular Phones PC Cards Wireless and DSL Modems Other Portable Power Systems The synchronous buck converter provides a high efficiency output, typically 90%. It can provide up to 500mA of output current while switching at 2.25MHz, allowing the use of small surface mount inductors and capacitors. A mode select pin allows Burst Mode operation to be enabled for higher efficiency at light load currents, or disabled for lower noise, constant frequency operation. The VLDO regulator provides a low noise, low voltage output capable of providing up to 300mA of output current using only a 2.2µF ceramic capacitor. The input supply voltage of the VLDO regulator (LVIN) may come from the buck regulator or a separate supply. , LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. VLDO is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258. TYPICAL APPLICATIO U Buck (Burst) Efficiency vs Load Current 100 LTC3541-3 Typical Application EFFICIENCY 80 2.2µH EFFICIENCY (%) SW ENVLDO VIN MODE LTC3541-3 ENBUCK GND VOUT VOUT1 1.8V LVIN 10µF LVOUT PGND 2.2µF 35413 TA01a VOUT2 1.575V 0.1 70 60 POWER LOSS 50 40 0.01 30 POWER LOSS (W) VIN 3V TO 5V 1 VIN = 3V 90 0.001 20 10 0 1 10 100 LOAD CURRENT (mA) 0.0001 1000 35413 TA01b 35413fc LTC3541-3 W W W (Note 1) AXI U RATI GS U ABSOLUTE Supply Voltages: VIN, LVIN................................................... –0.3V to 6V LVIN – VIN...........................................................<0.3V Pin Voltages: ENVLDO, ENBUCK, MODE, SW . .....–0.3V to VIN + 0.3V Linear Regulator IOUT(MAX) (100ms) (Note 9).......100mA Operating Ambient Temperature Range (Note 2)..................................................... –40°C to 85°C Junction Temperature (Notes 5, 10)...................... 125°C Storage Temperature Range.................... –65°C to 125°C U W U PACKAGE/ORDER I FOR ATIO TOP VIEW 10 SW VIN 1 ENBUcK 2 VOUT 3 Nc 4 7 GND LVOUT 5 6 LVIN 9 ENVLDO 11 8 MODE DD PAcKAGE 10-LEAD (3mm × 3mm) PLASTIc DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 11) IS PGND, MUST BE SOLDERED TO PCB Order part number DD part marking LTC3541EDD-3 LCHR Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Notes 2, 3). SYMBOL IPK PARAMETER Peak Inductor Current CONDITIONS VIN = 4.2V (Note 8) VIN Input Voltage Range (Note 4) VIN(LINEREG) Buck VIN Line Regulation VIN = 2.7V to 5.5V, ENBUCK = VIN, ENVLDO = 0V, MODE = VIN (Note 6) VIN = 3V to 5.5V, LVOUT = 1.575V, ENBUCK = VIN, VLDO VIN Line Regulation (Referred to LVOUT) ENVLDO = VIN, MODE = 0V, IOUT(VLDO) = 100mA VIN = 3V to 5.5V, LVOUT = 1.575V, ENBUCK = 0V, Linear Regulator VIN Line Regulation (Referred to LVOUT) ENVLDO = VIN, IOUT(LDO) = 10mA LVIN(LINEREG) LVIN Line Regulation LVIN = 1.675V to 5.5V, VIN = 5.5V, LVOUT = 1.575V, (Referred to LVOUT) ENBUCK = VIN, ENVLDO = VIN, MODE = VIN, IOUT(VLDO) = 100mA VLDODO LVIN – LVOUT Dropout Voltage LVOUT = 1.575V, ENBUCK = VIN, ENVLDO = VIN, MODE = VIN, IOUT(VLDO) = 50mA (Note 9) VLOADREG Buck Output Load Regulation ENBUCK = VIN, ENVLDO = 0V, MODE = VIN (Note 6) VLDO Output Load Regulation VVOUT Linear Regulator Output Load Regulation Reference Regulation Voltage (Note 6) IOUT(VLDO) = 1mA – 300mA, LVIN = 1.8V, LVOUT = 1.575V, ENBUCK = VIN, ENVLDO = VIN, MODE = VIN IOUT(LDO) = 1mA – 30mA, LVOUT = 1.575V, ENBUCK = 0V, ENVLDO = VIN ENBUCK = VIN, ENVLDO = 0V, TA = 25°C Reference Regulation Voltage (Note 7) l 0.04 MAX 1.25 UNITS A 5.5 V 0.4 %/V 2.2 mV/V 2.2 mV/V 0.8 mV/V 20 50 0.5 mV % l 0.25 0.5 % l 0.25 0.5 % 1.764 1.8 1.836 V 1.760 1.8 1.840 V 1.755 1.8 1.845 V 1.543 1.575 1.607 V 1.540 1.575 1.610 V 1.536 1.575 1.614 V l ENBUCK = 0V, ENVLDO = VIN, TA = 25°C ENBUCK = 0V, ENVLDO = VIN, 0°C ≤ TA ≤ 85°C ENBUCK = 0V, ENVLDO = VIN, –40°C ≤ TA ≤ 85°C TYP 0.95 2.7 l ENBUCK = VIN, ENVLDO = 0V, 0°C ≤ TA ≤ 85°C ENBUCK = VIN, ENVLDO = 0V, –40°C ≤ TA ≤ 85°C VLVOUT MIN 0.8 l 35413fc LTC3541-3 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Notes 2, 3). SYMBOL IS CONDITIONS LVIN = 1.8V, LVOUT = 1.575V, ENBUCK = VIN, ENVLDO = VIN, MODE = 0V, IOUT(VLDO) = 10µA, VVOUT = 2.03V LVIN = 1.8V, LVOUT = 1.575V, ENBUCK = VIN, ENVLDO = VIN, MODE = VIL, IOUT(VLDO) = 10µA, VVOUT = 1.575V LVIN = 1.8V, LVOUT = 1.575V, ENBUCK = VIN, ENVLDO = VIN, MODE = VIN, IOUT(VLDO) = 10µA, VVOUT = 1.575V VVOUT = 2.03V, IOUT(BUCK) = 0A, ENBUCK = VIN, ENVLDO = 0V, MODE = 0V fOSC PARAMETER Buck + VLDO Burst Mode Sleep VIN Quiescent Current Buck + VLDO Burst Mode Active VIN Quiescent Current Buck + VLDO Pulse-Skip Mode Active VIN Quiescent Current Buck Burst Mode Sleep VIN Quiescent Current Buck Burst Mode Active VIN Quiscent Current Buck Pulse-Skip Mode Active VIN Quiescent Current Linear Regulator VIN Quiescent Current VIN Shutdown Quiescent Current LVIN Shutdown Quiescent Current Oscillator Frequency MIN TYP 85 MAX UNITS RPFET RDS(ON) of P-Channel MOSFET ISW = 100mA 0.25 Ω RNFET RDS(ON) of N-Channel MOSFET ISW = –100mA 0.35 Ω ILSW SW Leakage Enable = 0V, VSW = 0V or 6V, VIN = 6V ±0.01 VIH Input Pin High Threshold MODE, ENBUCK, ENVLDO l VIL Input Pin Low Threshold MODE, ENBUCK, ENVLDO l IMODE, IENBUCK, IENVLDO Input Pin Current µA 315 µA 300 µA 55 µA VVOUT = 1.575V, IOUT(BUCK) = 0A, ENBUCK = VIN, ENVLDO = 0V, MODE = 0V 300 µA VVOUT = 1.575V, IOUT(BUCK) = 0A, ENBUCK = VIN, ENVLDO = 0V, MODE = VIN 285 µA LVOUT = 1.575V, ENBUCK = VIL, ENVLDO = VIN, IOUT(VLDO) = 10µA ENBUCK = 0V, ENVLDO = 0V 50 µA 2.5 µA LVIN = 3.6V, ENBUCK = 0V, ENVLDO = 0V 0.1 µA l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3541-3 is guaranteed to meet performance specifications from 0°C to 85°C. VLDO/linear regulator output is tested and specified under pulse load conditions such that TJ ≈ TA, and are 100% production tested at 25°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Minimum operating LVIN voltage required for VLDO regulation is: LVIN ≥ LVOUT + VDROPOUT Note 4: Minimum operating VIN voltage required for VLDO and linear regulator regulation is: VIN ≥ LVOUT + 1.4V Note 5: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the following formula: TJ = TA + (PD • 43°C/W) l 1.8 2.25 2.7 ±1 0.9 MHz µA V ±0.01 0.3 V ±1 µA Note 6: The LTC3541-3 is tested in a proprietary test mode that connects VBUCKFB to the output of the error amplifier. For the reference regulation and line regulation tests, the output of the error amplifier is set to the midpoint. For the load regulation test, the output of the error amplifier is driven to minimum and maximum of the signal range. Note 7: Measurement made in closed loop linear regulator configuration with LVOUT = 1.575V, ILOAD = 10µA. Note 8: Measurement made in a proprietary test mode with slope compensation disabled. Note 9: Measurement assured by design, characterization and statistical process control. Note 10: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 35413fc LTC3541-3 TYPICAL PERFOR A CE CHARACTERISTICS U W Efficiency vs Input Voltage for Buck (Pulse Skip) Efficiency vs Input Voltage for Buck (Burst) 95 100 100 90 95 90 90 EFFICIENCY (%) IOUT = 100mA 75 70 IOUT = 30mA 65 85 80 IOUT = 100mA 75 IOUT = 30mA 70 65 50 40 30 20 55 55 10 2 4 3 50 6 5 2 3 INPUT VOLTAGE (V) 35413 G01 90 VIN = 3.6V 80 DROPOUT VOLTAGE (mV) 50 40 30 20 250 VIN = 3.6V ILOAD_BUCK = 0 IBIAS = IVIN + ILVIN – ILOAD 200 VIN = 3V 80 1000 Buck (Burst) Plus VLDO Bias Current vs VLDO Load Current 100 VIN = 2.7V 60 10 100 LOAD CURRENT (mA) 35413 G03 VLDO Dropout Voltage vs Load Current VIN = 4.2V 70 1 35413 G02 Efficiency vs Load Current for Buck (Burst) 100 0 0.1 6 4 5 INPUT VOLTAGE (V) VIN = 4.2V 60 60 50 VIN = 3.6V 70 60 VIN = 3.6V BIAS CURRENT (µA) EFFICIENCY (%) 80 VIN = 2.7V 80 IOUT = 500mA EFFICIENCY (%) IOUT = 500mA 85 EFFICIENCY (%) Efficiency vs Load Current for Buck (Pulse Skip) 60 VIN = 4.2V 40 150 100 50 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 0 1000 0 50 100 150 200 LOAD CURRENT (mA) 35413 G04 250 0 0.1 300 2.45 VOUT 1V/DIV Oscillator Frequency vs Supply Voltage 2.5 VIN = 3.6V 2ms/DIV 35413 G07 VIN = 3.6V 2.4 2.35 FREQUENCY (MHz) FREQUENCY (MHz) 2.40 IVOUT = 200mA ILVOUT = 30mA 1000 35413 G06 Oscillator Frequency vs Temperature 2.50 VIN 2V/DIV 10 100 LOAD CURRENT (mA) 35413 G05 Output (Auto-Start-Up Sequence) vs Time LVOUT 1V/DIV 1 2.30 2.25 2.20 2.15 2.10 2.3 2.2 2.1 2.05 2.00 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 35413 G08 2.0 3 5 4 SUPPLY VOLTAGE (V) 6 35413 G09 35413fc LTC3541-3 TYPICAL PERFOR A CE CHARACTERISTICS U W VLDO/Linear Regulator vs Temperature VIN = 3.6V 0.406 0.812 0.404 0.808 0.402 0.400 0.398 0.396 0.400 0.792 0.784 0.200 0.100 0.780 –50 125 SYNCH SWITCH 0.300 0.796 0.392 100 0.500 0.800 0.788 50 25 0 75 TEMPERATURE (°C) 0.600 0.804 0.394 0.390 –50 –25 0.700 VIN = 3.6V 0.816 REFERENCE (V) REFERENCE (V) 0.408 RDS(0N) vs Temperature Buck Reference vs Temperature 0.820 RDS(ON) (Ω) 0.410 –25 50 25 0 75 TEMPERATURE (°C) 35413 G19 100 125 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 35413 G20 VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED VOUT 10mV/DIV AC COUPLED IL 500mA/DIV IL 500mA/DIV ILOAD 500mA/DIV ILOAD 500mA/DIV 35413 G11 VIN = 3.6V 40µs/DIV VOUT = 1.8V ILOAD = 1mA TO 500mA 125 Buck (Burst) Load Step from 1mA to 500mA LVOUT 10mV/DIV AC COUPLED 35413 G21 100 35413 G10 Buck (Pulse Skip) Load Step from 1mA to 500mA Buck (Burst) and VLDO Output VIN = 3.6V 2µs/DIV LVOUT = 1.5V VOUT = 1.875V ILOAD = 50mA Burst Mode OPERATION VIN = 2.5V VIN = 3.6V VIN = 5.5V MAIN SWITCH VIN = 3.6V 40µs/DIV VOUT = 1.8V ILOAD = 1mA TO 500mA 35413 G12 VLDO Load Step from 100mA to 300mA VLDO Load Step from 1mA to 300mA LVOUT 20mV/DIV AC COUPLED LVOUT 20mV/DIV AC COUPLED ILOAD 250mA/DIV ILOAD 250mA/DIV VIN = 3.6V 400µs/DIV VOUT = 1.575V ILOAD = 1mA TO 300mA 35413 G13 VIN = 3.6V 400µs/DIV VOUT = 1.575V ILOAD = 100mA TO 300mA 35413 G14 35413fc LTC3541-3 TYPICAL PERFOR A CE CHARACTERISTICS U W Linear Regulator to VLDO Transient Step, Load = 1mA Linear Regulator to VLDO Transient Step, Load = 30mA LVOUT 10mV/DIV AC COUPLED LVOUT 10mV/DIV AC COUPLED ILOAD 25mA/DIV ILOAD 5mA/DIV VIN = 3.6V VOUT = 1.575V ILOAD = 1mA 40µs/DIV 35413 G15 VIN = 3.6V VOUT = 1.575V ILOAD = 30mA VLDO to Linear Regulator Transient Step, Load = 1mA LVOUT 10mV/DIV AC COUPLED ILOAD 5mA/DIV ILOAD 25mA/DIV 40µs/DIV 35413 G16 VLDO to Linear Regulator Transient Step, Load = 30mA LVOUT 10mV/DIV AC COUPLED VIN = 3.6V VOUT = 1.575V ILOAD = 1mA 40µs/DIV 35413 G17 VIN = 3.6V VOUT = 1.575V ILOAD = 30mA 40µs/DIV 35413 G18 35413fc LTC3541-3 PI FU CTIO S U U U VIN (Pin 1): Main Supply Pin. This pin must be closely decoupled to GND with a 10µF or greater capacitor. ENBUCK (Pin 2): Buck Enable Pin. This pin enables the buck regulator when driven to a logic high. VOUT (Pin 3): Buck Regulator Output Pin. This pin receives the buck regulator’s output voltage. NC (Pin 4): Not Connected. This pin must not be connected or capacitively loaded. LVOUT (Pin 5): VLDO/Linear Regulator Output Pin. This pin provides the regulated output voltage from the VLDO or linear regulator. LVIN (Pin 6): VLDO/Linear Regulator Input Supply Pin. This pin provides the input supply voltage for the VLDO power FET. SW (Pin 10): Switch Node Pin. This pin connects the internal main and synchronous power MOSFET switches to the external inductor for the buck regulator. Exposed Pad (Pin 11): Ground Pin. This pin must be soldered to the PCB to provide both electrical contact to ground and good thermal contact to the PCB. Note: Table 1 details the truth table for the control pins of the LTC3541-3. Table 1. LTC3541-3 Control Truth Table PIN NAME OPERATIONAL DESCRIPTION ENBUCK ENVLDO MODE 0 0 X LTC3541-3 Powered Down 0 1 X Buck Powered Down, VLDO Powered Down, Linear Regulator Enabled 1 0 0 Buck Enabled, VLDO Powered Down, Linear Regulator Powered Down, Burst Mode Operation 1 0 1 Buck Enabled, VLDO Powered Down, Linear Regulator Powered Down, Pulse-Skip Mode 1 1 0 Buck Enabled, VLDO Enabled, Linear Regulator Powered Down, Burst Mode Operation 1 1 1 Buck Enabled, VLDO Enabled, Linear Regulator Powered Down, Pulse-Skip Mode GND (Pin 7): Analog Ground Pin. MODE (Pin 8): Buck Mode Selection Pin. This pin enables buck Pulse-Skip operation when driven to a logic high and enables buck Burst Mode operation when driven to a logic low. ENVLDO (Pin 9): VLDO/Linear Regulator Enable Pin. When driven to a logic high, this pin enables the linear regulator when the ENBUCK pin is driven to a logic low, and enables the VLDO regulator when the ENBUCK pin is driven to a logic high. 35413fc LTC3541-3 W FU CTIO AL BLOCK DIAGRA U VOUT(BUCK) = 1.8V IOUT(BUCK) = 500mA 2.2µH U VIN(MIN) ≥ LVOUT + 1.4V 10µF 10 1 SW VIN 500mA BUCK VIN SW REF VOUT FB GND PGND LVIN VLDO/LINEAR REG REF REF 2 9 8 LFB ENBUCK ENVLDO MODE CNTRL CONTROL LOGIC VIN 3 6 LVIN LVOUT = 1.575V IOUT = 300mA (LDO) IOUT = 30mA (LINEAR REG) + – LVOUT 5 GND GND PGND 7 11 2.2µF 35413 F01 Figure 1. LTC3541-3 Functional Block Diagram 35413fc LTC3541-3 U OPERATIO The LTC3541-3 contains a high efficiency synchronous buck converter, a very low dropout regulator (VLDO) and a linear regulator. It can be used to provide up to two output voltages from a single input voltage making the LTC3541-3 ideal for applications with limited board space. The combination and configuration of these major blocks within the LTC3541-3 is determined by way of the control pins ENBUCK and ENVLDO as defined in Table 1. With the ENBUCK pin driven to a logic high and ENVLDO driven to a logic low, the LTC3541-3 enables the buck converter to efficiently reduce the voltage provided at the VIN input pin to an output voltage of 1.8V as determined by an internal feedback resistor network. The buck regulator can be configured for Pulse-Skip or Burst Mode operation by driving the MODE pin to a logic high or logic low respectively. The buck regulator is capable of providing a maximum output current of 500mA, which must be taken into consideration when using the buck regulator to provide the power for both the VLDO regulator and for external loads. With the ENBUCK pin driven to a logic low and ENVLDO driven to a logic high, the LTC3541-3 enables the linear regulator, providing a low noise regulated output voltage of 1.575V at the LVOUT pin while drawing minimal quiescent current from the VIN input pin. This feature allows output voltage LVOUT to be brought into regulation without the presence of the LVIN voltage. With the ENBUCK and ENVLDO pins both driven to a logic high, the LTC3541-3 enables the high efficiency buck converter and VLDO, providing dual output operation from a single input voltage. When configured in this manner, the LTC3541-3’s auto start-up sequencing feature will initally bring the VLDO/linear regulator output (1.575V) into regulation in a controlled manner using the linear regulator prior to enabling the buck output (1.8V) without the need for external pin control. The LTC3541-3 automatically transitions the VLDO/linear regulator output (1.575V) from the linear regulator to the VLDO regulator within 20ms of buck soft-start initiation. A detailed discussion of the transitions between the VLDO regulator and linear regulator can be found in the VLDO/Linear Regulator Loop section. Buck Regulator Control Loop The LTC3541-3 internal buck regulator uses a constant frequency, current mode, step-down architecture. Both the main (top, P-channel MOSFET) and synchronous (bottom, N-channel MOSFET) switches are internal. During normal operation, the internal main switch is turned on at the beginning of each clock cycle provided the internal feedback voltage to the buck is less than the reference voltage. The current into the inductor provided to the load increases until the current limit is reached. Once the current limit is reached the main switch turns off and the energy stored in the inductor flows through the bottom synchronous switch into the load until the next clock cycle. The peak inductor current is determined by comparing the buck feedback signal to an internal 0.8V reference. When the load current increases, the output of the buck and hence the buck feedback signal decrease. This decrease causes the peak inductor current to increase until the average inductor current matches the load current. While the main switch is off, the synchronous switch is turned on until either the inductor current starts to reverse direction or the beginning of a new clock cycle. When the MODE pin is driven to a logic low, the LTC3541‑3 buck regulator operates in Burst Mode operation for high efficiency. In this mode, the main switch operates based upon load demand. In Burst Mode operation the peak inductor current is set to a fixed value, where each burst event can last from a few clock cycles at light loads to nearly continuous cycling at moderate loads. Between burst events the main switch and any unneeded circuitry are turned off, reducing the quiescent current. In this sleep state, the load is being supplied solely from the output capacitor. As the output voltage droops, an internal error amplifier’s output rises until a wake threshold is reached causing the main switch to again turn on. This process repeats at a rate that is dependant upon the load current demand. 35413fc LTC3541-3 U OPERATIO When the MODE pin is driven to a logic high the LTC3541-3 operates in Pulse-Skip mode for low output voltage ripple. In this mode, the LTC3541-3 continues to switch at a constant frequency down to very low currents, where it will begin skipping pulses used to control the main (top) switch to maintain the proper average inductor current. If the input supply voltage is decreased to a value approaching the output voltage, the duty cycle of the buck is increased toward maximum on-time and 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the main switch and the inductor. VLDO/Linear Regulator Loop In the LTC3541-3, the VLDO and linear regulator loops consist of an amplifier and N-channel MOSFET output stages that servo the output to maintain a regulator output voltage, LVOUT. Loop configurations enabling the VLDO or the linear regulator are stable with an output capacitance as low as 2.2µF and as high as 100µF. Both the VLDO regulator and the linear regulators are capable of operating with an input voltage, VIN, as low as 3V. The VLDO regulator is designed to provide up to 300mA of output current at a very low LVIN to LVOUT voltage. This allows a clean, secondary, analog supply voltage to be provided with a minimum drop in efficiency. The VLDO regulator is provided with thermal protection that is designed to disable the VLDO function when the output, pass transistor’s junction temperature reaches approximately 160°C. In addition to thermal protection, short-circuit detection is provided to disable the VLDO function when a short-circuit condition is sensed. This circuit is designed such that an output current of approximately 1A can be provided before this circuit will trigger. As detailed in the Electrical Characteristics, the VLDO regulator will be out of regulation when this event occurs. Both the thermal and short-circuit faults, when detected, are treated as catastrophic fault conditions. The LTC3541-3 will be reset upon the detection of either event. The N-channel MOSFET incorporated in the VLDO regulator has its drain connected to the LVIN pin as shown in Figure 1. To ensure reliable operation, the LVIN voltage must be stable before the VLDO regulator is enabled. For the case where the voltage on LVIN is supplied by the buck regulator, the internal power supply sequencing logic assures voltages are applied in the appropriate manner. For the case where the buck is enabled before the VLDO regulator and an external supply is used to power the LVIN pin, the voltage on LVIN pin must be stable 1ms before the ENVLDO pin is brought from a low to a high. Further, the externally supplied LVIN must be reduced in conjunction with VIN whenever VIN is pulled low or removed. The linear regulator is designed to provide a lower output current (30mA) than that available from the VLDO regulator. The linear regulator’s output, pass transistor has its drain tied to the VIN rail. This allows the linear regulator to be turned on prior to, and independent of, the buck regulator which ordinarily drives the VLDO regulator. The linear regulator is provided with thermal protection that is designed to disable the linear regulator function when the output pass transistor’s junction temperature reaches approximately 160°C. In addition to thermal protection, short-circuit detection is provided to disable the linear regulator function when a short-circuit condition is sensed. This circuit is designed such that an output current of approximately 120mA can be provided before this circuit will trigger. As detailed in the Electrical Characteristics, the linear regulator will be out of regulation when this event occurs. Both the thermal and short-circuit faults are treated as catastrophic fault conditions. The LTC3541-3 will be reset upon the detection of either event. The N-channel MOSFET incorporated in the linear regulator has its drain connected to the VIN pin as shown in Figure 1. The size of these MOSFETs and their associated power bussing is designed to accommodate 30mA of DC current. Currents above this value can be supported for short periods as stipulated in the Absolute Maximum Ratings. 35413fc 10 U OPERATIO Transitioning from linear regulator mode to VLDO mode, accomplished by bringing ENBUCK from a logic low to a logic high while ENVLDO is a logic high or as occurs during the auto start-up sequence, is designed to be as seamless and transient free as possible. The precise transient response of LVOUT due to this transition is a function of COUT and the load current. Waveforms given in the Typical Performance Characteristics section show typical transient responses using the minimum COUT of 2.2µF and load currents of 1mA and 30mA respectively. Generally, the amplitude of any transients present will decrease as COUT is increased. To ensure reliable operation and adherence to the load regulation limits presented in the Electrical Characterstics table, the load current must not exceed the linear regulator IOUT limit of 30mA within 20ms after ENBUCK has transitioned to a logic high. The 300mA IOUT limit of VLDO applies thereafter. Further, for configurations that do not use the LTC3541-3’s buck regulator to provide the VLDO input voltage (LVIN), the user must ensure a stable LVIN voltage is present no less than 1ms prior to ENBUCK transitioning to a logic high. LTC3541-3 In a similar manner, transitioning from VLDO mode to linear regulator mode, accomplished by bringing ENBUCK from a high low to a logic low while ENVLDO is a logic high, is designed to be as seamless and transient free as possible. Again, the precise transient response of LVOUT due to this transition is a function of COUT and the load current. Waveforms given in the Typical Performance Characteristics section show typical transient responses using the minimum COUT of 2.2µF and load currents of 1mA and 30mA respectively. Generally, the amplitude of any transients present will decrease as COUT is increased. To ensure reliable operation and adherence to the load regulation limits presented in the Electrical Characterstics table, the load current must not exceed the linear regulator IOUT limit of 30mA 1ms prior to ENBUCK transitioning to a logic low and thereafer. Further, for configurations that do not use the LTC3541-3’s buck regulator to provide the VLDO input voltage (LVIN), the user must continue to ensure a stable LVIN voltage no less than 1ms after ENBUCK has transitioned to a logic low. 35413fc 11 LTC3541-3 APPLICATIO S I FOR ATIO U U W U The basic LTC3541-3 application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement and requires the selection of L, followed by CIN, COUT, and feedback resistor values for the buck and the selection of the output capacitor and feedback values for the VLDO and linear regulator. BUCK REGULATOR Inductor Selection For most applications, the appropriate inductor value will be 2.2µH. Its value is chosen largely based on the desired ripple current and burst ripple performance. Generally, large value inductors reduce ripple current, and conversely, small value inductors produce higher ripple current. Higher VIN or VOUT may also increase the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current is ΔIL = 200mA (40% of 500mA). ΔIL = V 1 VOUT 1− OUT VIN ( f )(L ) (1) The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 600mA rated inductor should be enough for most applications (500mA + 100mA). For better efficiency, choose a low DC resistance inductor. Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirement and any radiated field/EMI requirements rather than what the LTC3541-3 requires to operate. Table 2 shows some typical surface mount inductors that work well in LTC3541-3 applications. Table 2. Representative Surface Mount Inductors PART NUMBER VALUE (µH) DCR MAX DC (Ω MAX) CURRENT (A) SIZE W × L × H (mm3) Sumida CDRH3D23 1.0 1.5 2.2 3.3 0.025 0.029 0.038 0.048 2 1.65 1.3 1.1 3.9 × 3.9 × 2.4 Sumida CMD4D06 2.2 3.3 0.116 0.174 0.950 0.770 3.5 × 4.3 × 0.8 Coilcraft ME3220 1.0 1.5 2.2 3.3 0.058 0.068 0.104 0.138 2.7 2.2 1.8 1.3 2.5 × 3.2 × 2.0 Murata LQH3C 1.0 2.2 0.060 0.097 1.00 0.79 2.5 × 3.2 × 2.0 CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: cIN required IRMS ≅ IOMAX VOUT ( VIN − VOUT ) VIN 1/22 This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple, worst-case condition is commonly used for design. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer with any question regarding proper capacitor choice. The selection of COUT for the buck regulator is driven by the desired buck loop transient response, required effective series resistance (ESR) and burst ripple performance. The LTC3541-3 minimizes the required number of external components by providing internal loop compensation for the buck regulator loop. Loop stability, transient response and burst ripple performance can be tailored by choice of output capacitance. For many applications, desirable stability, transient response and ripple performance can 35413fc 12 LTC3541-3 APPLICATIO S I FOR ATIO U W U U be obtained by choosing an output capacitor value of 10µF to 22µF. the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ΔVOUT is determined by: When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. 1 ΔVOUT ≅ ΔIL ESR + 8 fcOUT Checking Transient Response where f = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors High value, low cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating, and low ESR make them ideal for switching regulator applications. Since the LTC3541-3’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ΔILOAD • ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady-state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. VLDO/LINEAR REGULATOR Output Capacitance and Transient Response The LTC3541-3 is designed to be stable with a wide range of ceramic output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. A minimum output capacitor of 2.2µF with an ESR of 0.05Ω 35413fc 13 LTC3541-3 APPLICATIO S I FOR ATIO U U W U or less is recommended to ensure stability. The LTC3541-3 VLDO is a micropower device and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Note that bypass capacitors used to decouple individual components powered by the LTC3541-3 will increase the effective output capacitor value. High ESR tantalum and electrolytic capacitors may be used, but a low ESR ceramic capacitor must be in parallel at the output. There is no minimum ESR or maximum capacitor size requirement. 20 BOTH cAPAcITORS ARE 1µF, 10V, 0603 cASE SIZE cHANGE IN VALUE (%) 0 X5R –20 –40 EFFICIENCY CONSIDERATIONS Y5V –60 –80 –100 0 2 6 4 Dc BIAS VOLTAGE (V) 8 10 35413 F06 Figure 6. Change in Capacitor vs Bias Voltage 20 0 cHANGE IN VALUE (%) Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but exhibit large voltage and temperature coefficients as shown in Figures 6 and 7. When used with a 2V regulator, a 1µF Y5V capacitor can lose as much as 75% of its initial capacitance over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are usually more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. In all cases, the output capacitance should never drop below 1µF or instability or degraded performance may occur. X5R –20 Y5V –40 –60 –80 BOTH cAPAcITORS ARE 1µF, 10V, 0603 cASE SIZE –100 –50 0 25 50 –25 TEMPERATURE (°c) 75 35413 F07 Figure 7. Change in Capacitor vs Temperature Generally, the efficiency of a regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual loss terms to determine which terms are limiting efficiency and what if any change would yield the greatest improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual loss terms as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources typically account for the majority of the losses in the LTC3541-3 circuits: VIN quiescent current, I2R losses and loss across VLDO output device. When operating with both the buck and VLDO regulator active (ENBUCK and ENVLDO equal to logic high), VIN quiescent current loss and loss across the VLDO output device dominate the efficiency loss at low load currents, whereas the I2R loss and loss across the VLDO output device dominate the efficiency loss at medium to high load currents. At low load currents with the part operating with the linear regulator (ENBUCK equal to logic low, ENVLDO 35413fc 14 LTC3541-3 APPLICATIO S I FOR ATIO U W U U equal to logic high), efficiency is typically dominated by the loss across the linear regulator output device and VIN quiescent current. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of little consequence. 1. The VIN quiescent current loss in the buck is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current and proportional to frequency. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. 3. Losses in the VLDO/linear regulator are due to the DC bias currents as given in the Electrical Characteristics and to the (VIN – VOUT) voltage drop across the internal output device transistor. Other losses when the buck and VLDO regulator are in operation (ENBUCK and ENVLDO equal logic high), including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. THERMAL CONSIDERATIONS The LTC3541-3 requires the package backplane metal (GND pin) to be well soldered to the PC board. This gives the DFN package exceptional thermal properties. The power handling capability of the device will be limited by the maximum rated junction temperature of 125°C. The LTC3541-3 has internal thermal limiting designed to protect the device during momentary overload conditions. For continuous normal conditions, the maximum junction temperature rating of 125°C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through holes can also be used to spread the heat generated by power devices. To avoid the LTC3541-3 exceeding the maximum junction temperature, some thermal analysis is required. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = PD • qJA where PD is the power dissipated by the regulator and qJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3541-3 at an input voltage VIN of 3V, an LVIN voltage of 1.8V provided by the buck regulator, an LVOUT voltage of 1.575V, a load current of 300mA for the VLDO regulator, a load current of 200mA for the buck (total load for buck = 500mA), and an ambient temperature of 85°C. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 35413fc 15 LTC3541-3 APPLICATIO S I FOR ATIO U W U U 85°C is approximately 0.25Ω.The RDS(ON) of the N-channel switch is approximately 0.4Ω. Therefore, power dissipated by the part is approximately: PD = (ILOADBUCK)2 • RSW(ON) + (ILOADVLDO) • (LVIN – LVOUT) = 145mW For the 3mm × 3mm DFN package, the qJA is 43°C/W. Thus, the junction temperature of the regulator is: TJ = 85°C + (0.145)(43) = 91°C which is well below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance RDS(ON). PC BOARD LAYOUT CHECKLIST When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3541-3. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 3. Keep the switching node, SW, away from the sensitive LFB node. 4. Keep the (–) plates of CIN and COUT as close as possible. DESIGN EXAMPLE As a design example, assume the LTC3541-3 is used in a single lithium-ion battery powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 3V. The load current requirement is a maximum of 0.5A for the buck output but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. The output voltage for the buck is 1.8V. The requirement for the output voltage of the VLDO regulator is 1.575V while providing up to 0.3A of current. With this information we can calculate L using Equation 2: L= V 1 VOUT 1− OUT VIN ( f )( ΔIL ) (2) Substituting VOUT = 1.8V, VIN = 3.6V (typ), ΔIL = 200mA and f = 2.25MHz in Equation 3 gives: L= 1.8 V 1.8 V 1− = 2 µH 2.25MHz(200mA) 3.6 V (3) A 2.2µH inductor works well for this application. For best efficiency choose a 600mA or greater inductor with less than 0.2Ω series resistance. CIN will require an RMS current rating of at least 0.25A = ILOAD(MAX)/2 at temperature. COUT for the buck is chosen to have a value of 22µF and an ESR of less than 0.25Ω. In most cases, a ceramic capacitor will satisfy this requirement. COUT for the VLDO regulator is chosen as 2.2µF. 35413fc 16 LTC3541-3 TYPICAL APPLICATIO S U Dual Output with Minimal External Components Using Auto Start-Up Sequence, Buck in Burst Mode Operation for High Efficiency Down to Low Load Currents VIN 3V TO 4.2V VOUT 1V/DIV SW ENVLDO LVOUT 1V/DIV VIN MODE LTC3541-3 ENBUCK GND 2.2µH VOUT VOUT1 1.8V 200mA LVIN 10µF LVOUT PGND 2.2µF VOUT2 1.575V 300mA VIN 2V/DIV IVOUT = 200mA ILVOUT = 30mA 35413 TA02a 2ms/DIV 35413TA02b Dual Output with Minimal External Components Using Auto Start-Up Sequence, Buck in Pulse-Skip Mode for Low Noise Operation VIN 3V TO 4.2V VOUT 1V/DIV SW ENVLDO VIN MODE LTC3541-3 ENBUCK GND 2.2µH LVOUT 1V/DIV VOUT VOUT1 1.8V 200mA LVIN 10µF LVOUT PGND 2.2µF VOUT2 1.575V 300mA 35413 TA03a VIN 2V/DIV IVOUT = 200mA ILVOUT = 30mA 2ms/DIV 35413TA03b 35413fc 17 LTC3541-3 TYPICAL APPLICATIO S U Dual Output Using Minimal External Components with VOUT2 Controlled by External Logic Signal, Buck in Burst Mode Operation for High Efficiency Down to Low Load Currents VIN 3V TO 4.2V VOUT 1V/DIV SW ENVLDO VIN MODE LTC3541-3 ENBUCK GND 2.2µH VOUT1 1.8V 200mA LVOUT 1V/DIV VOUT LVIN 10µF LVOUT PGND 2.2µF VOUT2 1.575V 300mA VIN 2V/DIV IVOUT = 200mA ILVOUT = 300mA 35413 TA04a 4ms/DIV 35413TA04b Dual Output Using Minimal External Components with VOUT1 Controlled by External Logic Signal, Buck in Burst Mode Operation for High Efficiency Down to Low Load Currents VIN 3V TO 4.2V SW 2.2µH VOUT1 1.8V 200mA 10µF VOUT 1V/DIV ENVLDO LVOUT 1V/DIV VIN MODE LTC3541-3 ENBUCK GND VOUT LVIN LVOUT PGND VOUT2 1.575V 2.2µF 300mA 35413 TA05a VIN 2V/DIV IVOUT = 200mA ILVOUT = 30mA 4ms/DIV 35413TA05b 35413fc 18 LTC3541-3 PACKAGE DESCRIPTIO U DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PAcKAGE OUTLINE 0.25 ± 0.05 0.50 BSc 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITcH AND DIMENSIONS R = 0.115 TYP 6 3.00 ±0.10 (4 SIDES) 0.38 ± 0.10 10 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 5 0.200 REF 1 0.75 ±0.05 0.00 – 0.05 (DD10) DFN 1103 0.25 ± 0.05 0.50 BSc 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEc PAcKAGE OUTLINE M0-229 VARIATION OF (WEED-2). cHEcK THE LTc WEBSITE DATA SHEET FOR cURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO ScALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PAcKAGE DO NOT INcLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXcEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENcE FOR PIN 1 LOcATION ON THE TOP AND BOTTOM OF PAcKAGE 35413fc Information furnished by Linear Technology corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3541-3 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT 3023 Dual, 2x100mA, Low Noise Micropower LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 40µA, ISD < 1µA, VOUT = ADJ, DFN, MS Packages, Low Noise < 20µVRMS(P-P), Stable with 1µF Ceramic Capacitors LT3024 Dual, 100mA/500mA, Low Noise Micropower LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 60µA, ISD < 1µA, VOUT = ADJ, DFN, TSSOP Packages, Low Noise < 20µVRMS(P-P), Stable with 1µF Ceramic Capacitors LTC3025 300mA, Micropower VLDO Linear Regulator VIN: 0.9V to 5.5V, VOUT(MIN) = 0.4V, 2.7V to 5.5V Bias Voltage Required, VDO = 45mV, IQ = 50µA, ISD < 1µA, VOUT = ADJ, DFN Packages, Stable with 1µF Ceramic Capacitors LTC3407 Dual Synchronous 600mA Synchronous Step-Down DC/DC Regulator 1.5MHz Constant Frequency Current Mode Operation, VIN from 2.5V to 5.5V, VOUT Down to 0.6V, DFN, MS Packages LTC3407-2 Dual Synchronous 800mA Synchronous Step-Down DC/DC Regulator, 2.25MHz 2.25MHz Constant Frequency Current Mode Operation, VIN from 2.5V to 5.5V, VOUT Down to 0.6V, DFN, MS Packages LTC3445 I2C Controllable Buck Regulator with Two LDOs and Backup Battery Input 600mA, 1.5MHz Current Mode Buck Regulator, I2C Programmable VOUT from 0.85V to 1.55V, two 50mA LDOs, Backup Battery Input with PowerPath Control, QFN Package LTC3446 Triple Output Step-Down Converter 1A Output Buck, Two Each 300mA VDLOs VIN: 2.7V to 5.5V, VOUT(MIN) Buck = 0.8V, VOUT(MIN) VDLO = 0.4VOUT(MIN), 14-Pin DFN Package LTC3448 600mA (IOUT), High Efficiency, 1.5MHz/2.25MHz Synchronous Step-Down Regulator with LDO Mode VIN: 2.7V to 5.5V, VOUT(MIN) = 0.6V, Switches to LDO Mode at ≤3A, DD8, MS8/E Packages LTC3541 High Efficiency Buck + VLDO Regulator VIN: 2.7V to 5.5V, VOUT(MIN) Buck = 0.8V, VOUT(MIN) VLDO = 0.4V, 3mm × 3mm 10-Pin DFN Package ® LTC3548/LTC3548-1 Dual 800mA/400mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converter LTC3548-2 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD < 1µA, DFN and 10-Pin MS Packages LTC3700 VIN from 2.65V to 9.8V, Constant Frequency 550kHz Operation Step-Down DC/DC Controller with LDO Regulator PowerPath is a trademark of Linear Technology Corporation. 35413fc 20 Linear Technology Corporation LT 0507 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2006