ROHM BD9302FP-E

TECHNICAL NOTE
Single-chip Type with Built-in FET Switching Regulator Series
2-output High-efficiency Step-down
Switching Regulators
with Built-in Power MOSFET
BD9302FP
Description
The BD9302FP is a 2-channel step-down switching regulator controller with a 2.5-MHz, 2-A power switch and available for
2.5-MHz high speed switching operation, which facilitates settings of switching frequency with external resistance, supporting
for a wide input voltage range of 6 to 18 V. Furthermore, due to a low reference voltage of 0.6 V, this BD9302FP is an L/C best
suited to high-voltage input/low-voltage output applications, for example, to step down a voltage from 12 V to 1.2 V.
Features
1)
2)
3)
4)
5)
6)
7)
A wide input voltage range of 6 V to 18 V
Easy switching frequency setting in the range of 200 k to 2.5 MHz.
Two built-in power switches of 0.4 Ω, 2 A.
180˚ phase shift
Built-in Under Voltage Lock Out circuit
Built-in overcurrent protection circuit
Built-in Thermal Shutdown circuit
Use
Power supply for DPS requiring two power sources
ADSL modem/plasma display
Audio devices
Dec. 2008
Absolute maximum ratings (Ta=25˚C)
Item
Symbol
Rating
Unit
Power supply voltage
Vcc
20
V
Power dissipation
Pd
1450*
mW
Operating temperature
Topr
-40 ~ +85
˚C
Storage temperature
Tstg
-55 ~ +150
˚C
Io
2**
A
Tjmax
150
˚C
Output current
Maximum junction temperature
* Should be derated by 11.6 mW/˚C at Ta=25˚C or more. When mounted on a glass epoxy PCB of 70¥70¥1.6 mm)
** Should not exceed Pd-value.
Recommended operating range (Ta=25˚C)
Item
Symbol
Power supply voltage
6
–
Vcc
Output current
Io
Timing resistance
RT
Oscillation frequency
Limits
Typ
Min
12
–
–
10
V
18
1.8
A
100
kΩ
2500
kHz
–
100
Fosc
Unit
Max
Electrical characteristics
Electrical characteristics (Unless otherwise specified, Ta=25˚C, Vcc=12 V, RT=10 kΩ)
Item
Symbol
Limits
Unit
Conditions
Min
Typ
Max
1800
–
2000
kHz
1
2200
–
4
6
A
3.3
3.6
V
3.0
3.3
V
10
14
uA
Vss=1V
Vss=1V, Vcc=3V
[Triangular wave oscillator block]
Oscillation frequency
FOSC
Frequency variation
FDVO
%
RT=10kΩ
~ 18V
[Overcurrent protection circuit block]
Overcurrent limit
Isw
2
[Under-voltage malfunction prevention circuit block]
3.0
VtH
Upper limit threshold voltage
2.7
VtL
Lower limit threshold voltage
*
[Soft start circuit block]
Source current
Isso
Sink current
ISSI
Clamp voltage
Vcl
Shutdown voltage
VSDWN
6
0.6
1.75
–
Not designed for radiation resistance.
* Design guarantee (No 100% pre-shipment inspections are conducted.)
2/16
1.7
5
mA
1.95
2.15
V
–
0.3
V
Vcc=3V
Electrical characteristics
Electrical characteristics (Unless otherwise specified, Ta=25˚C, Vcc=12 V, RT=10 kΩ)
Item
Symbol
Limits
Typ
Min
Max
Unit
Conditions
[Error amplifier block]
Input bias current
IIB
–
0.4
1
uA
Voltage gain
AV
–
200
–
V/V
COMP maximum output voltage
VOH
1.75
1.95
–
V
ICOMP= -0.1mA
COMP minimum output voltage
VOL
–
0.8
1.0
V
ICOMP=0.1mA
Output sink current
IOI
1
2
4
mA
VFB=0.8V
IOO
–8
–4
–1
mA
VFB=0.4V
VFB
0.588
0.600
0.612
V
Buffer
Upper-side ON resistance
Ronh
–
–
0.4
0.6
Io=1A*
Low-side ON resistance
Ronl
0.1
2
3
Ω
Ω
Output source current
Feedback voltage
[Output block]
IOFF
OFF current
[Total device]
0.2
0.4
5
–
mA
–
ICC
Average supply current
mA
Io=20mA*
SW=0V
RT=1.0V
Not designed for radiation resistance.
* Design guarantee (No 100% pre-shipment inspections are conducted.)
Measurement circuit diagram
10pF
30kΩ
A
V
A
+
1kΩ
0.6V
30kΩ
NULL AMP
100kΩ
V
V
–
1V
10kΩ
1000pF
10K
1000pF
A
1V
10pF
V
30kΩ
A
12V
V
0.6V
1000pF
SW1
RT
BOOT1
NC
PVcc
SS1
PVcc
Ω
A
5V
1uF
Vcc
NC
FB2
NULL AMP
+
–
FB1
SS2
A
V
SW1
A
1V
1kΩ
SW1L
COMP1
V
30kΩ
100kΩ
PGND1
10kΩ
1000pF
V
A
Fig. 1 Typical measurement circuit
3/16
PVcc
PVcc
BOOT2
COMP2
SW2
GND
SW2
PGND2
SW2L
5V
1uF
Ω
A
70
60
50
40
30
20
10
0
200
1000
2000
SWITCHING FREQUENCY : FSW [kHz]
Fig.8
Switching frequency – MAX Duty
SWITCHING FREQUENCY : FSW [kHz]
MAX DUTY [%]
80
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
-40˚C
25˚C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
INPUT VOLTAGE : VCC [V]
100000
10000
1000
100
10
Fig.6
SWL ON resistance –
Ambient temperature
100
85˚C
Fig.4
Power supply voltage –
Circuit current
SWITCHING FREQUENCY : FSW [kHz]
SWL ON RESISTANCE : RONL [Ω]
SW ON RESISTANCE : RONH [Ω]
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
AMBIENT TEMPERATURE : Ta [˚C]
Fig.5
SW ON resistance –
Ambient temperature
90
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Fig.3
Switching frequency –
Ambient temperature
Fig.2
Feedback voltage –
Ambient temperature
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
AMBIENT TEMPERATURE : Ta [˚C]
CIRCUIT CURRENT : ICC [mA]
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
AMBIENT TEMPERATURE : Ta [˚C]
10
100
TIMING RESISTANCE : RT [kΩ]
Fig.7
Setting resistance –
Switching frequency
100
90
80
EFFICIENCY : h [%]
0.66
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.50
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
AMBIENT TEMPERATURE : Ta [˚C]
SWITCHING FREQUENCY : FSW [kHz]
FEED BACK VOLTAGE : VFB [V]
Reference characteristics data
70
60
50
40
30
20
10
6 7
8 9 10 11 12 13 14 15 16 17 18
INPUT VOLTAGE : VCC [V]
Fig.9
Switching frequency – Power supply voltage
(*) The data shown above represent real values sampled but not guarantee values.
4/16
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
OUTPUT CURRENT : IO [A]
Fig.10
Output current – Efficiency
100
90
90
80
80
70
60
50
40
30
70
60
50
40
30
20
20
10
10
0
6
7
0
8 9 10 11 12 13 14 15 16 17 18
INPUT VOLTAGE : VCC [V]
Fig.11
Power supply voltage – Efficiency
100
DELAY TIME : TV01 [ms]
100
EFFICIENCY : h [%]
EFFICIENCY : h [%]
Reference characteristics data
10
1
0
0.01
400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
SWITCHING FREQUENCY : FSW [kHz]
Fig.12
Switching frequency – Efficiency
0.10
SS CAPACITOR : CSS [μF]
Fig.13
Set capacitance – Delay time
12V
INPUT
VOLTAGE
OUTPUT
CURRENT
OUTPUT
CURRENT
OUTPUT
VOLTAGE
(AC)
OUTPUT
VOLTAGE
(AC)
2.5V
1.47ms
OUTPUT
VOLTAGE
Fig.14
Startup waveform
Fig.15
Load transient response No. 1
Fig.16
Load transient response No. 2
Application measurement circuit diagram
100
3300pF
kΩ
33pF
10μH
20kΩ
Vo1=3.3V
0.1μF
0.1μF
20kΩ
30kΩ
30
kΩ
BD9302FP
22 51kΩ
kΩ
10μF
0.1μF
Vcc
12V
10μF
0.1μF
10μH
Vo2=1.2V
10μF
3300
pF
33
pF
Fig.17 Application measurement circuit diagram
(*) The data shown above represent real values sampled but not guarantee values.
5/16
1.00
Pin assignment
Block diagram
PGND1
1
25 SW1L
COMP1
2
24 SW1
FB1
3
23 SW1
RT
4
22 BOOT1
N.C.
5
21 PVCC
SS1/SDWN
6
20 PVCC
PGND1
1
COMP1
2
FB1
3
RT
4
N.C.
5
25 SW1L
Current
Sense
ERR
Fin
Fin
VCC
7
SS2/SDWN
8
19 PVCC
N.C.
9
18 PVCC
FB2 10
SS1/SDWN
6
VCC
7
24 SW1
OCP
0.6V
+
-
DRV2 SDWN
Set
DRV1
Reset
SDWN
slope
+ PWM
23 SW1
22 BOOT1
21 PVCC
17 BOOT2
COMP2 11
16 SW2
GND 12
15 SW2
PGND2 13
14 SW2L
20 PVCC
Internal
Bias
VREF
SS2/SDWN
8
N.C.
9
UVLO
TSD
5V
OSC
19 PVCC
FB2 10
+
-
18 PVCC
SDWN
0.6V
Set
ERR
Reset
DRV1
17 BOOT2
DRV2 SDWN
PWM
+ COMP2 11
slope
Current
Sense
16 SW2
OCP
GND 12
15 SW2
PGND2 13
14 SW2L
TOP VIEW
Fig.18 Pin assignment / Block diagram
Pin assignment / functions
Pin No.
Pin name
1
Function
Pin No.
Pin name
Function
PGND1
Ground
13
PGND2
2
COMP1
Error amplifier output
14
SW2L
Switching output 2 (Low side)
3
FB1
Error amplifier inverting input
15
SW2
Switching output 2
4
RT
Frequency setting resistor connection
16
SW2
Switching output 2
5
–
N.C.
17
BOOT2
6
SS1/SDWN
Soft start capacitor connection
18
Pvcc
Power supply input
(Shutdown at Low)
19
Pvcc
Power supply input
Power supply input
20
Pvcc
Power supply input
Soft start capacitor connection
21
Pvcc
Power supply input
(Shutdown at Low)
22
BOOT1
N.C.
23
SW1
Switching output 1
Error amplifier inverting input
24
SW1
Switching output 1
Error amplifier output
25
SW1L
Switching output 1 (Low side)
7
VCC
8
SS2/SDWN
9
–
10
FB2
11
COMP2
12
GND
Ground
6/16
Ground
Boot capacitor connection
Boot capacitor connection
33pF
PGND1
100kΩ
1
3300
pF COMP1
25
2
20kΩ
FB1
3
24
OCP
0.6V
+
-
Current
Sense
ERR
22kΩ
RT
4
slope
51kΩ
N.C. 5
SS1/SDWN
0.1μF
+ PWM
SW1
10
μH
SW1
VO : 3.3V
10μF
0.1μF
BOOT1
22
DRV2 SDWN
Set
DRV1
Reset
SDWN
21
PVCC
6
VCC
7
20
VCC
VREF
SS2/SDWN
23
SW1L
Internal
Bias
8
UVLO
TSD
PVCC
10
μF
5V
OSC
19
VCC
PVCC
0.1μF
N.C. 9
0.6V
FB2
30
kΩ
30
kΩ
10
+
-
Set
ERR
Reset
PWM
33
pF
18
SDWN
DRV1
17
DRV2 SDWN
PVCC
BOOT2
0.1
μF
+ COMP2
3300 20
pF kΩ
GND
11
slope
Current
Sense
OCP
12
13
PGND2
16
SW2
10
μH
VO : 1.2V
10
μF
15
14
SW2
SW2L
Fig.19 Typical application circuit
ü Error amplifier (ERR) block
The ERR block is a circuit used to compare between the 0.6-V reference voltage and the feedback voltage of output
voltage. The COMP voltage, a result of this comparison, determines the switching Duty. Furthermore, soft start function is
activated with the SS voltage while in startup operation. Consequently, the COMP voltage is limited to the SS voltage.
ü Oscillator (OSC) block
The OSC block is a block to determine the switching frequency through the RT pin, which is settable in the range of 100
kHz to 2500 kHz.
ü SLOPE block
The SLOPE block is a block to generate a triangular wave from the clock generated with the OSC and then to transmit the
triangular wave to the PWM comparator.
ü PWM block
The PWM block is used to make comparison between the output COMP voltage of the error amplifier block and the
triangular wave of the SLOPE block, thus determining the switching Duty. The switching duty is limited with the maximum
duty ratio, which is internally determined, and will not reach 100%.
ü Reference voltage (UREF) block
The UREF block is a block to generate a 2.9-V internal reference voltage.
ü Protection circuit (UVLO/TSD) block
The UVLO (Under Voltage Lock Out) circuit is used to shut down the circuit when the voltage falls below approximately 3.3
V, while the TSD (Thermal Shutdown) circuit is used to shut down the circuit at a temperature of 175˚C and reset it at a
temperature of 160˚C.
ü Overcurrent protection circuit (OCP)
This function is used to detect a current passing through the power transistor FET with the CURRENT SENSE and activate
the overcurrent protection when the current reaches approximately 4 A. If the overcurrent protection is activated, switching
will be turned OFF to discharge the SS pin capacitance.
7/16
Timing chart
Startup sequence
Vcc
SS
SW
VOUT
Fig.20 Startup sequence
Normal operation
VdC
SW
Vo
Io
Fig.21 While in normal operation
8/16
External component setting procedure
(1) Setting of output L constant
The coil L used for output is determined according to the rated current ILR and the maximum load current value IOMAX
of the coil.
IL
Adjust so that (IOMAX + DIL) will
not conflict with the rating.
VCC
ILR
IL
Average IOMAX current
L
VO
CO
t
Fig.22
Fig.23
Adjust so that (IOMAX + DIL) will not conflict with the rating. At this time, DIL can be obtained according to the formula
shown below.
Step-down DIL =
VO
1
1
¥ (VCC – VO) ¥
¥
VCC
L
f
[A] . . . (1.1)
,where f: Switching frequency
Furthermore, since the coil L value may also vary by approximately ±30%, set this value with an adequate margin. If the
coil current IL exceeds the rated coil current ILR, the internal IC element may be damaged. It is recommended to make
setting of coil value in the range of 4.7 μF to 100 μF.
(2) Setting of output Co constant
For output capacitor, select the allowable ripple voltage VPP or the allowable drop voltage at a sharp change of load,
whichever larger for the capacitor. The output ripple voltage can be obtained according to the formula shown below.
Step-down DVPP = DIL ¥ RESR + DIL ¥ VO ¥ 1
2CO
VCC
f
,where f: Switching frequency
[V]
Design the component so that this constant will fall within the allowable ripple voltage.
Furthermore, estimate the drop voltage VDR at a sharp change of load according to the formula shown below.
VDR =
DI
¥ 10μsec
CO
[V]
However, 10 μsec will be the estimated value of the DC/DC converter response speed.
Make setting of capacitance with thorough consideration given to the margin so that these two values will fall into the
specified values. It is recommended to make setting of the capacitance in the range of 10 μF to 100 μF. if a short circuit
occurs, an inverse current passes through the parasitic diode to cause damage to the internal circuits. To prevent that,
insert a backflow prevention diode.
9/16
(3) Setting of feedback resistance constant
In order to make settings of feedback resistance, refer to the formula shown. It is recommended to make setting of
resistance in the range of 10 kΩ to 330 kΩ. Setting the resistance to 10 kΩ or less will result in degraded power
efficiency, while setting it to 330 kΩ or more will increase the offset voltage due to the input bias current of 0.4 μA (TYP)
of the internal error amplifier.
VO
Internal reference voltage: 0.6 V
R8
FB
R9
Fig.24
R8+R9
¥ 0.6 [V]
R9
VO=
(4) Setting of oscillation frequency
Connecting a resistor to the RT pin (pin 4) will allow for the setting of triangular wave oscillation frequency. The RT
determines the charge/discharge current to the internal capacitor, with which the frequency varies. Referring to Figure
shown below, make settings of the RT resistor. Recommended setting range is 10 to 100 kΩ. Be noted that any setting
outside of this range may turn OFF switching, thus impairing the operation guarantee.
SWITCHING FREQUENCY : FSW [kHz]
100000
10000
1000
100
10
10
100
TIMING RESISTANCE : RT [kΩ]
Fig.25 RT vs. Switching frequency
(5) Setting of soft start time
The soft start function will be required to prevent an excessive increase in the coil current and overshoot of the output
voltage, while in startup operation. Figure below shows the relationship between the capacitor and the soft start time.
Referring to this Figure, make the capacitor setting.
DELAY TIME : TV01 [ms]
100
10
1
0
0.01
0.10
SS CAPACITOR : CSS [μF]
1.00
Fig.26 SS capacitance vs. Delay time
It is recommended to make setting of capacitance value in the range of 0.01 to 10 μF. Setting the capacitance value to
0.01 μF or less may cause overshoot to the output voltage. If any startup-related function (sequence) of other power
supply is provided, use a high-accuracy product (e.g. ¥ 5R) or the like.
Furthermore, since the soft start time varies with the input voltage, output voltage, load, coil, output capacitor, or else,
be sure to check to be sure this soft start time on the actual system.
10/16
(6) Phase compensation
Phase compensation setting procedure
The phase compensation setting procedure varies with the selection of capacitance used for DC/DC converter
application. In this connection, the following section describes the procedure by classifying into the two types.
Furthermore, the application stability conditions are described in the “Description” section.
1. Application stability conditions
2. For output capacitors having high ESR, such as electrolytic capacitor
3. For output capacitors having low ESR, such as ceramic capacitor or OS-CON
About application stability conditions
The following section shows the stability conditions of negative feedback system.
ü At a 1 (0-dB) gain, the phase delay is 150˚ or less (i.e., the phase margin is 30˚ or more).
Furthermore, since the DC/DC converter application is sampled according to the switching frequency, GBW of the
overall system should be set to 1/10 or less of the switching frequency. The following section summarizes the
targeted characteristics of this application.
ü At a 1 (0-dB) gain, the phase delay is 150˚ or less (i.e., the phase margin is 30˚ or more).
ü The GBW (i.e., frequency at 0-dB gain) for this occasion is 1/10 or less of the switching frequency.
Consequently, in order to upgrade the responsiveness, higher switching frequency should be provided.
A knack for ensuring the stability through the phase compensation is to cancel a secondary phase delay (-180˚)
resulting from LC resonance with a secondary phase lead (i.e., through inserting two phase leads).
Furthermore, the GBW (i.e., frequency at 0-dB gain) is determined according to phase compensation capacitance
to be provided for the error amplifier. Consequently, in order to reduce the GBW, increase the capacitor
capacitance.
(1) Typical (sun) integrator (Low pass filter)
(2) Open loop characteristics of integrator
A
Feed
back
A
R
FB
(a)
-20dB/decade
Gain
[dB]
GBW(b)
0
Phase
[deg]
C
Fig.27
0
-90
-90˚
位相マージン
-180
-180˚
Fig.28
Point (a) fa=
1
1.25 [Hz]
2pRCA
Point (b) fa= GBW
1
[Hz]
2pRC
Since the error amplifier is provided with (1) or (2) phase compensation, the low pass filter is applied.
In the case of the DC/DC converter application, the R becomes a parallel resistance of the feedback resistance.
11/16
For output capacitors having high ESR, such as aluminum electrolytic capacitor
For output capacitors having high ESR (i.e., several ohms), the phase compensation setting procedure becomes
comparatively simple. Since the DC/DC converter application has surely a LC resonant circuit attached to the
output, a -180˚ phase-delay occurs in that area. If ESR component is present there, however, a +90˚ phase-lead
occurs to shift the phase delay to -90˚. Since the phase delay is desired to set within 150˚, this is a very effective
method but has a demerit to increase the ripple component of the output voltage.
(3) LC resonant circuit
(4) With ESR provided
VCC
VCC
L
L
VO
VO
RESR
C
C
fr=
1
[Hz]
2p LC
1
[Hz]: Resonance point
2p LC
fr=
At this resonance point, a -180˚
phase-delay occurs.
fESR=
1
[Hz]: Phase lead
2pRESRC
A -90˚ phase-delay occurs.
Fig.29
Fig.30
According to changes in phase characteristics due to the ESR, only one phase lead should be inserted. For this
phase lead, select either of the methods shows below.
(5) Insert feedback resistance in the C.
VO
C1
(6) Insert the R3 in integrator.
VO
C2
R1
R3
C2
R1
A
FB
A
FB
R2
R2
Phase lead: fZ=
1
[Hz]
2pC1R1
Phase lead: fZ=
Fig.31
1
[Hz]
2pC2R3
Fig.32
For the purpose of canceling the LC resonance, the frequency to insert the phase lead should be set close to the
LC resonant frequency.
For output capacitors having low ESR, such as ceramic capacitor or OS-CON
Unlike the section above, in order to use capacitors having low ESR (i.e., several tens of mW), two phase-leads
should be inserted so that a -180∞ phase-delay due to LC resonance will be observed. Example (7) blow shows a
typical phase compensation procedure.
(7) Phase compensation with secondary phase lead
VO
C1
R3
C2
R1
A
Phase lead: fZ1=
1
[Hz]
2pR1C1
Phase lead: fZ2=
1
[Hz]
2pR3C2
FB
R2
LC resonant frequency: fr=
1
2p LC
[Hz]
Fig.33
For the settings of phase lead frequency, insert both of the phase leads close to the LC resonant frequency.
12/16
Equivalent circuit
2.COMP1
VREG
3.FB1
Vcc
VREG
10.FB2
11.COMP2
1kΩ
20Ω
5kΩ
2.5kΩ
5kΩ
4.RT
6.SS1/SDWN
VREG
Vcc
8.SS2/SDWN
2kΩ
170Ω
50Ω
100kΩ
14.SW2L
15.SW2
PVcc
16.SW2
25.SW1L
23.SW1
24.SW1
17.BOOT2
22.BOOT1
10Ω
SW
Fig.34 Equivalent circuit
13/16
PVcc
BOOT
Cautions on use
1)
Absolute maximum ratings
Even though thorough attention is exerted to the quality control of this IC, exceeding the absolute maximum ratings, such
as applied voltage, operating temperature range, etc., can break down the IC. Should the IC break down, it will be
impossible to identify breaking mode such as short circuit mode or an open mode. If any special mode exceeding the
absolute maximum ratings is assumed, consideration should be given to take physical safety measures including use of
fuses, etc.
2)
GND potential
GNDMake setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.
3)
Thermal design
With consideration given to power dissipation (Pd) in the actual use state, provide the thermal design with an adequate
margin.
4)
Short circuit between pins and erroneous mounting
In order to mount ICs on a set printed circuit board, pay thorough attention to the direction and offset of the ICs.
Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering
between pins or between the pin and the power supply or the GND pin, the ICs can break down.
5)
Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
6)
Inspection with set printed circuit board
On the inspection with the set printed circuit board, if a capacitor is connected to a low-impedance pin, the IC can suffer
stress. Therefore, be sure to discharge from the set printed circuit board by each process. For protection against static
electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage
of the set printed circuit board. Furthermore, in order to connect the jig for the inspection process, be sure to turn OFF
the power supply and then mount the set printed circuit board to the jig. After the completion of the inspection, be sure to
turn OFF the power supply and then dismount the set printed circuit board from the jig.
7)
IC pin input
This IC is a monolithic IC, which has P+ isolation and P layer between elements to isolate the elements. P-N junction is
formed with this P layer and the N layer of each element, thus composing a variety of parasitic elements.
For example, as shown in Fig. 35, if the resistor and the transistor is connected with the pin respectively,
When GND>(Pin A) for the resistor or GND>(Pin B) for the transistor (NPN), P-N junction will operate as a parasitic
diode.
For the transistor (NPN), when GND>(Pin B), the parasitic NPN transistor will operate with the N layer of other
element in the proximity of the said parasitic diode.
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the
parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the
IC. Therefore, pay thorough attention not to handle the input pins such as to apply to the input pins a voltage lower than
the GND (P layer) so that any parasitic element will operate.
Transistor (NPN)
Resistor
B
(Pin A)
(Pin B)
C
E
GND
N
P
P+
P+
N
N
N
N
P layer
P
P+
P+
N
N
P layer
Parasitic element
GND
Parasitic element
(Pin A)
GND
(Pin B)
Parasitic element
B
C
E
GND
GND
Fig.35 Typical simple construction of monolithic IC
14/16
Parasitic element
8)
9)
Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be
recommended to separate the large-current GND pattern from the
small-signal GND pattern and establish a single ground at the reference
point of the set PCB so that resistance to the wiring pattern and voltage
fluctuations due to a large current will cause no fluctuations in voltages of
the small-signal GND. Pay attention not to cause fluctuations in the GND
wiring pattern of external parts as well.
On the application shown on the right, if the VCC and each output voltage
are inverted, for example, if the VCC is short-circuited to the Ground with
external diode charged, internal circuits or elements may be damaged. To
avoid that, use the output pin capacitor in the range of 10 to 100 μF.
Furthermore, in order to use a capacitor of 100 μF or more, it is
recommended to insert a backflow prevention diode or a bypass diode
between the output and VCC.
Bypass diode
Backflow prevention diode
VCC
Output pin
Fig.36 Typical bypass diode application
10) Overcurrent protection circuit
Output has a built-in overcurrent protection circuit according to the current capability, which prevents the destruction of
the IC at short-circuiting of load. However, this protection circuit is only effective to prevent destruction due to a sudden
accident but does not support for the continuous operation of the protection circuit or use in transition. Furthermore,
since the current capability has characteristic negative to temperature, give consideration to the thermal design.
11) Temperature protection circuit
This IC has a built-in temperature protection circuit to prevent the thermal destruction of the IC. As described above, be
sure to use this IC within the power dissipation range. Should a condition exceeding the power dissipation range
continues, the chip temperature Tj will rise to activate the temperature protection circuit, thus turning OFF the output
power element. Then, when the tip temperature Tj falls, the circuit will be automatically reset.
Furthermore, since the temperature protection circuit is activated under the condition exceeding the absolute maximum
ratings, NEVER attempt to use the temperature protection circuit for set design or else.
12) Input capacitor
In order to derate a peak noise, which occurs while in switching operation, be sure to insert a capacitor (ceramic
capacitor) having a low ESR of 10 to 100 μF as close to the pin as possible between the VCC and Ground.
Power dissipation
Power dissipation : PD [mW]
1500
1250
1000
750
500
250
0
0
25
50
75
100
Ambient temperature : Ta [˚C]
Fig.37 Thermal derating characteristics
15/16
125
150
Selection of order type
B
D
9
3
0
2
F
Product name
P
-
E
2
Package/Forming specifications
Package specifications
HSOP25
<Outline dimensions>
<Package specifications>
13.6±0.2
Package style
2.75±0.1
Q’ty per package 2000 pcs
Packaging
E2
(When holding a reel by left hand and pulling out the tape by
direction
0.3 Min.
7.8±0.3
14
5.4±0.2
25
1
1.9±0.1
right hand, No. 1 pin appears in the upper left of the reel.)
13
0.25±0.1
1.95±0.1
0.11
Embossed carrier tape
0.1
0.8
0.36±0.1
Reel
(Unit : mm)
No. 1 pin
Pulling-out side
* Please place an order for this IC in multiplies of the quantity per package.
The contents described herein are correct as of December, 2008
Catalog No. 08T907A '08.12 ROHM©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or
exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
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The Products are not designed or manufactured to be used with any equipment, device or system
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Copyright © 2008 ROHM CO.,LTD.
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Contact us : [email protected] rohm.co. jp
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Appendix1-Rev3.0