CADEKA SPT5420SIM

SPT5420
13-BIT, OCTAL D/A CONVERTER
TECHNICAL DATA
JUNE 26, 2001
FEATURES
APPLICATIONS
• 13-bit resolution
• Pin compatible with AD7839
• Eight DACs in one package
• Buffered voltage outputs
• Wide output voltage swing V DD–2.5 V to VSS+2.5 V
• 15 µs settling time to ±0.5 LSB
• Double-buffered digital inputs
• Microprocessor and TTL/CMOS compatible
• Automatic test equipment
• Instrumentation
• Process control
GENERAL DESCRIPTION
DAC’s full-scale output voltage and output voltage offset
are adjustable with analog inputs (RGND, VREFB, VREFT).
The SPT5420 contains eight 13-bit digital-to-analog
CMOS converters designed primarily for automatic test
equipment applications. It uses novel circuit topology to
convert the 13-bit digital inputs into output voltages which
are proportionate to the applied reference voltages. Each
The SPT5420 operates over an industrial temperature
range of –40 °C to +85 °C and is available in a 10 x 10 mm,
44-lead metric quad flat pack (MQFP) plastic package.
BLOCK DIAGRAM
VREFT01 VREFB01
13
D
0A
LEA0
13
D
1A
LEA1
13
D
2A
LEA2
13
D0–D12
13
LDAC
D
4A
LEA4
WR
CS
3A
LEA3
13
A0–A2
D
Control
8
Logic
LEA0–LEA7
13
LDAC
D
5A
LEA5
13
D
6A
LEA6
13
D
7A
LEA7
Q
LE
D
0B
Q
LE
1B
Q
LE
2B
Q
LE
3B
Q
LE
4B
Q
LE
5B
Q
LE
6B
Q
LE
7B
Q
LE
13
RGND23 RGND01
-
+
DAC0
LDAC
Q
LE
D
13
-
+
DAC1
VOUT0
VOUT1
LDAC
Q
LE
D
13
-
+
DAC2
LDAC
Q
LE
D
-
13
DAC3
+
DAC4
+
VOUT2
VOUT3
LDAC
Q
LE
D
13
-
VOUT4
LDAC
Q
LE
D
13
+
DAC5
-
VOUT5
LDAC
Q
LE
D
13
+
DAC6
-
VOUT6
LDAC
Q
LE
D
13
+
DAC7
-
LDAC
VREFT2345 VREFB2345 VREFT67 VREFB67
CLR
RGND45 RGND67
VOUT7
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VCC ........................................................................ +6 V
VDD ...................................................................... +15 V
VSS ...................................................................... –15 V
Temperature
Operating Temperature .......................... –40 to +85 °C
Storage ................................................ –65 to +150 °C
Input Voltages
VREFT .................................... VSS –0.3 V to VDD +0.3 V
VREFB ................................... VDD +0.3 V to VSS –0.3 V
Digital inputs ....................................–0.3 V to VCC +0.3 V
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VCC = +5.0 V, VDD = +11.5 V, VSS = –8.0 V, VREFT=3.5 V, VREFB = –1.5 V, RL = +10 kΩ, CL = 50 pF, unless otherwise specified.
TEST
LEVEL
MIN
Accuracy
Resolution
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
Zero-Scale Error
Full Scale Error
Gain Error
VI
VI
VI
VI
VI
VI
13
–2.0
–1.0
–25
–25
–25
Reference Inputs
Input Current
VREFT1
VREFB2
IV
VI
VI
0
–5.0
RGND Inputs
DC Input Impedance
Input Range
V
IV
–2.0
Output Characteristics
Output Swing3,4
Short Circuit Current
Resistive Load
DC Output Impedance
VI
IV
VI
IV
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current
Input Capacitance
VI
VI
VI
V
PARAMETERS
TEST
CONDITIONS
SPT5420
TYP
±0.5
±0.3
+3.5
–1.5
MAX
UNITS
+2.0
+1.0
+25
+25
+25
Bits
LSB
LSB
mV
mV
mV
±100
+5.0
0
nA
V
V
2.0
kΩ
V
60
+7/–3
15
5
1.0
2.4
0.8
10
–10
10
V
mA
kΩ
Ω
V
V
µA/pin
pF
Notes:
1. VREFT < 8 V + (VSS x 0.5); e.g., if VSS = –8 V, then VREFT < 4 V
2. VREFB > (VDD x 0.5) – 9.5 V; e.g., if VDD = 11 V, then VREFB > –4 V
3. VSS + 2.5 V ≤ VOUT ≤ VSS + 16.0 V for 18.5 V ≤ VDD – VSS ≤ 20.0 V
VSS + 2.5 V ≤ VOUT ≤ VDD – 2.5 V for VDD – VSS ≤ 18.5 V
4. VOUT = 2 X (VREFB +[VREFT – VREFB] X
INPUT CODE
8192
) – VRGND
SPT5420
2
6/26/01
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VCC = +5.0 V, VDD = +11.5 V, VSS = –8.0 V, VREFT=3.5 V, VREFB=–1.5 V, RL = +10 kΩ, CL = 50 pF, unless otherwise specified.
PARAMETERS
Power Requirements
VCC Supply Voltage (Digital)
VDD Supply Voltage (Analog)1,2
VSS Supply Voltage (Analog)1,2
ICC Supply Current
IDD Supply Current
ISS Supply Current
Power Supply Rejection Ratio
TEST
CONDITIONS
TEST
LEVEL
IV
VI
VI
VI
VI
VI
IV
IV
Outputs Unloaded
Outputs Unloaded
∆VDD / ∆Full Scale
∆VSS / ∆Full Scale
Dynamic Performance
Output Settling Time3
(Full Scale Change to ±0.5 LSB) CL ≤ 220 pF
Slew Rate
Glitch Impulse
Channel to Channel Isolation
DAC to DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
IV
V
V
V
V
V
V
Timing Characteristics
(See page 4)
IV
MIN
SPT5420
TYP
4.75
5
–12.5
5
11.5
–8
5
5
80
80
MAX
UNITS
5.25
12.5
–5
0.5
10
10
V
V
V
mA
mA
mA
dB
dB
15
2.0
35
100
40
1
1
µs
V/µs
nV-s
dB
nV-s
nV-s
nV-s
1. Supplies should provide 2.5 V headroom above and below max output swing.
2. VDD – VSS ≤ 20 V
3. Output can drive 10,000 pF without oscillation, but with settling time degradation.
DEFINITION OF SELECTED TERMINOLOGY
Channel-to-Channel Isolation
Channel-to-Channel isolation refers to the proportion of input signal from one DAC’s reference input that appears at the output of
the other DAC. It is expressed in dBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that appears at one DAC’s output due to both the digital change and subsequent analog output change at any other DAC. It is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to one DAC’s output due to a change in digital input code of any other DAC. It is specified in nV-s.
Digital Feedthrough
Digital feedthrough is the noise at a DAC’s output caused by changes to D0–D12 while WR is high.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT5420
3
6/26/01
TIMING CHARACTERISTICS
Figure 1a – Timing Diagram: Latched Mode
(LDAC Strobed)
t1
Figure 1b – Timing Diagram: Transparent Mode
(LDAC Held Low)
t2
A0–A2
A0–A2
t3
CS
t3
CS
t5
WR
t2
t1
t5
t6
t4
t6
t4
WR
t7
t7
t8
t8
D0–D12
D0–D12
t9
t9
VOUT
VOUT
t10
t11
LDAC
CLR
t9
VOUT
PARAMETER
SYMBOL
MIN
TYP
Address Valid to WR Setup
t1
20
Address Valid to WR Hold
t2
0
CS Pulse Width Low
t3
50
WR Pulse Width Low
t4
50
CS to WR Setup
t5
0
WR to CS Hold
t6
0
Data Setup
t7
25
Data Hold
t8
0
Settling Time1
t9
LDAC Pulse Width Low
t10
50
CLR Pulse Activation
t11
NOTES:
All digital input rise and fall times are measured from 10%
tr = tf = 5 ns.
1. RL = 10 kΩ
CL ≤ 220 pF
MAX
15
300
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
to 90% of +5 V.
SPT5420
4
6/26/01
VOLTAGE REFERENCES AND
ANALOG GROUND INPUTS
ANALOG OUTPUTS VS DIGITAL INPUT
CODE
Three VREFTXX and three VREFBXX inputs set the output
range of the three corresponding groups of DACs
(0 and 1; 2 through 5; 6 and 7). Four RGNDXX inputs set
the output offset voltage of the four corresponding groups
of DACs (0 and 1; 2 and 3; 4 and 5; 6 and 7). The formula
for output swing and offset is presented in the “Analog
Outputs” section below.
The output voltage range is equal to twice the difference
between VREFTXX and VREFBXX. The output voltage is
given by:
VOUT = 2 X (VREFB +[VREFT – VREFB] X
INPUT CODE
8192
) – VRGND
CODE = 0 – 8191
DAC ADDRESSING AND LATCHING
Table I – DAC Addressing
Each DAC has an input latch which receives data from the
data bus, and a DAC latch which receives data from the
input latch. The analog output of each DAC corresponds
to the data in its DAC latch. One of the eight input latches
is addressed by the address lines A(2:0) according to
Table I. While CS and WR are low, the addressed input
latch is transparent and the seven other input latches are
latched. Bringing CS or WR high latches data into the addressed input latch. While LDAC is low, all eight DAC
latches are transparent. Bringing LDAC high latches data
into the DAC latches. While CS, WR and LDAC are low, both
latches are transparent and input data is transferred
directly to the selected DAC. While CLR is low, all DAC outputs are set to their corresponding RGNDXX. Bringing CLR
high returns each DAC’s output to the voltage corresponding to the data in each DAC latch.
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
Addressed Input
Latch DAC#
0
1
2
3
4
5
6
7
A0
0
1
0
1
0
1
0
1
Table II – Control Logic Table
Table II summarizes this information, and figures 1a and
1b should be referenced for timing limitations.
POWER SUPPLY SEQUENCING
WR
CS
LDAC
CLR
0
1
x
x
x
x
0
x
1
x
x
x
x
x
x
0
1
x
1
1
1
1
1
0
Input Latch DAC Latch
transparent1
x
latched
x
latched
x
x
transparent
x
latched
DAC outputs at RGNDXX
Note:
1. Only the input latch addressed by A(2:0) is transparent.
The other input latches are latched.
The sequence in which VDD, VSS and VCC come up is not
critical. The reference inputs, VREFTXX and VREFBXX, must
come on only after VDD and VSS have been established.
However, they may be turned on prior to VCC. The digital
inputs must be driven only after VDD, VSS and VCC have
been established. Reverse the power-on sequence for
power-down.
SPT5420
5
6/26/01
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Linearity Error vs Code
Differential Linearity Error vs Code
0.20
1.00
0.80
0.00
0.60
–0.20
DLE (LSBs)
ILE (LSBs)
0.40
0.20
0.00
–0.20
–0.40
–0.60
–0.40
–0.80
–0.60
–0.80
–1.00
–1.00
0
1440
2880
4320
Code
5760
0
IDD
ISS
6
5760
7200
Load Capacitance vs Settling Time
Capacitance (pF)
Supply Current (mA)
7
4320
10000
VREFT=+5 V
VREFB=–5 V
VDD=12 V
VSS=–8 V
2880
Code
IDD/ISS vs Temperature
8
1440
7200
5
VSWING=10 V
1000
100
10
1
11.20
11.70
12.20
13.90
17.90
26.50
52.00
70.00
Settling Time to ±0.5 LSB (µS)
4
–40
0
25
70
85
Temperature °C
Digital-to-Analog Glitch Impulse
DAC to DAC Crosstalk
code 0FFFH to 1000H
code 0FFFH to 1000H
2 mV/div
DAC to DAC glitch
output glitch
2 V/div
2 mV/div
WR
2 µS
2 µS
SPT5420
6
6/26/01
TYPICAL PERFORMANCE CHARACTERISTICS
Slew and Settling Time
Digital Feedthrough
CL=50 pF
RL=10 kW
output
20 mV/div
code 0FFFH to 1000H
2 mV/div
digital feedthrough
output
2 V/div
code 0000H to 1FFFH
2 µS
1 µS
PACKAGE OUTLINE
44-Lead MQFP
A
B
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
Pin 1
Index
C
E
D
INCHES
MIN
MAX
0.5098
0.5295
0.3917
0.3957
0.3917
0.3957
0.5098
0.5295
0.0311
0.0319
0.0118
0.0177
0.0768
0.0827
0.0039
0.0098
0.0287
0.0406
0.0630 REF
0°
7°
MILLIMETERS
MIN
MAX
12.95
13.45
9.95
10.05
9.95
10.05
12.95
13.45
0.79
0.81
0.30
0.45
1.95
2.10
0.10
0.25
0.73
1.03
1.60 REF
0°
7°
F
G
K
I
H
J
SPT5420
7
6/26/01
CLR
(Active Low) Analog Clear. Sets the output
voltages to RGND. (Each RGND is common to a
DAC pair.) CLR does not reset the digital latches.
When CLR is brought back high, the DAC outputs
revert back to their original outputs as determined
by the data in their DAC latches.
LDAC
When this logic input is taken low, the contents of
the input latches are transferred to their respective
DAC latches. (Active Low) Data is latched on
rising edge.
VREFT67
VSS
A0 – A2
Addresses DAC0 to DAC7 for loading the eight
input latches.
CLR
D12 (MSB)
D11
D10
D9
D8
D0 – D12
Digital Inputs (D0 = LSB)
VDD
VOUT4
RGND45
VOUT5
VOUT6
VREFT2345
VOUT1
VOUT2
RGND23
VOUT3
VREFB2345
PIN ASSIGNMENTS
44
RGND01
VOUT0
VREFB01
1
RGND67
VOUT7
VREFB67
VREFT01
VDD
VSS
Top View
LDAC
A2
A1
A0
CS
ANALOG PINS
VREFT01
Top Reference Voltage for DACs 0 and 1
VREFT2345 Top Reference Voltage for DACs 2, 3, 4 and 5
VREFT67
Top Reference Voltage for DACs 6 and 7
VREFB01
Bottom Reference Voltage for DACs 0 and 1
D5
D6
D7
WR
VCC
GND
D0 (LSB)
D1
D2
D3
D4
VREFB2345 Bottom Reference Voltage for DACs 2, 3, 4 and 5
PIN FUNCTIONS
Name
Function
DIGITAL CONTROL PINS
VREFB67
Bottom Reference Voltage for DACs 6 and 7
RGND01
Reference Ground for Output Amplifiers 0 and 1
RGND23
Reference Ground for Output Amplifiers 2 and 3
RGND45
Reference Ground for Output Amplifiers 4 and 5
RGND67
Reference Ground for Output Amplifiers 6 and 7
VOUT0–7
Output Voltage Pins for DAC0 – DAC7
POWER SUPPLY PINS
CS
Chip Select (Active Low)
VCC
Digital +5 V Supply
WR
Level Triggered Write Input (Active Low). Used in
conjunction with CS to write data to the SPT5420
input data latches. Data is latched into selected
input data latch on the rising edge of WR.
VDD
Analog +11.5 V Supply (Nominal)
VSS
Analog –8 V Supply (Nominal)
GND
Ground
ORDERING INFORMATION
PART NUMBER
SPT5420SIM
TEMPERATURE RANGE
PACKAGE
–40 to +85 °C
44L MQFP
SPT5420
8
6/26/01