C9530 PCIX I/O System Clock Generator with EMI Control Features Table 1. Test Mode Logic Table[1] Features • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter Input Pins OEA SA1 Output Pins SA0 CLKA • Input clock frequency of 25 MHz to 33.3 MHz OEB SB1 SB0 CLKB REF • Output frequencies of XINx1, XINx2, XINx3 and XINx4 HIGH LOW LOW XIN XIN • Output grouped in two banks of five clocks each HIGH LOW HIGH 2 * XIN XIN • One REF XIN clock output HIGH HIGH LOW 3 * XIN XIN • SMBus clock control interface for individual clock disabling and SSCG control and individual back frequency selection HIGH HIGH HIGH 4 * XIN XIN LOW X X Three-state Three-state • Output clock duty cycle is 50% (± 5%) • < 250 ps skew between output clocks within a bank • Output jitter < 250 psec (175 psec with all outputs at the same frequency) • Spread Spectrum feature for reduced electromagnetic interference (EMI) • OE pins for entire output bank enable control and testability • 48-pin SSOP and TSSOP packages Pin Configuration Block Diagram REF 1 48 SDATA VDD 2 47 SCLK XIN 3 46 VDD XOUT 4 45 VSS CLKA0 VSS 5 44 VDD CLKA1 SA0 6 SA1 7 43 42 SB1 AGOOD# SSCG# SSCG Logic /N 1 0 XIN 0 SDATA SCLK IA(0:2) SA(0,1) SB(0,1) /N 1 I2C Control Logic CLKB1 CLKB2 CLKB3 CLKB4 OEB BGOOD# REF VSS 8 41 VSS CLKA0 9 40 CLKB0 CLKA1 10 39 CLKB1 VDDA 11 CLKA2 12 C9530 XOUT CLKA2 CLKA3 CLKA4 OEA CLKB0 SB0 38 VDDB 37 CLKB2 VSS 13 36 VSS VDDA 14 35 VDDB CLKA3 15 34 CLKB3 CLKA4 16 33 CLKB4 VSS 17 32 VSS AGOOD# 18 31 BGOOD# VSS 19 30 AVDD IA0 20 29 AVDD IA1 21 28 VSS IA2 22 27 SSCG# AVDD 23 26 VSS OEA 24 25 OEB Note: 1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state REF. Cypress Semiconductor Corporation Document #: 38-07033 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 31, 2005 C9530 Pin Description[3] Pin[2] Name PWR[4] I/O Description 3 XIN VDDA I Crystal Buffer input pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. 4 XOUT VDDA O Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is used or in Test mode, this pin is kept unconnected. 1 REF VDD O Buffered inverted outputs of the signal applied at Xin, typically 33.33 or 25.0 MHz 24* OEA VDD I Output Enable for clock bank A. Causes the CLKA output clocks to be in a three-state condition when driven to a logic low level. 25* OEB VDD I Output Enable for clock bank B. Causes the CLKB output clocks to be in a three-state condition when driven to a logic low level. 18 AGOOD# VDD O When this output signal is a logic low level, it indicates that the output clocks of the A bank are locked to the input reference clock. This output is latched. 31 BGOOD# VDD O When this output signal is at a logic low level, it indicates that the output clocks of the B bank are locked to the input reference clock. This output is latched. 6*, 7* SA(0,1) VDD I Clock Bank A selection bits. These control the clock frequency that will be present on the outputs of the A bank of buffers. See Table 1 for frequency codes and selection values. 43*, 42* SB(0,1) VDD I Clock Bank B selection bits. These control the clock frequency that will be present on the outputs of the B bank of buffers. See Table 1 for frequency codes and selection values. 20*, 21*, 22* IA(0:2) VDD I SMBus address selection input pins. See Table 3 SMBus Address table. 27* SSCG# VDD I Enables Spread Spectrum clock modulation when at a logic low level, see Spread Spectrum Clocking on page 6. 48 SDATA VDD I/O Data for the internal SMBus circuitry. 47 SCLK VDD I Clock for the internal SMBus circuitry. 11, 14 VDDA – PWR 3.3V common power supply pin for Bank A PCI clocks CLKA. 38, 35 VDDB – PWR 3.3V common power supply pin for Bank B PCI clocks CLKB. 2, 44, 46 VDD – PWR Power supply for internal Core logic. 23, 29, 30 AVDD – PWR Power for internal analog circuitry. This supply should have a separately decoupled current source from VDD. 9, 10, 12, 15, 16 CLKA (0:4) VDDA O A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks. 40, 39, 37, 34, CLKB (0:4) VDDB 33 O A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks. 5, 8, 13, 17, 19, 26, 28, 32, 36, 41, 45 VSS – PWR Ground pins for the device. Notes: 2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. 3. A bypass capacitor (0.1 µF) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the trace. 4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s). Document #: 38-07033 Rev. *C Page 2 of 11 C9530 Serial Data Interface Table 2. Block Read and Block Write Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol Block Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 Command Code – 8 bits ‘00000000’ stands for block operation 19 The clock driver serial protocol accepts block write a operations from the controller. The bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The C9530 does not support the Block Read function. The block write protocol is outlined in Table 2. The addresses are listed in Table 3. Acknowledge from slave 20:27 Byte Count – 8 bits 28 Acknowledge from slave 29:36 Data byte 1 – 8 bits 37 Acknowledge from slave 38:45 Data byte 2 – 8 bits 46 Acknowledge from slave .... ...................... .... Data Byte (N–1) – 8 bits .... Acknowledge from slave .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop Table 3. SMBus Address Selection Table SMBus Address of the Device IA0 Bit (Pin 10) IA1 Bit (Pin 11) IA2 Bit (Pin 12) DE 0 0 0 DC 1 0 0 DA 0 1 0 D8 1 1 0 D6 0 0 1 D4 1 0 1 D0 0 1 1 D2 1 1 1 Serial Control Registers Byte 0: Function Select Register Bit @Pup Name 7 1 TESTEN 6 0 SSEN Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to a 0) 0 = OFF, 1= ON 5 1 SSSEL SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification 4 0 S1 SB1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) 3 0 S0 SB0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) 2 0 Document #: 38-07033 Rev. *C Description Test Mode Enable. 1 = Normal operation, 0 = Test mode SA1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) Page 3 of 11 C9530 Byte 0: Function Select Register (continued) Bit @Pup 1 0 0 1 Name Description HWSEL Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, 42, 43 and 27), 0 = SMBus Byte 0 bits 1-4, & 6 SA0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) Table 4. Clarification Table for Byte0, bit 5 Byte0, bit6 Byte0, bit5 0 0 Description Frequency generated from second PLL 0 1 Frequency generated from XIN 1 0 Spread @ –1.0% 1 1 Spread @ –0.5% Table 5. Test Table Outputs Test Function Clock CLKA CLKB REF Frequency XIN/6 XIN/4 XIN Byte 1: A Bank and REF Clock Control Register Bit @Pup Name 7 1 Reserved 6 1 Reserved 5 1 4 1 CLKA4 Output Enable 0 = Disable, 1= Enable 3 1 CLKA3 Output Enable 0 = Disable, 1= Enable 2 1 CLKA2 Output Enable 0 = Disable, 1= Enable 1 1 CLKA1 Output Enable 0 = Disable, 1= Enable 0 1 CLKA0 Output Enable 0 = Disable, 1= Enable REFEN Description REF Output Enable 0 = Disable, 1= Enable Byte 2: PCI Register Bit @Pup 7 1 Reserved 6 1 Reserved 5 1 Reserved 4 1 18 CLKB4 Output Enable 0 = Disable, 1= Enable 3 1 19 CLKB3 Output Enable 0 = Disable, 1= Enable 2 1 22 CLKB2 Output Enable 0 = Disable, 1= Enable 1 1 23 CLKB1 Output Enable 0 = Disable, 1= Enable 0 1 24 CLKB0 Output Enable 0 = Disable, 1= Enable Document #: 38-07033 Rev. *C Name Description Page 4 of 11 C9530 Table 6. Suggested Oscillator Crystal Parameters Parameter Description Fo Frequency TC Tolerance TS TA Conditions Min Typ. Max. Unit 33.0 33.33 33.5 MHz See Note 5 – – ±100 PPM Stability (TA –10 to +60C) Note 5 – – ±100 PPM PPM Aging (first year @ 25C) Note 5 – – 5 Operating Mode Parallel Resonant, Note 5 – – – CXTAL Load Capacitance The crystal’s rated load. Note 5 – 20 – pF RESR Effective Series Resistance (ESR) Note 6 – 40 – Ohms Internal Crystal Oscillator Output Clock Frequency Control This device will operate in two input reference clock configurations. In its simplest mode a 33.33-MHz fundamental cut parallel resonant crystal is attached to the XIN and XOUT pins. All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of these control signals is determined by the SMBus register Byte 0 bit 0. At initial power-up this bit is set of a logic 1 state and thus the frequency selections are controlled by the logic levels present on the device’s S(0,1) pins. If the application does not use an SMBus interface then hardware frequency selection S(0,1) must be used. If it is desired to control the output clocks using an SMBus interface, then this bit (B0b0) must first be set to a low state. After this is done the device will use the contents of the internal SMBus register Bytes 0 Bits 3 and 4 to control the output clock’s frequency. In the second mode a 33.33-MHz input reference clock is driven in on the IN clock from an external source. In this application the XOUT pin must be left disconnected. Output Clock Three-state Control All of the clocks in Bank A (CLKA) and Bank B (CLKB) may be placed in a three-state condition by bringing their relevant OE pins (OEA and OEB) to a logic LOW state. This transition to and from a state and active condition is a totally asynchronous event and clock glitching may occur during the transitioning states. This function is intended as a board level testing feature. When the output clocks are being enabled and disabled in active environments the SMBus control register bits are the preferred mechanism to control these signals in an orderly and predictable manner. CL = The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal (CXINPCB + CXINFTG + CXINDISC) x (CXOUTPCB) + CXOUTFTG) + CXOUTDISC) (CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB) + CXOUTFTG) + CXOUTDISC) where: CXTAL = The load rating of the crystal. CXINFTG = The clock generators XIN pin effective device internal capacitance to ground. CXOUTFTG = The clock generators XOUT pin effective device internal capacitance to ground. CXINPCB = The effective capacitance to ground of the crystal to device PCB trace. CXOUTPCB = The effective capacitance to ground of the crystal to device PCB trace. CXINDISC = Any discrete capacitance that is placed between the XIn pin and ground. CXOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground. Notes: 5. For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifications. 6. Larger values may cause this device to exhibit oscillator startup problems. Document #: 38-07033 Rev. *C Page 5 of 11 C9530 Spread Spectrum Clocking Down Spread Description XIN CXINPCB CXINDISC CXOUTPCB CXOUTDISC CXINFTG XOUT CXOUTFTG Clock Generator As an example and using this formula for this data sheet’s device, a design that has no discrete loading capacitors (CDISC) and each of the crystal device PCB traces has a capacitance (CPCB) to ground of 4 pF (typical value) would calculate as follows. Therefore, to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20 pF. CL = Spread Spectrum is a modulation technique for distributing clock period over a certain bandwidth (called Spread Bandwidth). This technique allows the distribution of the undesirable electromagnetic energy (EMI) over a wide range of frequencies therefore reducing the average radiated energy present at any frequency over a given time period. As the spread is specified as a percentage of the resting (non-spread) frequency value, it is effective at the fundamental and, to a greater extent, at all it's harmonics. In this device, Spread Spectrum is enabled externally through pin 27 (SSCG#) or internally via SMBus Byte 0 Bit 0 and 6. Spread spectrum is enabled externally when the SSCG# pin is low. This pin has an internal device pull up resistor, which causes its state to default to a high (Spread Spectrum disabled) unless externally forced to a low. It may also be enabled by programming SMBus Byte 0 Bit 0 LOW (to enable SMBus control of the function) and then programming SMBus Byte 0 Bit 6 LOW to set the feature active. (4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF) (4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF) = 40 x 40 40 x 40 = 1600 80 = 20 pF S p re a d o ff S p re a d o n C e n te r F re q u e n c y , S p re a d o ff C e n te r F re q u e n c y , S p re a d o n Figure 1. Spread Spectrum Table 7. Spectrum Spreading Selection Table[7] % of Frequency Spreading Output Clock Frequency SMBus Byte 0 Bit 5 = 0 SMBus Byte 0 Bit 5 = 1 Mode 33.3 MHz (XIN) 1.0% (–1.0% + 0%) 0.5% (–0.5% + 0%) Down Spread 66.6 MHz (XIN*2) 1.0% (–1.0% + 0%) 0.5% (–0.5% + 0%) Down Spread 100.0 MHz (XIN*3) 1.0% (–1.0% + 0%) 0.5% (–0.5% + 0%) Down Spread 133.3 MHz (XIN*4) 1.0% (–1.0% + 0%) 0.5% (–0.5% + 0%) Down Spread Note: 7. When SSCG is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. This means that for a 100-MHz output clock frequency will sweep through a spectral range from 99 to 100 MHz. Document #: 38-07033 Rev. *C Page 6 of 11 C9530 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD,VDDP Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to V SS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) UL–94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level 2000 – V 15 °C/W 45 °C/W V–0 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition Min. Max. Unit 3.135 3.465 V VDD, VDDA, VDDB 3.3 Operating Voltage 3.3V ± 5% VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – – S(A,B)O, S(A,B)1, OE(A,B) VIL Input Low Voltage VIH Input High Voltage VSS – 0.5 0.8 V 2.0 VDD + 0. 5 V IIL Input Leakage Current except pull-ups or pull-downs 0 < VIN < VDD –5 5 µA VOL Output Low Voltage IOL = 1 mA – 0.4 V VOH Output High Voltage IOH = –1 mA 2.4 – V IOZ High-Impedance Output Current –10 10 µA CIN Input Pin Capacitance 2 5 pF COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH CXTAL Crystal Pin Capacitance 32 38 pF VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDD Dynamic Supply Current At 133 MHz and all outputs loaded per Table 8 – 300 mA IPD Power-down Supply Current PD# Asserted – 1 mA Condition Min. Max. Unit From XIN and XOUT pins to ground AC Electrical Specifications Parameter Description Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70%. 45 55 % XINFREQ XIN Frequency When Xin is driven from an external clock source 25 33.3 MHz Document #: 38-07033 Rev. *C Page 7 of 11 C9530 AC Electrical Specifications (continued) Min. Max. Unit TR / TF Parameter XIN Rise and Fall Times Description Measured between 0.3VDD and 0.7VDD Condition – 10.0 ns TCCJ XIN Cycle to Cycle Jitter As an average over 1µs duration – 500 ps LACC Long-term Accuracy Over 150 ms 300 ppm CLK TDC CLK Duty Cycle Measurement at 1.5V 45 55 % TPERIOD33 33MHz CLK Period Measurement at 1.5V 29.5 30.5 ns TPERIOD66 66MHz CLK Period Measurement at 1.5V 14.5 15.5 ns TPERIOD100 100MHz CLK Period Measurement at 1.5V 9.5 10.5 ns TPERIOD133 133MHz CLK Period Measurement at 1.5V 7.0 8.0 ns TR / TF CLK Rise and Fall Times Measured between 0.4V and 2.4V 0.5 2.0 ns TSKEW Any CLK to Any CLK Clock Skew Measurement at 1.5V – 250 ps TCCJ CLK Cycle to Cycle Jitter Measurement at 1.5V – 175 ps REF TDC REF Duty Cycle Measurement at 1.5V 45 55 % TR / TF REF Rise and Fall Times Measured between 0.4V and 2.4V 1.0 4.0 ns TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 750 ps ENABLE/DISABLE and SET-UP tpZL,tpZH Output Enable Delay (all outputs) – 10.0 ns tpLZ,tpZH Output Disable Delay (all outputs) – 10.0 ns TSTABLE Clock Stabilization from Power-up – 3.0 ms Test and Measurement Set-up 3 . 3 V S ig n a ls tD C - - Output under Test 3 .3 V Probe 2 .4 V Load Cap 1 .5 V 0 .4 V 0V Tr Lumped Load Tf LVTTL Signaling Figure 2. Test and Measurement Set-up Table 8. Loading Output Name Max Load (in pF) CLK5 30 REF 20 Document #: 38-07033 Rev. *C Page 8 of 11 C9530 Ordering Information Part Number IMIC9530CY IMIC9530CYT IMIC9530CT IMIC9530CTT Lead-free CYI9530ZXC CYI9530ZXCT Document #: 38-07033 Rev. *C Package Type 48-Pin SSOP 48-Pin SSOP – Tape and Reel 48-Pin TSSOP 48-Pin TSSOP – Tape and Reel Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C 48-Pin TSSOP 48-Pin TSSOP – Tape and Reel Commercial, 0° to 70°C Commercial, 0° to 70°C Page 9 of 11 C9530 Package Diagrams 48-lead Shrunk Small Outline Package O48 51-85061-*C 48-lead (240-mil) TSSOP II Z4824 0.500[0.019] 24 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 7.950[0.313] 8.255[0.325] REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms 5.994[0.236] 6.198[0.244] PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 25 48 12.395[0.488] 12.598[0.496] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° 0.508[0.020] 0.762[0.030] SEATING PLANE 0.100[0.003] 0.200[0.008] 51-85059-*C All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07033 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. C9530 Document History Page Document Title: C9530 PCIX I/O System Clock Generator with EMI Control Features Document #: 38-07033 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106961 06/12/02 IKA Convert from IMI to Cypress *A 122726 12/17/02 RBI Added power-up requirements to maximum ratings information *B 126595 05/14/03 RGL Converted from Word to FrameMaker Fixed AC and DC tables to match char data Added 25-MHz Operation. *C 404563 See ECN RGL Added Pb-free devices for TSSOP Document #: 38-07033 Rev. *C Page 11 of 11