SL28DB200 100 MHz Differential Buffer for PCI Express and SATA Features • Two differential 0.7V clock output pairs • OE# input for enabling SRC outputs • Individual OE controls Functional Description The SL28DB200 is a differential buffer capable of distributing the Serial Reference Clock (SRC) for PCI Express Gen2 and SATA implementations. The buffer enables the application system to control the distribution of the SRC. • Low CTC jitter (< 50 ps) • Spread Aware • 3.3V operation • Industrial Temperature Grade -40oC to +85oC • 16-pin TSSOP package Applications • Network/Media Attached Storage • Routers/IP Gateways • Multi-function Printers Block Diagram Pin Configuration 16 TSSOP .........................Document #: 38-07722 Rev 0.4 Page 1 of 8 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL28DB200 Pin Description Pin Name Type Description 2,3 SRCIN, SRCIN# I,DIF 5,6,13,12 SRC[1:2], SRC[1:2]# O,DIF 0.7V Differential Clock Outputs I,SE 0.7V Differential inputs 7,11 OE[1:2]# 15 IREF I 3.3V LVTTL input for enabling differential outputs 1 VDDA PWR 3.3V Power Supply A precision resistor 475 ohmis attached to this pin to set the differential output current 16 VSSA GND Ground 8,10,14 VDD PWR 3.3V power supply for outputs 4,9 VSS GND Ground for outputs Notes: I=Input, O=Output, DIF=Differential signal, SE=Single Ended, PWR=Power input, GND=Ground Table 1. Buffer Power-up State Machine State S0 Description 3.3V Buffer power off S1 After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay S2 Buffer waits for a valid clock on the SRCIN input S3 Once a valid input is detected, the buffer enters state 3 and enables outputs for normal operation Figure 1. Buffer Power-up State Diagram ........................ Document #: 38-07722 Rev 0.4 Page 2 of 8 SL28DB200 Output Enable Clarification OE Deassertion OE# functionality allows for enabling and disabling individual outputs. OE1# and OE2# are Active LOW inputs. Disabling the outputs may be implemented by deasserting the OE# input pin. If the OE# pin is deasserted, the output of interest will be tri-stated. (The assertion and deassertion of this signal is absolutely asynchronous.) The impact of deasserting OE# is that each corresponding output will transition from normal operation to tri-state in a glitch-free manner. The maximum latency from the deassertion to tri-stated outputs is between 2–6 DIF clock periods. OE Assertion Table 2. OE Functionality All differential outputs that were tri-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 SRC clock periods. In addition, SRC clocks will be driven high within 15 ns of OE# assertion to a voltage greater than 200 mV OE# SRC,SRC# 0 Enable 1 Tri-State Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient (Commercial Grade) Functional 0 85 °C TA Temperature, Operating Ambient (Industrial Grade) Functional -40 85 °C TJ Temperature, Junction Functional 150 °C ESDHBM ESD Protection (Human Body Model) JEDEC (JESD 22 - A114) – V UL-94 Flammability Rating UL (Class) 2000 V–0 DC Electrical Specifications Parameter Description VDDA, VDD 3.3V Operating Voltage VIL 3.3V Input Low Voltage Condition 3.3 ± 5% Min. Max. Unit 3.135 3.465 V VSS – 0.5 0.8 V 2.0 VDD + 0.5 VIH 3.3V Input High Voltage IIL Input Low Leakage Current except internal pull-up resistors, 0 < VIN < VDD IIH Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD 5 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance –- 6 pF LIN Pin Inductance – 7 nH IDD3.3V Dynamic Supply Current – 60 mA At max. load, Full Active, at 100MHz ........................ Document #: 38-07722 Rev 0.4 Page 3 of 8 V A –5 SL28DB200 AC Electrical Specifications All measurements at VDD (typical) = 3.3V, TA = 25oC unless otherwise stated Parameter Description Condition Min. Max. Unit Measured at crossing point VOX 9.9970 10.0533 ns TABSMIN-IN Absolute minimum clock periods Measured at crossing point VOX 9.8720 T R / TF SRC and SRC# Rise and Fall Times Single ended measurement: VOL = 0.175 to VOH = 0.525V (Averaged) 4 V/ns VIH Differential Input High Voltage VIL Differential Input Low Voltage VOX Crossing Point Voltage at 0.7V Swing Single-ended measurement VOX Vcross Variation over all edges Single-ended measurement VRB SRCIN at 0.7V TPERIOD Average Period 0.6 ns 150 mV –150 mV 250 550 mV 140 mV Differential Ringback Voltage –100 100 mV TSTABLE Time before ringback allowed 500 VMAX Absolute maximum input voltage VMIN Absolute minimum input voltage TDC SRC and SRC# Duty Cycle Measured at crossing point VOX TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) ps 1.15 V 45 55 % – 20 % –0.3 V SRC at 0.7V FIN Input Frequency 90 210 MHz FERROR Input/Output Frequency Error – 0 ppm TDC SRC and SRC# Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD Average Period Measured at crossing point VOX at 100 MHz 9.9970 10.0533 ns T R / TF SRC[1:2] and SRC[1:2]# Rise and Fall Times Single-ended measurement: VOL = 0.175 to VOH = 0.525V (Averaged) 175 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2 * (TR – TF)/(TR + TF) – 20 % TR/TF Rise and Fall Time Variation Variation Single-ended measurement: VOL = 0.175 to VOH = 0.525V (Real Time) – 125 ps VHIGH Voltage High Single-ended measurement 660 850 mv VLOW Voltage Low Single-ended measurement –150 – mv VOX Crossing Point Voltage at 0.7V Swing Single-ended measurement 250 550 mv VOX Vcross Variation over all edges Single-ended measurement – 140 mV VOVS Maximum Overshoot Voltage Single-ended measurement – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage Single-ended measurement – –0.3 V VRB Ring Back Voltage Single-ended measurement 0.2 N/A V TCCJ Cycle to Cycle Jitter Jitter is additive – 50 ps TSKEW Any SRC/SRC# to SRC/SRC# Clock Skew Measured at crossing point VOX – 50 ps TPD Input to output skew Measured at crossing point VOX 2.5 4.5 ns ........................ Document #: 38-07722 Rev 0.4 Page 4 of 8 SL28DB200 Test and Measurement Setup Figure 1. Differential Clock Termination Switching Waveforms TRise (CLOCK) VOH = 0.525V CL OC K OC CL K# VCROSS VOL = 0.175V TFall (CLOCK) Figure 2. Single-Ended Measurement Points for TRise and TFall ........................ Document #: 38-07722 Rev 0.4 Page 5 of 8 SL28DB200 VOVS VRB VRB VLOW VUDS Figure 3. Single-ended Measurement Points for VOVS,VUDS and VRB TPERIOD High Duty Cycle % Low Duty Cycle % Skew Management Point 0.000V Figure 4. Differential (Clock-Clock#) Measurement Points (Tperiod, Duty Cycle and Jitter) Ordering Information Ordering Code Package Type Operating Range Lead-free SL28DB200AZC 16-pin TSSOP Commercial, 0°C to 85°C SL28DB200AZCT 16-pin TSSOP—(Tape and Reel) Commercial, 0°C to 85°C SL28DB200AZI 16-pin TSSOP Industrial, -40°C to 85°C SL28DB200AZIT 16-pin TSSOP—(Tape and Reel) Industrial, -40°C to 85°C Note: All oderables are Lead-free and RoHS compliant ........................ Document #: 38-07722 Rev 0.4 Page 6 of 8 SL28DB200 Package Drawing and Dimensions 16-Lead Thin Shrunk Small Outline Package ........................ Document #: 38-07722 Rev 0.4 Page 7 of 8 SL28DB200 Document History Page Document Title: SL28DB200 PCI Express Gen2 and SATA Differential Buffer Document #: 38-07722 Rev 0.4 REV. ECR# Issue Date Orig. of Change Description of Change 1.0 06/17/10 TRP Initial Release AA 09/27/10 TRP Updated Dynamic Supply Current The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. ........................ Document #: 38-07722 Rev 0.4 Page 8 of 8