NTMS4800N Power MOSFET 30 V, 8 A, N−Channel, SOIC−8 Features • • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses SOIC−8 Surface Mount Package Saves Board Space This is a Pb−Free Device http://onsemi.com V(BR)DSS Applications RDS(ON) MAX 20 mW @ 10 V 30 V • DC−DC Converters • Printers Drain−to−Source Voltage Gate−to−Source Voltage N−Channel Symbol Value Unit VDSS 30 V VGS ±20 V ID 6.4 A Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C PD 1.29 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID 4.9 A Steady State PD ID 0.75 W TA = 25°C Power Dissipation RqJA, t < 10 s (Note 1) TA = 25°C PD TA = 25°C, tp = 10 ms IDM 32 A TJ, Tstg −55 to +150 °C IS 2.0 A EAS 60.5 mJ TL 260 °C Value Unit RqJA 97 °C/W RqJA 62.5 TA = 70°C Operating Junction and Storage Temperature A 8.0 6.4 Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 11 Apk, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for t = 10 s) 2.0 W THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Ambient – Steady State (Note 1) Junction−to−Ambient – t < 10 s (Note 1) S MARKING DIAGRAM/ PIN ASSIGNMENT 3.9 Continuous Drain Current RqJA, t < 10 s (Note 1) Pulsed Drain Current G 5.1 TA = 70°C TA = 25°C D Symbol Junction−to−Foot (Drain) RqJF 25 Junction−to−Ambient – Steady State (Note 2) RqJA 167 1 SO−8 CASE 751 STYLE 12 4800N A Y WW G Source Source Source Gate 1 8 4800N AYWWG G Power Dissipation RqJA (Note 2) TA = 70°C 8A 27 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter ID MAX Drain Drain Drain Drain Top View = Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NTMS4800NR2G Package Shipping† SOIC−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 in sq pad, 1 oz Cu 2. Surface−mounted on FR4 board using the minimum recommended pad size © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 1 1 Publication Order Number: NTMS4800N/D NTMS4800N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 26 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance 1.5 3.0 5.0 gFS V mV/°C VGS = 10 V, ID = 7.5 A 12.5 20 mW VGS = 4.5 V, ID = 6.5 A 20 27 VDS = 1.5 V, ID = 7.5 A 21 S 940 pF CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 125 Total Gate Charge QG(TOT) 7.7 Threshold Gate Charge QG(TH) 1.1 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 15 V VGS = 4.5 V, VDS = 15 V, ID = 7.5 A 225 nC 3.3 3.2 VGS = 10 V, VDS = 15 V, ID = 7.5 A 15.2 nC td(on) 9.4 ns tr 4.0 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(off) VGS = 10 V, VDS = 15 V, ID = 1.0 A, RG = 6.0 W tf 21 6.5 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD VGS = 0 V, IS = 2.0 A TJ = 25°C 0.75 TJ = 125°C 0.59 tRR 17.8 Charge Time ta 8.3 Discharge Time tb Reverse Recovery Charge VGS = 0 V, dIS/dt = 100 A/ms, IS = 2.0 A 1.0 V ns 9.5 QRR 8.0 nC LS 0.66 nH 0.20 nH 1.5 nH PACKAGE PARASITIC VALUES Source Inductance Drain Inductance LD Gate Inductance LG Gate Resistance RG TA = 25°C 1.5 3. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 3.0 W NTMS4800N TYPICAL PERFORMANCE CURVES 4V 3.8 V 7.5 3.4 V 5 3.2 V 2.5 2.8 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 3.6 V ID, DRAIN CURRENT (AMPS) 10 12.5 TJ = 25°C 10V 4.5 V 0 0.5 1.0 3.0 V 1.5 2.0 10 7.5 5 TJ = 125°C 2.5 TJ = 25°C 2.5 2 1.5 3 2.5 4 3.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = 7.5 A 0.085 0.075 0.065 0.055 0.045 0.035 0.025 0.015 3 4 6 5 8 7 9 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C 0.025 0.015 VGS = 10 V 0.010 0.005 0 2 6 4 10 8 14 12 ID, DRAIN CURRENT (AMPS) 100000 VGS = 0 V ID = 7.5 A VGS = 10 V IDSS, LEAKAGE (nA) 1.4 VGS = 4.5 V 0.020 Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.6 1.5 4.5 0.030 Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1 TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.095 0.005 VDS ≥ 10 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 12.5 1.3 1.2 1.1 1.0 0.9 10000 TJ = 150°C 1000 0.8 TJ = 100°C 0.7 0.6 −50 −25 0 25 50 75 100 125 150 100 3 6 9 12 15 18 21 24 27 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 30 NTMS4800N C, CAPACITANCE (pF) 350 250 150 50 TJ = 25°C VGS = 0 V Ciss Coss Crss 0 5 10 15 20 25 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 30 10 9 VDS 8 12 6 5 8 3 4 2 ID = 7.5 A TJ = 25°C 1 0 2 0 8 12 6 10 4 QG, TOTAL GATE CHARGE (nC) 14 0 16 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 3 IS, SOURCE CURRENT (AMPS) VDS = 15 V ID = 1 A VGS = 10 V td(off) 100 t, TIME (ns) QGD QGS 4 1000 tf td(on) 10 tr 1 10 1 0.4 0.5 0.6 0.7 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 ms 1 ms 1 10 ms VGS = 20 V SINGLE PULSE TC = 25°C dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 10 0.01 0.1 2 RG, GATE RESISTANCE (OHMS) 10 ms 0.1 VGS = 0 V TJ = 25°C 0 0.3 100 100 ID, DRAIN CURRENT (AMPS) 16 VGS 7 Figure 7. Capacitance Variation 1 20 QT VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1350 1250 1150 1050 950 850 750 650 550 450 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES 75 ID = 11 A 50 25 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 0.8 150 NTMS4800N PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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