FAIRCHILD FDD6682

FDD6682/FDU6682
June 2004
FDD6682/FDU6682
30V N-Channel PowerTrench MOSFET
General Description
Features
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
low gate charge, low RDS( ON) and fast switching speed.
• 75 A, 30 V
RDS(ON) = 6.2 mΩ @ VGS = 10 V
RDS(ON) = 8.0 mΩ @ VGS = 4.5 V
• Low gate charge
• Fast switching
Applications
• High performance trench technology for extremely
low RDS(ON)
• DC/DC converter
• Motor Drives
D
D
G
S
I-PAK
(TO-251AA)
D-PAK
TO-252
(TO-252)
G D S
Absolute Maximum Ratings
Symbol
G
S
TA=25oC unless otherwise noted
Ratings
Units
VDSS
Drain-Source Voltage
Parameter
30
V
VGSS
Gate-Source Voltage
±20
ID
Drain Current
PD
Power Dissipation for Single Operation
– Continuous
– Pulsed
(Note 3)
75
(Note 1a)
100
(Note 1)
71
(Note 1a)
3.8
W
1.6
(Note 1b)
TJ, TSTG
A
Operating and Storage Junction Temperature Range
–55 to +175
°C
°C/W
Thermal Characteristics
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
2.1
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
40
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
96
Package Marking and Ordering Information
Device Marking
Device
Package
FDD6682
FDD6682
FDU6682
FDU6682
2004 Fairchild Semiconductor Corporation
Reel Size
Tape width
Quantity
D-PAK (TO-252)
13’’
12mm
2500 units
I-PAK (TO-251)
Tube
N/A
75
FDD6682/FDU6682 Rev H(W)
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
240
mJ
17
A
Drain-Source Avalanche Ratings (Note 2)
WDSS
Drain-Source Avalanche Energy
IAR
Drain-Source Avalanche Current
Single Pulse, VDD = 15 V, ID = 17 A
Off Characteristics
BVDSS
∆BVDSS
∆TJ
IDSS
IGSS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage
On Characteristics
VGS = 0 V,
ID = 250 µA
VDS = 24 V,
VGS = 0 V
VGS = ±20 V,
VDS = 0 V
ID = 250 µA
VDS = VGS,
ID = 250 µA, Referenced to 25°C
Static Drain–Source
On–Resistance
VGS = 10 V,
ID = 17 A
VGS = 4.5 V,
ID = 15 A
VGS = 10 V, ID = 17 A, TJ=125°C
ID(on)
On–State Drain Current
VGS = 10 V,
VDS = 5 V
gFS
Forward Transconductance
VDS = 5 V,
ID = 17 A
VDS = 15 V,
f = 1.0 MHz
V GS = 0 V,
VGS = 15 mV,
f = 1.0 MHz
∆VGS(th)
∆TJ
RDS(on)
V
20
mV/°C
1
±100
µA
nA
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
VGS(th)
30
ID = 250 µA, Referenced to 25°C
1
1.9
–7
5.2
6.4
8.0
3
V
mV/°C
6.2
8
11.9
50
mΩ
A
65
S
2400
pF
577
pF
258
pF
1.4
Ω
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
RG
Gate Resistance
Switching Characteristics
(Note 2)
td(on)
Turn–On Delay Time
14
20
ns
tr
Turn–On Rise Time
12
37
ns
td(off)
Turn–Off Delay Time
tf
Turn–Off Fall Time
Qg
Total Gate Charge
Qgs
Gate–Source Charge
Qgd
Gate–Drain Charge
VDD = 15 V,
VGS = 10 V,
VDS = 15V,
VGS = 5 V
ID = 1 A,
RGEN = 6 Ω
ID = 17 A,
38
64
ns
18
32
ns
24
31
nC
6.5
nC
8.1
nC
FDD6682/FDU6682 Rev H(W)
FDD6682/FDU6682
Electrical Characteristics
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min
Typ
Max
Units
3.2
A
0.7
1.2
V
Drain–Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain–Source Diode Forward Current
VSD
trr
Drain–Source Diode Forward
Voltage
Diode Reverse Recovery Time
Qrr
Diode Reverse Recovery Charge
VGS = 0 V,
IF = 17 A,
IS = 3.2 A
(Note 2)
diF/dt = 100 A/µs
32
nS
20
nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) RθJA = 40°C/W when mounted on a
2
1in pad of 2 oz copper
b) RθJA = 96°C/W when mounted
on a minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. Maximum current is calculated as:
PD
R DS(ON)
where PD is maximum power dissipation at TC = 25°C and RDS(on) is at TJ(max) and VGS = 10V. Package current limitation is 21A
FDD6682/FDU6682 Rev H(W)
FDD6682/FDU6682
Electrical Characteristics (continued)
FDD6682/FDU6682
Typical Characteristics
100
2
VGS = 3.5V
4.0V
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS=10V
80
6.0V
4.5V
3.5V
60
40
3.0V
20
1.8
1.6
4.0V
1.4
4.5V
5.0V
1.2
10V
1
0.8
0
0
1
2
0
3
20
40
Figure 1. On-Region Characteristics.
80
100
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
2
0.02
ID = 17A
VGS = 10V
1.8
RDS(ON), ON-RESISTANCE (OHM)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
60
ID, DRAIN CURRENT (A)
VDS, DRAIN-SOURCE VOLTAGE (V)
1.6
1.4
1.2
1
0.8
ID = 8.5A
0.015
TA = 125oC
0.01
TA = 25oC
0.005
0
0.6
-50
-25
0
25
50
75
100
125
150
2
175
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
o
TJ, JUNCTION TEMPERATURE ( C)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
80
100
VGS = 0V
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VDS = 5V
60
40
20
TA =125oC
25oC
-55oC
0
10
TA = 125oC
1
25oC
0.1
-55oC
0.01
0.001
0.0001
1
2
3
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
4
0
0.2
0.4
0.6
0.8
1
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature
FDD6682/FDU6682 Rev H(W)
3500
15V
CISS
3000
8
20V
6
4
2500
2000
COSS
1500
1000
CRSS
2
500
0
0
0
10
20
30
Qg, GATE CHARGE (nC)
40
50
0
Figure 7. Gate Charge Characteristics
5
10
15
20
25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 8. Capacitance Characteristics
1000
P(pk), PEAK TRANSIENT POWER (W)
100
100
100µs
RDS(ON) LIMIT
1ms
10ms
10
100ms
1s
10s
DC
1
VGS = 10V
SINGLE PULSE
RθJA = 96oC/W
0.1
TA = 25oC
0.01
0.01
0.1
1
10
60
40
20
0
0.01
100
SINGLE PULSE
RθJA = 96°C/W
TA = 25°C
80
0.1
1
10
100
1000
t1, TIME (sec)
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area
Figure 10. Single Pulse Maximum
Power Dissipation
1
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
ID, DRAIN CURRENT (A)
f = 1MHz
VGS = 0 V
VDS = 10V
ID = 17A
CAPACITANCE (pF)
VGS, GATE-SOURCE VOLTAGE (V)
10
D = 0.5
RθJA(t) = r(t) * RθJA
RθJA = 96 °C/W
0.2
0.1
0.1
0.05
P(pk)
0.02
t1
0.01
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
0.01
SINGLE PULSE
0.001
0.001
0.01
0.1
1
10
100
1000
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDD6682/FDU6682 Rev H(W)
FDD6682/FDU6682
Typical Characteristics
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
FAST
ActiveArray™
FASTr™
Bottomless™ FPS™
CoolFET™
FRFET™
CROSSVOLT™ GlobalOptoisolator™
DOME™
GTO™
EcoSPARK™ HiSeC™
E2CMOS™
I2C™
EnSigna™
i-Lo™
FACT™
ImpliedDisconnect™
FACT Quiet Series™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC
Across the board. Around the world.™ OPTOPLANAR™
PACMAN™
The Power Franchise
POP™
Programmable Active Droop™
Power247™
PowerSaver™
PowerTrench
QFET
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
µSerDes™
SILENT SWITCHER
SMART START™
SPM™
Stealth™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic
TINYOPTO™
TruTranslation™
UHC™
UltraFET
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I11