FDS4072N7 40V N-Channel PowerTrench MOSFET General Description Features This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for “low side” synchronous rectifier operation, providing an extremely low RDS(ON) in a small package. • 12.4 A, 40 V Applications • High power and current handling capability • Synchronous rectifier • Fast switching RDS(ON) = 11 mΩ @ VGS = 4.5 V RDS(ON) = 9 mΩ @ VGS = 10 V • High performance trench technology for extremely low RDS(ON) • DC/DC converter • FLMP SO-8 package: Enhanced thermal performance in industry-standard package size 5 Absolute Maximum Ratings Symbol Bottom-side Drain Contact 4 6 3 7 2 8 1 TA=25oC unless otherwise noted Ratings Units VDSS Drain-Source Voltage Parameter 40 V VGSS Gate-Source Voltage ± 12 V ID Drain Current 12.4 A – Continuous (Note 1a) – Pulsed PD 60 Power Dissipation (Note 1a) (Note 1b) TJ, TSTG Operating and Storage Junction Temperature Range 3.0 1.5 W –55 to +150 °C Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case (Note 1a) 40 °C/W 0.5 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS4072N7 FDS4072N7 13’’ 12mm 2500 units 2004 Fairchild Semiconductor Corporation FDS4072N7 Rev C2 (W) FDS4072N7 February 2004 Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units Drain-Source Avalanche Ratings (Note 2) EAS Drain-Source Avalanche Energy IAS Drain-Source Avalanche Current Single Pulse, VDD = 20V, ID=12.4 A 200 mJ 12.4 A Off Characteristics Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient ID = 250 µA VGS = 0 V, ID = 250 µA, Referenced to 25°C Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V IGSSF Gate–Body Leakage, Forward VGS = 12 V, IGSSR Gate–Body Leakage, Reverse VGS = –12 V , BVDSS ∆BVDSS ∆TJ IDSS On Characteristics 40 V 38 mV/°C 1 µA VDS = 0 V 100 nA VDS = 0 V –100 nA (Note 2) VGS(th) ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance gFS Forward Transconductance ID = 250 µA VDS = VGS, ID = 250 µA, Referenced to 25°C VGS = 4.5 V, ID = 12.4 A VGS = 10 V, ID = 13.7 A VGS = 4.5 V, ID = 12.4 A,TJ = 125°C VDS = 10 V, ID = 12.4 A 1 1.3 –4.5 3 9 8 14 84 11 9 18 V mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn–On Delay Time VDS = 20 V, f = 1.0 MHz V GS = 0 V, 4299 pF 351 pF 149 pF (Note 2) VDD = 20 V, VGS = 4.5 V, ID = 1 A, RGEN = 6 Ω 20 36 ns ns tr Turn–On Rise Time 12 22 td(off) Turn–Off Delay Time 52 83 ns tf Turn–Off Fall Time 18 32 ns 33 46 Qg Total Gate Charge Qgs Gate–Source Charge Qgd Gate–Drain Charge VDS = 20 V, VGS = 4.5 V ID = 12.4 A, nC 7.8 nC 8.1 nC Drain–Source Diode Characteristics and Maximum Ratings IS VSD trr Qrr Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward VGS = 0 V, IS = 2.5 A Voltage IF = 12.4 A, Diode Reverse Recovery Time diF/dt = 100 A/µs Diode Reverse Recovery Charge (Note 2) 0.7 2.5 A 1.2 V 30 nS 90 nC FDS4072N7 Rev C2 (W) FDS4072N7 Electrical Characteristics TA = 25°C unless otherwise noted Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 40°C/W when mounted on a 1in2 pad of 2 oz copper b) 85°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDS4072N7 Rev C2 (W) FDS4072N7 Electrical Characteristics FDS4072N7 Typical Characteristics 1.6 VGS =10V 3.0V 2.5V 4.5V ID, DRAIN CURRENT (A) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 80 60 40 20 1.4 VGS = 2.5V 1.2 3.0V 3.5V 10V 0.8 0 0 1 2 3 0 4 20 Figure 1. On-Region Characteristics. 60 80 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.025 1.9 ID = 12.4A VGS = 4.5V RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 40 ID, DRAIN CURRENT (A) VDS, DRAIN-SOURCE VOLTAGE (V) 1.6 1.3 1 0.7 ID = 6.2A 0.02 TA = 125oC 0.015 0.01 TA = 25oC 0.005 0.4 -50 -25 0 25 50 75 100 125 1 150 4 Figure 3. On-Resistance Variation withTemperature. 100 IS, REVERSE DRAIN CURRENT (A) VDS = 5V 60 40 o TA =125 C o 25 C 0 10 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 80 20 7 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) ID, DRAIN CURRENT (A) 4.5V 1 o -55 C VGS = 0V 10 o TA = 125 C 1 o 25 C 0.1 0.01 o -55 C 0.001 0.0001 1 1.5 2 2.5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 3 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS4072N7 Rev C2 (W) FDS4072N7 Typical Characteristics 6000 ID = 12.4A VDS = 10V 20V 8 f = 1MHz VGS = 0 V 5000 CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 10 30V 6 4 2 CISS 4000 3000 2000 COSS 1000 CRSS 0 0 0 20 40 60 0 80 10 Figure 7. Gate Charge Characteristics. P(pk), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 0.1 40 50 100µs 1ms 10ms 100ms 1s 10s DC RDS(ON) LIMIT 10 1 30 Figure 8. Capacitance Characteristics. 1000 100 20 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) VGS = 4.5V SINGLE PULSE o RθJA = 85 C/W o TA = 25 C 0.01 0.01 0.1 1 10 SINGLE PULSE RθJA = 85°C/W TA = 25°C 40 30 20 10 0 0.01 100 0.1 1 VDS, DRAIN-SOURCE VOLTAGE (V) 10 100 1000 t1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 RθJA(t) = r(t) * RθJA RθJA = 85 °C/W 0.2 0.1 0.1 P(pk) 0.05 t1 0.02 0.01 t2 0.01 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDS4072N7 Rev C2 (W) FDS4072N7 Dimensional Outline and Pad Layout FDS4072N7 Rev C2 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FPS™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ FACT™ ImpliedDisconnect™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I8