NSC ADC12EU050_0811

ADC12EU050
Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta
Analog-to-Digital Converter
General Description
Features
The ADC12EU050 is a 12-bit, ultra-low power, octal A/D converter for use in high performance analog to digital applications. The ADC12EU050 uses an innovative continuous time
sigma delta architecture offering ultra low power consumption
and an alias free sample bandwidth up to 25MHz. The input
stage of each channel features a proprietary system to ensure
instantaneous recovery from overdrive. Instant overload recovery (IOR) with no memory effect guarantees the elimination of phase errors resulting from out of range input signals.
The ADC12EU050 reduces interconnection complexity by using programmable serialized outputs which offer the industry
standard LVDS and SLVS modes. Power consumption of only
48mW per channel @ 50MSPS gives a total chip power consumption of 384mW. The ADC12EU050 can operate entirely
from a 1.2V supply, although a separate output driver supply
of up to 1.8V can be used. The device operates from -40 to
+85 °C and is supplied in a 10 x 10 mm2, 68 pin package.
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■
■
■
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CT∑Δ ADC architecture with 40-50MSPS throughput
Anti-alias filter free Nyquist sample range
Unique Instant Overload Recovery (IOR)
Wide 2.10 VPP input range
1.2V supply voltage
Integrated precision LC PLL
Serial control via SPI compatible interface
Key Specifications
■ Resolution
■ Conversion Rate
■ SNR
■ THD
■
■
■
■
Per Channel Power
Total Active Power
Inter-Channel Isolation
Operating Temp. Range
12 Bits
40 to 50 MSPS
69.3 dBFS (typ) @ 50 MSPS
fIN = 4.4MHz
–76.6 dB (typ) @ 50 MSPS
fIN = 4.4MHz
48 mW/ch (typ) @ 50MSPS
385 mW (typ) @ 50MSPS
>110 dB @ fIN = 4.4MHz
-40 to +85 °C
Applications
■
■
■
■
© 2008 National Semiconductor Corporation
300511
Medical imaging, ultrasound
Industrial ultrasound, such as non-destructive testing
Communications
Battery powered portable systems
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ADC12EU050 Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital
Converter
November 6, 2008
ADC12EU050
Block Diagram
30051102
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2
ADC12EU050
Connection Diagram
30051101
Ordering Information
Industrial (−40°C ≤ TA ≤ +85°C)
Package
ADC12EU050CIPLQ
68 Pin LLP
ADC12EU050EB
Evaluation Board
3
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ADC12EU050
Pin Descriptions
Pin No.
Name
Type
Function and Connection
Input
Differential analog inputs to the ADC, for channels 0 to 7. The
negative input pin may be connected via a capacitor to AGND or
the inputs may be transformer coupled for single ended operation.
Differential inputs are recommended for best performance.
ANALOG I/O
2
3
67
68
64
65
61
62
58
59
55
56
52
53
49
50
VIN0+
VIN0VIN1+
VIN1VIN2+
VIN2VIN3+
VIN3VIN4+
VIN4VIN5+
VIN5VIN6+
VIN6VIN7+
VIN7-
4
VREFB
Optional negative reference voltage to improve multi-channel ADC
matching. This pin must be connected to AGND.
VREFT
Optional positive reference voltage to improve multi-channel ADC
matching. If using the internal reference, this pin should be left tied
to AGND through a 100nF capacitor. If using an external reference
voltage, this pin should be connected to the positive reference
voltage, which must lie in the range specified in the Electrical
Characteristics table.
DCAP
This pin provides the capacitance for the low pass filter in the
modulator’s DAC. It must be connected to AGND through a
minimum 100nF capacitor. It is possible to decrease the noise
close to the carrier by increasing this capacitor, up to a maximum
of 10μF. See Applications Information for further information on the
selection of this capacitor.
5
6
7
Input
External bias reference resistor. This pin must always be
connected to AGND through a resistor, whether the internal
reference or an external reference voltage is used. The resistor
value must be 10kΩ ±1%.
RREF
Input/Output
RST
Input
This pin is an active low reset for the entire ADC, both analog and
digital components. The pin must be held low for 500ns then
returned to high in order to ensure that the chip is reset correctly.
Input
Sleep mode. Toggling this pin to high will cause the ADC to enter
the low power sleep mode. When the pin is returned to low, the
chip will, after the specified time to exit sleep mode, return to normal
operation.
DIGITAL I/O
9
10
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SLEEP
4
Name
15
16
18
19
20
21
23
24
25
26
28
29
31
32
33
34
DO0+
DO0DO1+
DO1DO2+
DO2DO3+
DO3DO4+
DO4DO5+
DO5DO6+
DO6DO7+
DO7-
36
37
BCLK+
BCLK-
ADC12EU050
Pin No.
Type
Function and Connection
Output
Differential Serial Outputs for channels 0 to 7. Each pair of outputs
provides the serial output for the specific channel. The default
output is reduced common mode LVDS format, but by
programming the appropriate control registers, the output format
can be changed to SLVS or LVDS.
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100 ohm
resistors.
Output
Bit clock. Differential output clock used for sampling the serial
outputs. Information on timing can be seen in the Electrical
Specifications section of the datasheet.
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100 ohm
resistors.
38
39
WCLK+
WCLK-
Output
Word Clock. Differential output frame clock. Information on timing
can be seen in the Electrical Specifications section of the
datasheet.
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100 ohm
resistors.
44
SDATA
Input/Output
SPI data input and output. This pin is used to send and receive SPI
address and data information. The direction of the pin is controlled
internally by the ADC based on the SPI protocol.
45
SCLK
Input
SPI clock. In order to use the SPI interface, a clock must be
provided on this pin. See Electrical Specifications for SPI clock and
timing information.
46
SSEL
Input
SPI chip select. This active low pin is used to enable the serial
interface.
47
48
CLK+ (SE)
CLK-
Input
Differential Input Clock. The input clock must lie in the range of
40MHz to 50MHz. It is used by the PLL to generate the internal
sampling clocks. A single ended clock can also be used, and
should be connected to pin 47.
1, 8, 51, 54,
57, 60, 63, 66
VA
Power
Analog Power Supply. All pins should be connected to the same
1.2V supply, with voltage limits as in the Electrical Specification.
0
AGND
Ground
Analog Ground Return.
11, 12, 42, 43
VD
Power
Digital Power Supply. Connect to 1.2V, with voltage limits as in the
Electrical Specification.
13, 14, 22,
30, 40, 41
DGND
Ground
Digital and Output Driver Ground Return.
17, 27, 35
VDR
Power
Output Driver Power Supply. Can be connected to 1.2V – 1.8V,
depending on application requirements. Voltage limits are
described in more detail in the Electrical Specification.
POWER SUPPLY
5
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ADC12EU050
Storage Temperature Range
−65°C to +125°C
Soldering process must comply with National
Semiconductor's Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA, VD)
IO Supply Voltage (VDR)
Voltage at Analog Inputs
Voltage at SPI Inputs
Input Current, VIN+, VINInput Current, other pins
ESD Susceptibility
Human Body Model
Machine Model
Charged Device Mode
Soldering Temperature
Infrared, 10 seconds
Operating Ratings
−0.3V to 1.4V
-0.3 to 2.0V
-0.3 to 2.0V
-0.3 to 2.5V
±1mA
±10mA
(Notes 2, 3)
Operating Temperature Range
Supply Voltage (VA=VD)
IO Supply Voltage (VDR)
Minimum rise time on VA, VD,
VDR at power-up
Analog Inputs (VINN+, VINN-)
SPI Inputs (SDATA, SSEL, SCLK)
VREFT (When using external
reference)
VREFB
VCM Input Common Mode Range
(Differential Input)
CLK Input Frequency
External Clock Duty Cycle
Ground Difference |AGNDDGND|
2500V
250V
1,250V
235°C
−40°C to +85°C
+1.14 to +1.26V
+1.14 to +1.89V
40µs
-0.10 to VA
+1.14 to +2.50V
475mV to 525mV
AGND
0.4V to 1.2V
40 to 50 MHz
20% to 80%
<50mV
Electrical Characteristics
Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL
= 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits
apply for TA = +25°C.
Symbol
Parameter
Conditions
Typical
(Note 4)
Limits
Units
12
Bits
LSB
Static Converter Characteristics
Resolution (No missing codes
guaranteed)
INL
Integral Non Linearity
±0.75
±3.0
DNL
Differential Non Linearity
±0.35
±0.75
LSB
PSE
Positive Full Scale Error
±0.66
±3
%FS
NSE
Negative Full Scale Error
±0.58
±3
%FS
GE
Gain Error
±1.23
%FS
Dynamic Converter Characteristics – Instant Overload Recovery (IOR) Off
SNR
SINAD
ENOB
THD
Signal to Noise Ratio(Note 5)
Signal to Noise and Distortion(Note
5)
Effective Number of Bits
Total Harmonic Distortion
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fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
69.3
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
69.0
dBFS
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
69.9
dBFS
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
69.6
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
68.5
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
68.5
dBFS
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
69.3
dBFS
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
69.2
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
11.1
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
11.1
Bits
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
11.2
Bits
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
11.2
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-76
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-78
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-77
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-79
dBc
6
67.0
dBFS (min)
dBFS
62.5
dBFS (min)
dBFS
10.1
Bits (min)
Bits
-65
dBc (max)
H2
H3
SFDR
IMD
Parameter
Second Harmonic Distortion
Third Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
Typical
(Note 4)
Limits
Units
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-81
-66
dBc (max)
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-79
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-82
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-80
dBc
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-83
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-97
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-84
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-108
dBc
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
77
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
78
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
78
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
79
dBc
-70
dBFS
Conditions
f1 = 9.6MHz, VIN = -6dBFS
f2 = 10.1MHz, VIN = -6dBFS
-67
66
dBc (max)
dBc (min)
Dynamic Converter Characteristics – Instant Overload Recovery (IOR) On
SNR
SINAD
ENOB
THD
H2
H3
SFDR
IMD
Signal-to-Noise Ratio(Note 5)
Signal-to-Noise and Distortion(Note
5)
Effective Number of Bits
Total Harmonic Disortion
Second Harmonic Distortion
Third Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
67.6
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
67.4
dBFS
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
68.4
dBFS
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
68.2
dBFS
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
67.0
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
67.0
dBFS
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
67.9
dBFS
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
67.8
dBFS
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
10.8
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
10.8
Bits
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
11.0
Bits
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
11.0
Bits
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-76
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-77
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-77
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-78
dBc
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-80
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-78
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-81
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-79
dBc
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-83
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-96
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
-85
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
-107
dBc
fCLK = 50MHz, fIN = 4.4MHz, VIN = -0.5dBFS
76
fCLK = 50MHz, fIN = 9.5MHz, VIN = -0.5dBFS
77
dBc
fCLK = 40MHz, fIN = 4.4MHz, VIN = -0.5dBFS
78
dBc
fCLK = 40MHz, fIN = 9.5MHz, VIN = -0.5dBFS
78
dBc
-70
dBFS
f1 = 9.6MHz, VIN = -6dBFS
f2 = 10.1MHz, VIN = -6dBFS
65.5
61.5
9.9
-64
-65
-67
65
dBFS (min)
dBFS (min)
Bits (min)
dBc (max)
dBc (max)
dBc (max)
dBc (min)
Inter-channel Characteristics
Channel to channel gain match
±0.1
7
±0.5
dB
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ADC12EU050
Symbol
ADC12EU050
Symbol
Parameter
Inter-channel Isolation
Conditions
fIN = 4.4MHz @ -0.1dBFS
Typical
(Note 4)
Limits
Units
110
dB
IOR mode off
2.10
VPP
IOR mode on
1.56
VPP
Adjacent channel terminated
Reference And Analog Input Characteristics
VIN
Full Scale Analog Input Voltage
Maximum Input for Instantaneous
Recovery from Overload
RIN
Differential Input Impedance
VCM
Internal Input Common Mode
IOR mode on, fIN < 12MHz
2.61
Generated internally
Input Impedance of VReft
VREFOUT Internal Reference Voltage
2.75
605
2.4
kΩ (min)
2.8
kΩ (max)
574
637
mV (min)
mv (max)
20
Generated internally
VPP (max)
kΩ
502
480
520
mV (min)
mV (max)
Power Characteristics
IA
Analog Supply Current
fCLK = 50 MHz
152
163
mA (max)
ID
Digital Supply Current
fCLK = 50 MHz
130
147
mA (max)
IDR
Output Driver Supply Current
LVDS, VDR = 1.8V, fCLK = 50 MHz
38
45
mA (max)
fCLK = 50 MHz, Equalizer off
385
412
mW (max)
fCLK = 50 MHz, Equalizer on
435
470
mW (max)
fCLK = 40 MHz, Equalizer off
343
mW
fCLK = 40 MHz, Equalizer on
383
mW
Sleep
40
50
mW (max)
Power Down
5
15
mW (max)
fCLK = 50 MHz, Equalizer off
48
mW
Power consumption
Per channel power consumption
fCLK = 40 MHz, Equalizer off
43
mW
PSRR
Power supply rejection ratio
100mV, 100kHz to 1MHz sinusoid on VA
65
dB
CMRR
Common mode rejection ratio
100mV, 1MHz sinusoid on VIN+ and VIN-
60
dB
Recovery time from sleep
12
µs (max)
Recovery time from power down
18
ms (max)
Recovery time from single channel
power down
6
µs (max)
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8
Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL
= 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits
apply for TA = +25°C.
Symbol
Parameter
Pass band
Pass band transition
Conditions
Typical
(Note 4)
Units
fCLK = 50MHz
22
MHz
fCLK = 40MHz
17.6
MHz
fCLK = 50MHz, -3dB attenuation
25
MHz
fCLK = 40MHz, -3dB attenuation
20
MHz
Pass band ripple
fIN < 22MHz
Stop band
fCLK = 50MHz
34.5
fCLK = 40MHz
27.6
±0.01
Stop band attenuation
Group delay ripple (peak to peak)
Limits
fIN < 22MHz, Equalizer on
9
dB
MHz
MHz
72
dB (min)
0.05
Samples (max)
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ADC12EU050
Digital Decimation Filter Characteristics
ADC12EU050
External Input Clock and PLL Characteristics
Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL
= 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits
apply for TA = +25°C.
Symbol
Parameter
Conditions
Typical
(Note 4)
Limits
Units
40
50
MHz (min)
MHz (max)
20
80
% (min)
% (max)
External Input Clock
fCLK
External input clock frequency
tCLK
Input clock period
1/fCLK
ns
fCLK DC
External clock duty cycle
tCH
Input clock high time
0.45* fCLK
tCL
Input clock low time
0.45* fCLK
tCR
Input clock rise time
0.05* fCLK
ns
tCF
Input clock fall time
0.05* fCLK
ns
300
fs
tJIN
RMS Clock Jitter
50
Generated by PLL. Integrated from 0MHz to
BWloop
0.2* tCLK
ns (min)
0.8* tCLK
ns (max)
0.8* tCLK
ns (min)
0.2* tCLK
ns (max)
PLL
f∑Δ
Over-sampling frequency
BWloop
PLL Loop filter bandwidth
tJ
RMS Bit Clock Jitter
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640
800
Low Bandwidth
400
High Bandwidth
1.4
kHz
MHz
2
10
MHz (min)
MHz (max)
ps peak
Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL
= 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits
apply for TA = +25°C.
Symbol
Parameter
Conditions
Typical
(Note 4)
Limits
Units
Digital Inputs (SDATA, SSEL, SCLK, SLEEP, RST)
VIH
Logical input “1” voltage
Test run at 2MHz
900
mV (min)
VIL
Logical input “0” voltage
Test run at 2MHz
300
mV (max)
IIN1
Logical "1" Input current
1
µA (max)
IIN0
Logical "0" Input current
-1
µA (min)
CIN
Input Capacitance
Guaranteed by design
5
pF
Digital Outputs (SDATA)
VOH
Logical output “1” voltage
Test run at 2MHz, VDR = 1.2V
VDR
850
mV (min)
VOL
Logical output “0” voltage
Test run at 2MHz, VDR = 1.2V
DRGND
IOH
Logical "1" Output Current
250
mV (max)
-0.75
mA (min)
IOL
Logical "0" Output Current
1
mA (max)
Output Drive Capability (SDATA)
CLOAD
Load capacitance
R = 4.7 kohm, VDR > 1.8V
50
pF
R = 4.7 kohm, VDR = 1.2V
50
pF
Open Drain Mode
VEXT
Maximum allowed external voltage on
Open Drain mode activated
SDATA
RSDATA
Recommended SDATA external pullup resistor
Open Drain mode activated
11
2.5
4.7
V
kΩ
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ADC12EU050
Digital Input and Output Characteristics
ADC12EU050
AC and Timing Characteristics
Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL
= 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits
apply for TA = +25°C.
Symbol
Parameter
Conditions
Typical
(Note 4)
Limits
Units
40
50
MSPS (min)
MSPS (max)
General ADC Output Timing Parameters
fs
Sample Rate
19
Samples
tBCLK
Conversion Latency
Bit clock period
fCLK = 50MHz
3.33
ns
tWCLK
Word clock period
fCLK = 50MHz
20
ns
tS
Data valid setup time
830
325
ps (min)
tH
Data valid hold time
900
470
ps (min)
tR, tF
Output Rise/Fall time
320
tDFS
Data Edge to Word Edge Skew
-295
-720
220
ps (min)
ps (max)
ps
LVDS Output Parameters, OCM = 0 (VDR = 1.2V)
LVDS mode, I_drive[1:0] = 00 (2.5mA), RL =
270
mV
100Ω
VOD
Differential Output Voltage
LVDS mode, I_drive[1:0] = 01 (3.5mA), RL =
370
100Ω
LVDS mode, I_drive[1:0] = 11 (5.0mA), RL =
318
428
520
mV (min)
mV (max)
mV
100Ω
VOCM
Output Common Mode Voltage
LVDS mode, OCM = 0 (for VDR = 1.2V)
945
895
1000
mV (min)
mV (max)
LVDS Output Parameters, OCM = 1 (VDR = 1.8V)
LVDS mode, I_drive[1:0] = 00 (2.5mA), RL =
265
mV
100Ω
VOD
Differential Output Voltage
LVDS mode, I_drive[1:0] = 01 (3.5mA), RL =
350
100Ω
LVDS mode, I_drive[1:0] = 11 (5.0mA), RL =
280
417
485
mV (min)
mV (max)
mV
100Ω
VOCM
Output Common Mode Voltage
LVDS mode, OCM = 1
1265
1200
mV (min)
1340
mv (max)
SLVS Output Parameters
SLVS mode, I_drive[1:0] = 00 (2.5mA), RL =
245
mV
100Ω
VOD
Differential Output Voltage
SLVS mode, I_drive[1:0] = 01 (3.5mA), RL =
330
100Ω
SLVS mode, I_drive[1:0] = 11 (5.0mA), RL =
262
393
475
mV (min)
mV (max)
mV
100Ω
VOCM
Output Common Mode Voltage
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SLVS mode
225
12
185
270
mV (min)
mV (max)
Unless otherwise specified, the following conditions apply: VA = VD = 1.2V; VDR = 1.2V; VREF = internal; RREF = 10kohm ±1%; CL
= 5pF; 100Ω terminated at the receiver; fCLK = 50MHz; fS = 50MSPS. Boldface limits apply for TA = TMIN to TMAX; All other limits
apply for TA = +25°C.
Symb
ol
Parameter
Conditions
Typical
(Note 4)
Limits
Units
Serial Interface
tSSELS
SSEL setup time
250
tSSELH
SSEL hold time
250
tWS
SDATA setup time, write transaction
250
tWH
SDATA hold time, write transaction
tSCLK
SCLK period
tSCLKL
SCLK low time
450
ns (min)
tSCLKH
SCLK high time
450
ns (min)
tSCLKR
SCLK rise time
50
ns
tSCLKF
SCLK fall time
50
ns
500
ns
tSSELHI SSEL high time
Applies to read and write transactions
ns
ns
15
ns (max)
250
10
ns (max)
1
0.2
µs (min)
tRS
SDATA valid setup time, read
transaction
100
-5
ns (min)
tRH
SDATA valid hold time, read transaction
250
10
ns (min)
Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. Guaranteed
specifications and test conditions are specified in the Electrical Characterisitcs section. Operation of the device beyond the Operating Ratings is not recommended
as it may degrade the device lifetime.
Note 3: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 4: Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 5: This parameter is specified in dBFS. This indicates the value which would be obtained with a full-scale input.
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ADC12EU050
AC and Timing Characteristics (Serial Interface)
ADC12EU050
Timing Diagrams
30051103
FIGURE 1. LVDS/SLVS Output Timing
30051129
FIGURE 2. Output Level Definitions
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14
ADC12EU050
30051104
FIGURE 3. SPI Write Timing
30051105
FIGURE 4. SPI Read Timing
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ADC12EU050
Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VA =
VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
DNL
INL
30051130
30051131
Spectral Response @ fIN=10MHz, fCLK= 40MHz, IOR off
Spectral Response @ fIN=10MHz, fCLK= 40MHz, IOR on
30051132
30051133
Spectral Response @ fIN=10MHz, fCLK= 50MHz, IOR on
Spectral Response @ fIN=10MHz, fCLK= 50MHz, IOR off
30051134
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30051135
16
Unless otherwise specified, the following conditions apply: VA =
VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
SNR, SINAD, SFDR vs fCLK, IOR off
Distortion vs fCLK, IOR off
30051139
30051140
SNR, SINAD, SFDR vs fCLK, IOR on
Distortion vs fCLK, IOR on
30051141
30051142
SNR, SINAD, SFDR vs VA, fCLK = 40MHz, IOR off
Distortion vs VA, fCLK = 40MHz, IOR off
30051143
30051153
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ADC12EU050
Typical Performance Characteristics
ADC12EU050
Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VA =
VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
SNR, SINAD, SFDR vs VA, fCLK = 50MHz, IOR off
Distortion vs VA, fCLK = 50MHz, IOR off
30051144
30051154
SNR, SINAD, SFDR vs Temperature, fCLK = 40MHz, IOR off
Distortion vs Temperature, fCLK = 40MHz, IOR off
30051156
30051157
SNR, SINAD, SFDR vs Temperature, fCLK = 50MHz, IOR off
Distortion vs Temperature, fCLK = 50MHz, IOR off
30051160
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30051161
18
Unless otherwise specified, the following conditions apply: VA =
VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
SNR, SINAD, SFDR vs fIN, fCLK = 40MHz, IOR off
Distortion vs fIN, fCLK = 40MHz, IOR off
30051145
30051146
SNR, SINAD, SFDR vs fIN, fCLK = 40MHz, IOR on
Distortion vs fIN, fCLK = 40MHz, IOR on
30051147
30051148
SNR, SINAD, SFDR vs fIN, fCLK = 50MHz, IOR off
Distortion vs fIN, fCLK = 50MHz, IOR off
30051149
30051150
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ADC12EU050
Typical Performance Characteristics
ADC12EU050
Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VA =
VD = 1.2V; VDR = 1.2V; VREF = internal; CL = 5pF; fCLK = 50MHz; fS = 50MSPS; fIN = 10MHz. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
SNR, SINAD, SFDR vs fIN, fCLK = 50MHz, IOR on
Distortion vs fIN, fCLK = 50MHz, IOR on
30051151
30051152
Spectral Response @ fIN1= 9.6MHz, fIN2= 10.1MHz, IOR off
Spectral Response @ fIN1= 9.6MHz, fIN2= 10.1MHz, IOR on
30051136
30051137
Histogram of output code for zero input
Current vs fCLK, Equalizer off, LVDS output
30051138
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30051155
20
ADC12EU050
Functional Description
The ADC12EU050 employs a number of unique strategies to
provide a high performance multi-channel ADC that offers a
significant power consumption reduction when compared to
compteting architectures, as well as easing system level design. The ultra-low power performance of the ADC12EU050
is derived from the implementation of a fast continuous time
sigma delta (CT∑Δ) modulator. Other features of this technology are:
• Intrinsic anti-alias filter – the digital decimating filter
provides an intrinsic anti-alias filter, eliminating external
analog filter components, and simplifying multi-channel
designs.
• Instant overload recovery (IOR) system guarantees
extremely fast recovery from overload (<1ps), and no
settling errors on return from overload.
• Ultra-low inter-channel crosstalk.
• Digital Equalizer provides low group delay and hence
minimizes signal path delay variation.
The major signal path blocks are: clipping control; CT∑Δ
modulator; digital decimation filter; 12 bit serializer; and finally
the LVDS/SLVS outputs. The PLL is critical to the operation
of the ADC12EU050, and the PLL also provides the bit and
word clock outputs. The SPI Control Interface gives uncomplicated user access to the ADC registers.
30051123
FIGURE 5. SHA Input Stage
1.0 12-BIT SIGMA DELTA ADC CORE
The ADC12EU050 comprises eight analog ADC channels
using a CT∑Δ architecture, which provides very high dynamic
performance with ultra-low power, while operating from a
minimal 1.2V supply.
The CT∑Δ ADC architecture uses a third order sigma delta
modulator operating at a nominal 16 times over-sampling rate
in combination with a 3-bit quantizer. The modulator output is
coupled to a power efficient digital decimation filter that decimates the high rate modulator output (640 to 800MHz) to
provide output data at a sample rate between 40 MSPS and
50 MSPS.
A benefit of the CT∑Δ design is that the ADC requires no
external anti-alias filters for most applications. This benefit is
derived from a combination of the design of the analog sigma
delta modulator and digital decimation filter. The digital filter
achieves a steep transition band, and provides 72 dB of attenuation in the stop band. Using the digital equalizer, the
signal transfer characteristics including phase performance
can be optimized so as to minimise group delay variation. In
applications where it is not required, the digital equalizer can
be disabled to further save power.
30051124
FIGURE 6. Continuous Time Sigma Delta Input Stage
1.2 INSTANT OVERLOAD RECOVERY
The ADC12EU050 features an overload handling system
which provides instantaneous recovery from signals driving
the ADC inputs beyond the full-scale input range. The ADC
can operate in two different modes. In the default ADC mode
(IOR mode off) a full-scale input range of 2.10 VPP is supported, here the ADC operates with some inherent overload
recovery time, similar to a conventional ADC.
In the IOR mode, the ADC has a reduced 1.56 VPP full scale
input range, but provides a significant benefit in that the ADC
can now be driven by input voltages as high as 5 dB beyond
the nominal full-scale (fIN < 12MHz), that is 2.75 VPP, and will
recover instantaneously. In a number of applications this feature can help simplify input stage design and manufacturing
set-up and calibration. The ADC12EU050 recovers immediately from overload with no missing codes and no settling
time.
The proprietary strategy used within the ADC12EU050 uses
high speed patented clamp techniques to limit the input signal
and keep it within the stable input range of the ADC. This
process happens at a speed equivalent to the on-chip oversampling rate of 640 to 800 MHz. The advantage of this
system is that it responds immediately to out of range signals.
While the inputs are over-range the ADC outputs a full scale
result. As the over-range input is removed the ADC adjusts to
the input signal level and is able to provide sampled data instantaneously. The ADC’s behaviour on emerging from overload is repeatable and independent of whether the input
signal was positive or negative going at the point of overload.
The diagram below shows a 5dB overloaded input (2.75 VPP
versus 1.56 VPP Full scale), with 240,000 sample periods
1.1 DIFFERENTIAL INPUT STAGE
The ADC can capture high speed analog signals without resorting to a complex fast sample-and-hold amplifier (SHA) as
used in pipeline ADCs. This is where CT∑Δ technology derives much of its power and performance benefits. This feature also assists external circuit design. In the case of the SHA
inputs of pipeline ADCs, the effective input capacitance is
time variant, requiring a powerful input buffer to drive to the
resolution limits of the system. The input stage of the ADC is
purely resistive (1.3kΩ single ended) driving into virtual earth.
As a result the ADC12EU050 is extremely easy to drive as its
input impedance is not complex. It also means that external
lower power input buffering circuitry can used, and can be
completely eliminated in some cases.
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ADC12EU050
overlaid. There is no ringing and recovery from overload is
instantaneous.
30051106
FIGURE 7. Instant Overload Recovery
1.3 INTEGRATED PRECISION LC PLL
The ADC12EU050 family includes an integrated high performance “clean up” phase locked loop (PLL), simplifying the
need for a low jitter external clock. The PLL serves three important functions; it generates a highly accurate internal sampling clock source of up to 800 MHz; a clock for the LVDS
serializers at 600 MHz; and it provides a low jitter clock for
other internal components. With its jitter clean-up capability
this PLL allows lower performance system clocks to be used.
1.4 DIGITAL DECIMATION FILTER AND EQUALIZER
The digital decimation filter is an integral part of the sigma
delta architecture. It decimates the over-sampled data from
the modulator down to the sample rate, and its extremely
sharp low pass characteristic combined with the modulator’s
broad band response provides the intrinsic anti-alias filter.
The digital low pass filter exhibits 72dB of attenuation in the
stop band. The following diagram shows the digital filter transfer function at 40MSPS, compared to a third order Butterworth
transfer function. Due to the digital implementation of the filter,
the filter parameters automatically scale with the ADC sampling frequency.
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30051107
FIGURE 8. Digital Filter Transfer Function
22
1.6 POWER MANAGEMENT MODES
The ADC12EU050 operates normally at ultra-low power levels. In addition, several power management modes are provided:
• Power Down (accessible through PD bit of Top Control
Register)
• Sleep (SLEEP pin, or SLEEP bit of Top Control Register)
• Single channel power down (PD0-7 of ADC/LVDS
Channel Power Down Register)
Power Down is the lowest power consumption mode, but with
a longer wake-up time than Sleep mode. In power down
mode, all circuits in the chip are turned off, including the PLL,
reference and bias circuits.
Power consumption in Sleep mode is higher than in Power
Down mode, but pin access (SLEEP pin) and fast wake-up
enables duty cycle powering of the ADC.
The device also allows channel by channel power-down
through the ADC/LVDS Channel Power Down register. When
a single channel is powered down, the sigma delta modulator,
digital decimating filter and LVDS outputs for that channel will
be shut off, with the corresponding single channel reduction
in power consumption.
1.7 SPI CONTROL INTERFACE
The ADC12EU050 provides configurability via the serial control interface. This provides IOR mode control power management control, output configuration control, data output test
patterns to provide LVDS/SLVS training sequences, as well
as many other user configurable options. Full details of the
SPI registers can be found in the Programming Guide section
of this datasheet.
The SPI pins (SDATA, SCLK, SSEL), as well as the pins RST and
SLEEP, have been designed to operate with voltage levels
up to 2.5V, despite the low 1.2V core voltage. As a result, no
external level shift components are required for this control
interface.
30051108
FIGURE 9. Group Delay with Equalizer Off
1.8 UNCORRELATED NOISE REFERENCE FOR EACH
CHANNEL
In many early multi-channel ADC designs, a single voltage
reference was used to provide the reference level for each
channel. Unfortunately, this ensures that the noise at each
ADC’s reference terminal is cross correlated. Multi-channel
systems often make use of a 3 dB processing gain increase
that results from each channel doubling. Without a specific
technique to prevent the reference terminals seeing correlated noise the expected 3 dB gain is compromised. In the case
of the ADC12EU050, a unique system has been implemented
to de-correlate the noise at each ADC channel.
30051109
FIGURE 10. Group Delay with Equalizer On
1.5 SERIAL DATA OUTPUTS
Sampled data is transformed into high speed serial LVDS/
SLVS output data streams. The low amplitude differential signal swings of LVDS/SLVS help to reduce digital system noise.
It is possible to select between LVDS and SLVS modes by
simple programming through the SPI control interface. The
output common mode can also be programmed through the
SPI control interface, allowing it to be adjusted based on the
value of VDR.
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ADC12EU050
Such steep digital filters introduce group delay problems, but
the ADC12EU050 includes a digital equalizer, which reduces
group delay ripple variation to less than 0.05 samples. In applications where group delay is not of concern, the equalizer
can be turned off through the SPI interface in order to save
power.
The following two diagrams show the group delay ripple of the
digital decimation filter at 50MSPS, firstly with the equalizer
disabled, and secondly with the equalizer enabled.
ADC12EU050
differential clock, the clock traces should be routed as 100Ω
differential pairs, and terminated with a 100Ω resistor close to
the chip. A single ended clock input should be connected to
pin 47 (CLK+/SE), and pin 48 (CLK-) should be grounded.
On-chip PLL
The benefit of having an on chip PLL is that in most applications a high precision clock source is not required. The impact
of aperture jitter on the ADC’s performance is reduced dramatically by the jitter clean-up properties of the PLL, which
ensures that any RMS jitter outside of the PLL bandwidth is
attenuated. The PLL also significantly relaxes the input clock
duty cycle requirements, accepting input clock duty cycles of
20% to 80%.
The PLL offers two choices of bandwidth. For the majority of
systems, the default bandwidth of 400kHz is suitable. If the
system already contains a high performance clock, with excellent RMS jitter performance up to a 1.4MHz bandwidth,
then the PLL’s high bandwidth mode may be used.
Application Information
2.0 POWER-UP SEQUENCE
The ADC12EU050 has three separate power supplies: Analog (VA), Digital (VD) and the output drive voltage ( VDR). The
ADC contains a power on reset circuit, connected to VA, and
so to ensure correct reset of both analog and digital logic of
the ADC, the power supplies should be provided in the following order:
1. VDR
2. VD
3. VA
If this order is not followed, then the user should issue a reset
via the reset pin (RST) immediately after power up.
Additionally, it is required that the rise time for each voltage
supply is longer than the minimum rise time stated in the
Electrical Specifications section of this data sheet.
There is no required sequence for powering down the ADC.
2.1 ADC START-UP SEQUENCE
After any reset, either power-on reset, software reset via SPI
or hardware reset via the RST pin, the chip undergoes a series of internal calibrations and the PLL/VCO will lock to the
external clock.
After reset, the ADC12EU050’s registers have the default values shown in register tables. The registers can be programmed via the SPI after reset, even during the period while
the chip is performing the internal calibrations mentioned in
the previous paragraph.
During reset and until the PLL is locked, the LVDS outputs will
not provide valid data. Furthermore, the ADC has an inherent
data conversion latency, which is related to the pipeline
stages of the digital decimating filter. Until the data conversion
latency has passed, the data outputs will be invalid.
Thus the maximum time until valid sampled data is received
at the outputs is:
PLL lock time + ADC Latency
Specific values for these times can be found in the Electrical
Specifications section of this datasheet.
30051115
FIGURE 11. PLL Phase Noise Transfer Function: fs =
40MHz
2.2 USING ADC LOW POWER MODES
As explained previously in the Functional Description, the
ADC12EU050 offers several power management modes.
Sleep mode offers the fastest wake-up time, and should be
used in applications where duty cycle powering of the ADC is
required. In this case it is recommended to toggle sleep mode
via the SLEEP pin, which will give a faster cycle time than
programming the SLEEP bit through the SPI, due to the extra
time required to send a command through the SPI port.
The Power Down mode is accessible via the SPI port. Due to
the power-up time of the ADC coupled with the programming
time of the SPI port, this mode should be used to power the
chip down for longer time periods.
Channel power down allows one or more channels to be
turned off independently, with the corresponding power saving.
30051116
2.3 CLOCK SELECTION CONSIDERATIONS
The ADC12EU050 has an on-chip PLL, which simplifies the
task of clock source selection and clock network design.
Clock Input Connection
The ADC is designed to accept either single ended or differential clock inputs. In order to guarantee the specified performance, a differential clock should be used. When using a
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FIGURE 12. PLL Phase Noise Transfer Function: fs =
50MHz
On the input clock, excessive RMS jitter within the PLL bandwidth will be seen in the output spectrum as sidebands, or
close in phase noise, around the fundamental signal.
24
Differential Input Configurations
The ADC12EU050 can be driven either actively or passively.
The LMH6512 offers a combined LNA/VGA with differential
output, which performs well with the ADC12EU050 in systems
requiring input signal amplification, such as Medical Ultrasound.
Transformer coupling provides another possibility for converting a single ended signal into a differential signal. The
diagram below shows a transformer coupled input configuration.
2.4 ADC INPUT CONSIDERATIONS
The ADC12EU050’s sigma delta architecture offers many
flexible options for connecting input signals.
In order to obtain maximum performance from the device, it
is recommended to use a differential input connection. The
device, however, also supports single ended analog input.
30051121
FIGURE 13. Transformer Coupled Input
mum input voltage allowed is 3dB less than the 2.10V full
scale input. The diagram below shows a single ended input
configuration.
Single Ended Input Configurations
In cost sensitive applications, a single ended input may provide adequate performance, however ADC performance will
degrade slightly. When using single ended inputs, the maxi-
30051120
FIGURE 14. Single Ended Input
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ADC12EU050
Input Clock Selection
For systems which do not have a requirement for a high performance clock, any standard product 40MHz – 50MHz crystal oscillator will allow the ADC12EU050 to perform to
specifications. If the system requires high performance clocks
for other system components, then National Semiconductor's
LMK family of clock conditioners are recommended.
ADC12EU050
Due to the purely resistive input circuit of the sigma delta architecture, the ADC12EU050 allows the user to scale down
large input signals by adding external series resistors. The
gain achieved by adding external resistors can be calculated
as a simple voltage divider, as follows:
VFS/VIN = 20 * log (RADC /( RADC + REXT)) dB
The diagram below shows this configuration, and defines the
values in the equation above.
Input Coupling and Common Mode
The ADC12EU050 internally generates a common mode of
0.62V. It is possible to provide input signals with other common modes however, the full scale input range of the ADC
must be kept in mind.
For this reason, it is recommended that the device inputs are
AC coupled. The recommended capacitor value is 100nF.
External Series Resistance
30051118
FIGURE 15. External Series Resistance
RADC, the input resistance of the ADC, is nominally 1.3kΩ.
Due to manufacturing the value of this resistance can vary by
up to 15%. This is not important for the operation of the ADC,
since the ADC depends only on internal resistors being
matched, but it should be taken into account when performing
calculations.
2.5 ADC OUTPUT CONSIDERATIONS
The ADC12EU050 offers a variety of output settings in order
to cater for different system design and integration needs.
Output Driver Voltage, VDR
The ADC output driver voltage, VDR, can be set between
1.2V and 1.8V. A VDR of 1.2V will offer the lowest power
consumption. Because VDR can be varied, the ADC12EU050
provides, via the SPI registers, the ability to adjust the output
common mode voltage.
Output Modes And Output Common Mode
Three different output modes are also supported: SLVS,
LVDS and reduced common mode LVDS. SLVS and LVDS
modes output data according to their respective specifications.
Reduced common mode LVDS must be used when the output
driver voltage, VDR, is 1.2V. The standard LVDS common
mode voltage is 1.2V, which is obviously not feasible if VDR
is 1.2V. Therefore, the output common mode voltage must be
set to 1.0V by setting the bit OCM in the LVDS Control Register to 0.
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30051126
FIGURE 16. Output Driver Circuit: Reduced Common
Mode LVDS
When VDR is 1.8V, the standard LVDS common mode voltage of 1.2V must be used, by setting OCM equal to 1.
26
30051125
FIGURE 17. Output Driver Circuit: LVDS
SLVS mode offers the lowest power consumption, followed
by reduced common mode LVDS then standard LVDS.
30051127
FIGURE 18. Output Driver Circuit: SLVS
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ADC12EU050
As well as the different output modes, the output drive current
can also be controlled via the LVDS Control Register. The
default output drive current is 2.5mA, but this can be increased to 3.5mA or 5mA, depending on output trace routing
and receiver requirements. Power consumption of the ADC12EU050 will increase slightly as the output driver current
is increased.
Termination
The final control feature available in the LVDS Control Register is the choice between internal and external 100Ω termination. Although the termination is recommended to be as
close to the receiver as possible, in some cases it may be
necessary or desirable to perform this termination at the
transmitter. Internal 100Ω termination at the transmitter (the
ADC12EU050) is enabled by setting the bit TX_term to 1.
LVDS Output Training Sequences
Often it is necessary to calibrate the LVDS receiver, for example an FPGA or DSP, so that skew between the eight ADC
output channels is minimized. In order to simplify this process,
the ADC12EU050 provides three LVDS training modes,
where a pre-defined or custom pattern is output on all eight
channels simultaneously. While a training mode is active, the
word and bit clocks are output as usual. In order to select a
training mode, the TSEL bits of the Decimator Control Register (16h) must be programmed via the SPI interface.
There are two pre-defined training patterns, or a custom pattern can be loaded via the SPI into the Serializer Custom
Pattern 0 and 1 Registers (10h and 12h). In order to return to
normal ADC operation after skew calibration, the TSEL bits
should be returned to their default value of 00.
ADC12EU050
30051164
FIGURE 19. LVDS Training Select operation
The implementation of IOR mode in the ADC consists of analog and digital parts working in tandem.
The analog clipping circuitry, controlled by OL, is designed to
protect the sigma delta modulator from large signal inputs.
Using an analog clamp, signals are soft-limited to the less
than the 2.10Vpp full scale range of the modulator. OL gives
the value at which the circuit will begin to clamp.
The digital filter of the ADC12EU050 is where the full scale
input range is selected and the hard limiting of the signal takes
place. DGF selects the gain of the digital filter, and hence the
new full scale input range of the ADC.
In order to set a custom value for DGF, CGS, bit 7 of the Decimator Clipping Control register, must be set. The DGF can
then be set, based on the application requirements.
OL should then be set to a value approximately half-way between the new full scale input range (which was just selected
by DGF) and the default full scale input range of 2.10Vpp. OL
must be set to a value higher than DGF, otherwise the signal
will be limited by the analog clipping circuitry, rather than the
digtal circuitry, and overload recovery will be impacted.
2.6 USING IOR MODE
As discussed in the Functional Description, IOR mode provides instantaneous recovery from overload conditions, with
no ringing and correct data output as soon as the input returns
in range.
Standard Use of IOR Mode
The recommended way to enable IOR mode is by setting bit
4 (IOR) of the Modulator Overload Control register (04h). Setting this bit will enable IOR mode with the default settings for
DGF in the Decimator Clipping Control register (14h) and OL
in the Modulator Overload Control register (04h). Setting the
IOR mode bit to 0 will restore DGF and OL to their default
values, hence putting the chip back into ADC mode.
As can be seen in the Electrical Specifications, using IOR
mode gives a slight reduction in SNR performance, and also
a reduction of the full scale input range to 1.56Vpp differential.
Advanced Use of IOR Mode
The registers described above allow the user to customize
IOR mode. In order to correctly set the DGF and OL values,
it is necessary to understand how the IOR mode functions.
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ADC12EU050
30051128
FIGURE 20. IOR Mode Signal Modification
When using the internal reference, VREFT should be connected to AGND through a 100nF capacitor, while VREFB must be
connected to AGND.
Chip-to-chip gain matching between several ADC12EU050
ADCs can be improved by connecting the VREFT pins of the
ADCs. This is show in the figure below.
2.7 THE VOLTAGE REFERENCE
The ADC provides an on chip, ±5% tolerance voltage reference, together with all necessary biasing circuits and current
sources. A 10kΩ (±1%) resistor must be connected between
RREF and AGND in order to establish the biasing current of
the ADC. The internal reference voltage, VREF, is available at
the RREF pin.
30051122
FIGURE 21. Reference Sharing
If a tighter tolerance reference is required for improved thermal stability, an external voltage reference can be connected
between the VREFT and VREFB pins. The RREF resistor must be
connected even when using an external reference.
carrier. The filter circuit, which is a first order RC filter, is
shown in the diagram below.
2.8 DCAP CAPACITOR SELECTION
The DCAP pin provides the capacitance for the low pass filter
between the DAC bias block and the DAC in the sigma-delta
modulator. The filter blocks noise from the DAC Bias block
from entering the DAC. Any noise which passes through this
filter will be seen in the spectrum as side skirts around the
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ADC12EU050
This includes using a split ground plane, since the significant
digital portion of the chip can produce noise on the digital/IO
ground (DGND).
When designing the ADC12EU050 into a system, It is critical
that the exposed pad is connected to analog ground (AGND).
The exposed pad provides the analog ground connection for
the ADC12EU050, and so this connection is required for electrical rather than thermal reasons.
It is recommended to decouple the power supplies using a
large capacitor (e.g. 47µF) for low frequency noise, and small
capacitors (e.g. 100nF) placed close to each supply pin.
Analog and digital supplies (VA and VD) may be provided from
the same supply, however in this case it is recommended that
the supplies are isolated from each other with a ferrite bead
or inductor. If the IO driver supply (VDR ) is 1.2V, then it may
also be taken from the same supply, with isolation as described above.
The clock and data output traces, as well as the clock input
trace (when using a differential input clock), should be routed
as 100Ω impedance differential pairs. If not using the option
for 100Ω internal termination, then the clock and data output
trances should be terminated with a 100Ω resistor close to the
receiver.
If the system requires regulators to provide the ADC12EU050
1.2V operating voltage, National Semiconductor recommends the LP3878SD-ADJ Low Noise “Ceramic Stable” Adjustable Regulator or the LP3879 Low Noise “Ceramic Stable”
Regulator. Datasheets for both parts are available from the
National Semiconductor website.
30051117
FIGURE 22. DCAP RC Filter
The DCAP pin must be connected to AGND through a low
leakage, minimum 100nF capacitor. If the application is especially sensitive to close to the carrier phase noise, then it is
recommended to increase DCAP, up to a maximum of 10µF.
For other applications where close to the carrier phase noise
is not important, the capacitor can be kept small in order to
reduce costs and minimise board space. The corner frequency of this filter is determined by the equation:
f = 1/(2πRDCAPCDCAP)
2.9 BOARD LAYOUT CONSIDERATIONS
Proper grounding, layout and routing are essential to ensure
accurate conversion in any high speed ADC.
Maintaining separate analog and digital areas of the board is
recommended in order to achieve the specified performance.
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30
ADC12EU050
30051110
FIGURE 23. ADC12EU050 Application Diagram
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ADC12EU050
Programming Guide
3.0 THE SERIAL CONTROL INTERFACE
The ADC12EU050 provides several user controlled functions
which are accessed through a standard SPI compatible, 3
wire Serial Interface, as shown in the diagram below.
30051111
FIGURE 24. Three Wire Control Interface
Wired OR mode is supported in order to connect multiple ADC12EU050 devices to one SPI Master. The clock and data
buses are common to all ADC devices, and the chip select
SSEL is used to control which SPI is currently active. The SPI
master must have a unique pin available for each ADC’s
SSEL. The diagram below illustrates the connection.
30051112
FIGURE 25. Multi-Wire Control Interface
When connecting multiple devices, the SDATA pin must be set
in Open Drain mode. Open Drain mode is enabled by setting
the SPIOD bit in the Top Control Register of all connected
ADC12EU050 devices. When SDATA is in open drain mode,
the user must ensure that a pull-up resistor is connected to
the SDATA bus. Further details on Open Drain mode are given
in .
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3.1 SERIAL CONTROL INTERFACE PROTOCOL
Both read and write transactions are made up of eight address
bits and eight data bits. The final address bit of the address
phase determines whether the transaction will be a read
transaction or a write transaction – logic level low for write,
logic level high for read. The following diagram shows the
protocol.
32
ADC12EU050
30051113
FIGURE 26. Serial Control Interface Protocol
The eight address bits, A[7:1] + R/W, are sent first. The data,
D[7:0], is then sent for a write transaction, or D[7:0] is received
for a read transaction. Address and data are sent and received with the most-significant-bit (MSB) first. The SPI is
enabled using the active low input SSEL. If SSEL is high the SPI
cannot be accessed, although SSEL is not a reset signal and
registers will maintain their value when SSEL is toggled. SSEL
must be held low during the entire transaction.
Timing requirements for the Serial Interface are described in
the Electrical Characteristics section of this document.
be used. In Open Drain mode, the ADC’s SDATA will pull the
output low, and SDATA will be pulled up to the external level
by a pull-up resistor connected to the board’s positive voltage
rail, VEXT.
The intended use of Open Drain mode is when the ADC, including VDR, is running at 1.2V, and a VEXT of 1.8V is required.
Open Drain mode is enabled by setting the SPIOD bit in the
Top Control Register via the Serial Interface. When in Open
Drain mode, a pull-up resistor (RSDATA) must be connected
between SDATA and VEXT. The table of Electrical Specifications shows the required settings for VEXT and RSDATA.
3.2 SERIAL INTERFACE TRANSACTION
CANCELLATION
A transaction may be cancelled before the address and data
stages are completed by toggling SSEL to high at any stage
during an SPI access. This action is not recommended, as
transaction cancellation during a write transaction may corrupt register contents and during a read transaction will result
in incorrect data.
After canceling a transaction with SSEL the ADC may be in an
unknown state due to an incomplete and hence corrupted
write to a register. It is therefore recommended to reset the
chip via Software Reset (SRES) after a cancelled transaction.
3.4 SERIAL CONTROL INTERFACE READ AND WRITE
SPEED
SCLK (pin 45) controls the speed of interaction with the ADC.
The SPI interface supports write to and read from speeds as
defined in the Electrical Specifications section of this document.
3.5 SERIAL CONTROL INTERFACE REGISTER
DESCRIPTIONS
The following tables show the complete set of user accessible
SPI registers, with descriptions of the functionality of each bit.
Reset values of all registers are also described in the tables
below.
3.3 SDATA PAD OPEN DRAIN MODE
If the SDATA voltage at the board level is required to be higher
than the ADC12EU050’s VDR, the Open Drain mode should
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ADC12EU050
Register Index
Address
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
Default
Reserved
CBR
40/50
SRES
SPIOD
SLEEP
PD
00h
PD5
PD4
PD3
PD2
PD1
PD0
00h
Reserved
Reserved
IOR
OL[3]
OL[2]
OL[1]
OL[0]
00h
Reserved
Reserved
Reserved
Reserved
Reserved
SHBW
STCAL
00h
100HYS
50HYS
20HYS
Custom
Pattern
[4]
Custom
Pattern
[3]
Custom
Pattern
[2]
Custom
Pattern
[1]
Custom
Pattern
[0]
00h
Reserved
Reserved
Custom
Pattern
[11]
Custom
Pattern
[10]
Custom
Pattern
[9]
Custom
Pattern
[8]
00h
a[2]
a[1]
a[0]
b[2]
b[1]
b[0]
00h
Reserved
Reserved
EQON
DFS
MSB
TSEL[1]
TSEL[0]
00h
Reserved
Reserved
TX_term
I_drive[1]
I_drive[0]
OCM
SLVS
00h
ID [6]
ID [5]
ID [4]
ID [3]
ID [2]
ID [1]
ID [0]
Top Control Register
00h
Reserved
ADC / LVDS Channel Power Down Register
02h
PD7
PD6
Modulator Overload Control Register
04h
Reserved
PLL Control Register
08h
Reserved
LVDS Input Clock Hysteresis
0Ah
Reserved
Reserved
INVCLK
10HYSOFF HYSOFF
00h
Serializer Custom Pattern 0 Register
10h
Custom
Pattern
[7]
Custom
Pattern
[6]
Custom
Pattern
[5]
Serializer Custom Pattern 1 Register
12h
Reserved
Reserved
Decimator Clipping Control Register
14h
Reserved
Reserved
Decimator Control Register
16h
Reserved
LVDS Control Register
18h
Reserved
Chip ID Register
1Eh
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ID [7]
34
ADC12EU050
Top Control Register
Address:
Attributes
00h
Write Only.
Register 01h reads back contents of register 00h, if CBR is set.
The Top Control Register is the basic initialization and control register for the device.
b[7]
Description
b[6]
Reserved
Default
0
0
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
CBR
40/50
SRES
SPIOD
SLEEP
PD
0
0
0
0
0
0
Bit
7:6
5
Description
CBR: Control Bus Read. When asserted register 00h (this register) can be read, but no other registers.
When de-asserted all other registers can be read, but not register 00h.
Register 00h cannot be read from address 01h. All other registers can be read back.
Register 00h can be read from address 01h. All other registers cannot be read back.
40/50: Selects the ADC sample rate. This bit should be set according to the applied input clock to obtain
optimal performance.
0
1
3
00 h
Reserved. Write as zero for future compatibility.
0
1
4
HEX
45-50MSPS
40-45MSPS
SRES: Software Reset. When asserted the software reset will reset the whole device. SRES performs
the same function as the hardware reset (RST pin).
The SRES is self clearing in approximately 2µs.
0
1
2
SPIOD: SPI Open Drain mode.
0
1
1
Digital Logic Output
Open Drain Mode. Enables SPI Driver to operate above VDR
SLEEP: Sleep Mode. Powers down the device with the exception of the PLL and the reference blocks.
The time to wake-up from sleep mode is < 10µs.
0
1
0
Software Reset Inactive
Software Reset Active
Sleep Mode Inactive
Sleep Mode Active
PD: Power Down Mode. Completely powers down the device. The power up time is approximately
20ms.
0
1
PD Mode Inactive, device operates normally
PD Mode Active, device powered down
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ADC12EU050
ADC / LVDS Channel Power Down Register
Address:
Attributes
02h
Write Only.
Register 03h reads back contents of register 02h.
The ADC/LVDS Channel Power Down Register provides the capability to independently power down each ADC channel.
Description
Default
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
0
0
0
Bit
7
Description
PD7: Power Down Channel 7
0
1
6
PD6: Power Down Channel 6
0
1
5
Channel Active
Channel Power Down
PD0: Power Down Channel 0
0
1
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Channel Active
Channel Power Down
PD1: Power Down Channel 1
0
1
0
Channel Active
Channel Power Down
PD2: Power Down Channel 2
0
1
1
Channel Active
Channel Power Down
PD3: Power Down Channel 3
0
1
2
Channel Active
Channel Power Down
PD4: Power Down Channel 4
0
1
3
Channel Active
Channel Power Down
PD5: Power Down Channel
0
1
4
Channel Active
Channel Power Down
Channel Active
Channel Power Down
36
HEX
00 h
ADC12EU050
Modulator Overload Control Register
Address:
Attributes
04h
Write Only.
Register 05h reads back contents of register 04h.
b[7]
b[6]
Description
b[5]
Reserved
Default
0
0
b[4]
4
b[2]
0
0
IOR
0
b[1]
b[0]
HEX
0
0
00 h
OL[3:0]
0
Bit
7:5
b[3]
Description
Reserved. Write as zero for future compatibility.
IOR: Enable IOR Mode (Instant Overload Recovery)
This bit can be used to quickly enable IOR mode with the default IOR settings for DGF (see register
14h) and OL.
0
1
3:0
IOR Mode Disabled
IOR Mode Enabled
OL[3:0]: The bits define the differential peak voltage (in VPP) at which the analog input signal is clipped
when in IOR mode. In IOR mode the analog clipping is set to 1.746 VPP. In the default ADC mode
clipping of the analog input signal is disabled.
Should it be decided to over-ride the default setting, it is important to follow the guidelines for setting
OL, as described in the Applications Information section.
OL[3:0]
Clipping Voltage
VPP
0 (IOR Mode default)
1.746
0001
1.694
0010
1.64
0011
1.586
0100
1.534
0101
1.480
0110
1.426
0111
1.374
1000
2.172
1001
2.120
1010
2.066
1011
2.012
1100
1.960
1101
1.906
1110
1.852
1111
1.800
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ADC12EU050
PLL Control Register
Address:
Attributes
08h
Write Only.
Register 09h reads back contents of register 08h.
b[7]
b[6]
b[5]
0
0
0
Description
Default
b[4]
1
b[2]
0
0
Reserved
0
Bit
7:2
b[3]
b[1]
b[0]
SHBW
STCAL
0
0
HEX
00 h
Description
Reserved. Write as zero for future compatibility.
SHBW: Set PLL to High Bandwidth. The selection of the PLL bandwidth permits to set the sensitivity
of the PLL to input clock jitter. Less bandwidth decreases the sensitivity to input clock jitter.
The PLL Bandwidth is related to the sampling frequency, the exact values of which can be found in the
electrical specifications table.
The PLL will pass any input clock jitter up to the PLL bandwidth, while jitter above the PLL bandwidth
will be attenuated. Low bandwidth mode should be used for high jitter input clocks, while high bandwidth
mode can be used for high-quality, low jitter input clocks.
0
1
0
STCAL: Start VCO calibration. The calibration can be manually started in order to assure that the
frequency tuning margin is maximum, for example, in case of large temperature change during
operation it can be useful to restart the calibration.
0
1
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PLL bandwidth is set to Low Bandwidth (400kHz).
PLL bandwidth is set to High Bandwidth (1.4MHz).
The VCO calibration starts automatically if a Loss of Lock is detected
The VCO calibration is restarted.
38
ADC12EU050
LVDS Input Clock – Hysteresis
Address:
Attributes
0Ah
Write Only.
Register 0Bh reads back contents of register 0Ah.
b[7]
Description
Default
b[6]
Reserved
0
0
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
INVCLK
100HYS
50HYS
20HYS
10HYS
OFF
HYSOFF
0
0
0
0
0
0
Bit
7:6
5
Reserved. Write as zero for future compatibility.
INVCLK: Invert Input Reference Clock. This bit is used to invert the input clock.
Normal operation (10mV hysteresis)
20mV hysteresis. (LVDS input clock only)
10HYSOFF: Disable 10mV hysteresis. 10mV hysteresis is the default setting. This bit is used to
disable 10mV hysteresis, in the case where another hysteresis setting is desired, for example when
using a CMOS input clock.
0
1
0
Normal operation (10mV hysteresis)
50mV hysteresis. (CMOS input clock only)
20HYS: Enable 20mV hysteresis. This bit enables 20mV hysteresis. It should be used for an LVDS
input clock only.
0
1
1
Normal operation (10mV hysteresis)
100mV hysteresis (CMOS input clock only)
50HYS: Enable 50mV hysteresis. This bit enables 50mV hysteresis. It should be used for a CMOS
input clock only.
0
1
2
Reference input clock not inverted.
Reference input clock inverted.
100HYS: Enable 100mV hysteresis. This bit enables 100mV hysteresis. It should be used for a CMOS
input clock only.
0
1
3
00 h
Description
0
1
4
HEX
10mV hysteresis. (LVDS input clock only)
10mV hysteresis disabled.
HYSOFF: Disable all hysteresis settings. This bit is used to disable all hysteresis settings.
0
1
Normal operation (10mV hysteresis)
All hysteresis settings disabled.
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ADC12EU050
Serializer Custom Pattern 0 Register
Address:
Attributes
10h
Write Only.
Register 11h reads back contents of Register 10h.
This register in conjunction with User Register 12 provides storage for the custom de-skew pattern. See User Register 16 for a
description of how this training sequence is used.
b[7]
b[6]
b[5]
0
0
0
Description
Default
b[4]
b[3]
b[2]
b[1]
b[0]
HEX
0
0
0
00 h
Custom Pattern [7:0]
0
0
Bit
Description
7:0
Custom Pattern [7:0]. This pattern forms the lower byte of Custom Pattern [11:0] which is output by
the serializer when the Training Sequence Select bits (bits 1:0) of the Decimator Control Register are
set to select Training sequence 3.
Serializer Custom Pattern 1 Register
Address:
Attributes
12h
Write Only.
Register 13h reads back contents of Register 12h.
This register in conjunction with User Register 10 provides storage for the custom de-skew pattern. See User Register 16 for a
description of how this training sequence is used.
b[7]
b[6]
0
0
Description
Default
b[5]
b[4]
b[3]
0
0
Reserved
b[2]
b[1]
b[0]
HEX
0
00 h
Custom Pattern [11:8]
0
Bit
0
0
Description
7:4
Reserved. Write as zero for future compatibility.
3:0
Custom Pattern [11:8]. This pattern forms the upper 4 bits of Custom Pattern [11:0] which is output
by the serializer when the Training Sequence Select bits (bits 1:0) of the Decimator Control Register
are set to select Training sequence 3.
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40
ADC12EU050
Decimator Clipping Control Register
Address:
Attributes
14h
Write Only.
Register 15h reads back contents of Register 14h.
Description
Default
b[7]
b[6]
CGS
Reserved
0
0
b[5]
b[4]
b[3]
b[2]
0
0
a[2:0]
0
b[1]
b[0]
HEX
0
00 h
b[2:0]
0
0
Bit
Description
7
CGS: Custom Gain Setting. This bit is used to override the automatic gain settings for ADC and IOR
modes. If the user wishes to write a custom digital gain coefficient using a[2:0] and b[2:0] of this register,
then the CGS bit must be set.
0
1
6
5:3
Normal operation Automatic gain settings used
Custom Gain Setting Gain setting from a[2:0] and b[2:0] used.
Reserved. Write as zero for future compatibility.
a[2:0]: Digital Gain Coefficient. In clipping mode the input range of an ADC channel is limited to
1.56Vpp. In ADC mode the input range is 2.10Vpp. The output of the digital filter has to be scaled
according to the selected mode (the filter data has to be mapped in to the 12bit output data), the
difference between 1.6Vpp and 2.2Vpp is -2.6dB, hence the digital filter gain has to be set to 2.6dB
when in IOR mode and to 0dB when in clipping mode (default mode) . This is performed by setting a
Digital Gain Factor which is calculated using the following formula:
The mapping of the coefficient values for a[2:0] is as follows:
011 = Not used. Defaults to 2
010 = 2
001 = 1
000 = 0
111 = -1
110 = -2
101 = Not used. Defaults to -2
100 = Not used. Defaults to -2
The mapping of the coefficient values for b[2:0] is shown below. The table on the following page shows
the available Digital Gain Coefficient settings.
2:0
b[2:0]: Digital Gain Coefficient.
The mapping of the coefficient values for b[2:0] is as follows:
011 = Not used. Defaults to 2
010 = 2
001 = 1
000 = 0
111 = -1
110 = -2
101 = Not used. Defaults to -2
100 = Not used. Defaults to -2
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ADC12EU050
Coefficent a[2:0]
Coefficent b[2:0]
Digital Gain (dB)
Equivalent full scale
input range (VPP)
010
010
4.16
1.30
010
001
3.95
1.33
010
000
3.74
1.37
010
111
3.52
1.40
010
110
3.29
1.44
001
001
3.06
1.48
001
000
2.82
1.52
001
111
2.58
1.56
001
110
2.33
1.61
000
001
2.07
1.65
000
000
1.80
1.71
000
111
1.53
1.76
000
110
1.24
1.82
111
001
0.95
1.88
111
000
0.64
1.95
111
111
0.33
2.02
111
110
000
2.10
110
001
-0.34
2.18
110
000
-0.70
2.28
110
111
-1.07
2.38
110
110
-1.45
2.48
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42
IOR Mode default setting
ADC mode default setting
ADC12EU050
Decimator Control Register
Address:
Attributes
16h
Write Only.
Register 17h reads back contents of register 16h.
b[7]
Description
Default
b[6]
b[5]
Reserved
0
0
b[4]
b[3]
b[2]
EQON
DFS
MSB
0
0
0
0
Bit
7:5
4
TSEL[1:0]
0
0
00 h
EQON: Equalizer Enable. This bit is used to enable or disable the digital equalizer. The equalizer can
be switched on in order to reduce the group delay of the output data, at the cost of increased power.
Equalizer disabled
Equalizer enabled
DFS: Data Format Select. Selects the format, either Offset Binary or Twos Complement of the output
data
2s Complement
Offset Binary
MSB: Select the bit order of the LVDS output data stream
0
1
1:0
HEX
Reserved. Write as zero for future compatibility.
0
1
2
b[0]
Description
0
1
3
b[1]
LSB first
MSB first
TSEL[1:0]: Training Sequence Select. These bits select the LVDS output data.
The default mode of operation is where the filter output data is serialized.
In the remaining modes the selected training sequence is repeatedly output from the serializer this
allows the receiving data capture circuitry to perform the de-skewing process.
One of three known words can be selected, the first two words are hard-coded in the block, the third
one, the custom pattern, is written into User Registers 10h and 12h the Serializer Custom Pattern
Registers.
Note. The outputs bit-clock and word-clock are not affected by the value of the Training Sequence
Select bits.
00
01
10
11
ADC data[11:0]
Training sequence 1: 000000111111
Training sequence 2: 101010101010
Training sequence 3: custom pattern
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ADC12EU050
LVDS Control Register
Address:
Attributes
18h
Write Only.
Register 19h reads back contents of register 18h.
b[7]
Description
b[6]
b[5]
Reserved
Default
0
0
b[4]
b[3]
TX_term
0
0
I_drive[1:0]
0
Bit
7:5
4
b[0]
OCM
SLVS
0
0
0
HEX
00 h
Reserved. Write as zero for future compatibility.
TX_term: Enable Internal 100 Ohm termination for data outputs.
Internal 100 ohm termination disabled
Internal 100 ohm termination enabled
I_drive[1:0]: Controls the current drive of the data outputs.
00
01
10
11
1
b[1]
Description
0
1
3:2
b[2]
2.5 mA
3.5 mA
Reserved
5 mA
OCM: Output Common mode. Allows the output common mode to be shifted depending on the setting
of VDR.
If bit 0 of this register, SLVS, is set to 1 then changing OCM will have no impact on the output common
mode. The output common mode in SLVS mode is fixed, as described in the Electrical Specifications
section of this datasheet.
For VDR = 1.2V, OCM must be set to 0.
For VDR = 1.8V, OCM must be set to 1.
0
0
Output Common Mode, VOCM = 1.0V
1
Output Common Mode, VOCM = 1.25V
SLVS: Select the format for output data, either LVDS or SLVS. The differences in timing and electrical
specifications between the two modes can be seen in the Electrical Specifications section of the
datasheet.
If this bit is set to 1 (SLVS mode), OCM has no effect and the output common mode will be set for
SLVS as described in the Electrical Specifications section of this datasheet.
When LVDS mode is selected, the output common mode must be selected using the OCM bit of this
register.
0
1
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LVDS Mode
SLVS Mode
44
Address:
Attributes
1Eh
Read Only.
b[7]
b[6]
b[5]
b[4]
Description
Default
b[3]
0
0
0
0
0
Bit
7:0
b[2]
b[1]
b[0]
HEX
0
0
0
00 h
ID [7:0]
Description
ID[7:0]: Chip ID Register. Reading from this register will provide the chip version.
The expected Chip ID for the ADC12EU050 is 12.4.
X = ID[7]*8 + ID[6]*4 + ID[5]*2 + ID[4]
Y = ID[3]*8 + ID[2]*4 + ID[1]*2 + ID[0]
Chip ID = Version X.Y
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ADC12EU050
Chip ID Register
ADC12EU050
Physical Dimensions inches (millimeters) unless otherwise noted
68-Lead LLP Package 10x10x1.0mm, 0.5mm Pitch
Ordering Numbers ADC12EU050CIPLQ
NS Package Number LQA68A
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46
ADC12EU050
Notes
47
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ADC12EU050 Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital
Converter
Notes
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