TI TPS61300

TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
2 TM
1.5A/4.1A Multiple LED Camera Flash Driver With I C Compatible Interface
Check for Samples: TPS61300, TPS61301, TPS61305
FEATURES
DESCRIPTION
•
The TPS6130x device is based on a high-frequency
synchronous boost topology with constant current
sinks to drive up to three white LEDs in parallel
(400mA/800mA/400mA maximum flash current). The
extended high-current mode (HC_SEL) allows up
to 1025mA/2050mA/1025mA flash current out of
the storage capacitor.
23
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Four Operational Modes
– DC Light and Flashlight
– Voltage Regulated Converter: 3.8V...5.7V
– Standby: 2mA (typ.)
Storage Capacitor Friendly Solution
Automatic VF and ESR Calibration
Power-Save Mode for Improved Efficiency at
Low Output Power, Up to 95% Efficiency
Output Voltage Remains Regulated When
Input Voltage Exceeds Nominal Output Voltage
I2C Compatible Interface up to 3.4Mbits/s
Zero Latency Tx-Masking Input
Hardware Voltage Mode Selection Input
(TPS61300, TPS61301)
DC Light Mode Selection Input
(TPS61300, TPS61306)
Hardware Reset Input (TPS61301, TPS61305)
LED Temperature Monitoring (TPS61305)
Privacy Indicator LED Output
Integrated LED Safety Timer
Total Solution Size of Less Than 25 mm2
(<1mm height)
Available in a 20-Pin NanoFree™ (CSP)
The high-capacity storage capacitor on the output of
the boost regulator provides the high-peak flash LED
current, thereby reducing the peak current demand
from the battery to a minimum.
The 2-MHz switching frequency allows the use of
small and low profile 2.2mH inductors. To optimize
overall efficiency, the device operates with a 400mV
LED feedback voltage.
The TPS6130x device not only operates as a
regulated current source, but also as a standard
voltage boost regulator. The device keeps the output
voltage regulated even when the input voltage
exceeds the nominal output voltage. The device
enters power-save mode operation at light load
currents to maintain high efficiency over the entire
load current range.
To simplify flashlight synchronization with the camera
module, the device offers a trigger pin
(FLASH_SYNC) for zero latency LED turn-on time.
APPLICATIONS
•
•
•
Single/Dual/Triple White LED Flashlight Supply
for Cell Phones and Smart-Phones
LED Based Xenon "Killer" Flashlight
Audio Amplifier Power Supply
TPS61300
L
2.2 mH
2.5 V..5.5 V
SW
SW
AVIN
HC_SEL
CI
PHONE POWER ON
VOUT
SUPER-CAP
1
BAL
CO
10 mF
D1
D2
LED1
ENDCL
FLASH_SYNC LED2
CAMERA ENGINE
LED3
I2C I/F
SCL
SDA
INDLED
Privacy
Indicator
1.8 V
Tx- MASK
ENVM
GPIO/PG
AGND
PGND
PGND
FLASH READY
Figure 1. Typical Application
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TPS61300, TPS61301, TPS61305
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
(1)
PART NUMBER (1)
PACKAGE MARKING
PACKAGE
DEVICE SPECIFIC FEATURES (2)
TPS61300YFF
TPS61300
CSP-20
Hardware Enable DC Light Input (ENDCL)
TPS61301YFF
TPS61301
CSP-20
Hardware Enable / Disable Input (NRESET)
TPS61305YFF
TPS61305
CSP-20
Hardware Enable / Disable Input (NRESET)
LED Temperature Monitoring Input (TS)
TPS61306YFF (3)
TPS61306
CSP-20
Hardware Enable DC Light Input (ENDCL)
LED Temperature Monitoring Input (TS)
The YFF package is available in tape and reel. Add R suffix (TPS6130xYFFR) to order quantities of 3000 parts per reel, T suffix for 250
parts per reel.
For more details, refer to the section Application Diagrams.
Device status is Product Preview. Please contact TI for more details.
(2)
(3)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VI
(1)
VALUE
UNIT
Voltage range on AVIN, VOUT, SW, LED1, LED2, LED3 (2)
–0.3 to 7
V
Voltage range on SCL, SDA, FLASH_SYNC, ENDCL, NRESET, ENVM, GPIO/PG (2)
–0.3 to 7
V
Voltage range on HC_SEL, Tx-MASK, TS, BAL
(2)
Current on GPIO/PG
Power dissipation
TA
TJ
Operating ambient temperature range
(MAX)
Maximum operating junction temperature
Storage temperature range
Human body model
ESD rating
(1)
(2)
(3)
(4)
(4)
V
±25
mA
Internally limited
(3)
Tstg
–0.3 to 7
–40 to 85
°C
150
°C
–65 to 150
°C
2
kV
Charge device model
500
V
Machine model
100
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (qJA), as given by the following equation: TA(max) = TJ(max) – (qJA × PD(max))
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
THERMAL RESISTANCE (1)
qJA
THERMAL RESISTANCE (1)
qJB
POWER RATING
TA = 25°C
DERATING FACTOR
ABOVE (2) TA = 25°C
YFF
71°C/W
21°C/W
1.4 W
14mW/°C
Simulated with high-K board
Maximum power dissipation is a function of TJ(max), qJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/ qJA.
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤ TJ ≤ 125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
2.5
5.5
UNIT
SUPPLY CURRENT
VIN
Input voltage range
IQ
Operating quiescent current into AVIN
ISD
ISTBY
IOUT = 0 mA, device not switching
–40°C ≤ TJ ≤ +85°C
590
IOUT(DC) = 0mA, PWM operation
VOUT = 4.95V, voltage regulation mode
11.3
HC_SEL = 0, –40°C ≤ TJ ≤ +85°C
1
5
Standby current
HC_SEL = 1, storage capacitor balanced
–40°C ≤ TJ ≤ +85°C
2
5
Pre-charge current
VOUT = 2.3V, 2.5V ≤ VIN ≤ 5.5V
150
Undervoltage lockout threshold
(analog circuitry)
40
VIN falling
mA
mA
Shutdown current
Pre-charge hysteresis (referred to VOUT)
VUVLO
700
V
mA
mA
mA
75
2.3
mV
2.4
V
OUTPUT
Output voltage range
VOUT
OVP
Current regulation mode
VIN
5.5
V
Voltage regulation mode
3.825
5.7
V
–2%
2%
Internal feedback voltage accuracy
2.5V ≤ VIN ≤ 4.8V, –20°C ≤ TJ ≤ +125°C
Boost mode, PWM voltage regulation
Power-save mode ripple voltage
IOUT = 10 mA
Output overvoltage protection
Output overvoltage protection hysteresis
0.015 VOUT
VOUT rising, 0000 ≤ OV[3:0] ≤ 0100
4.5
VOUT rising, 0101 ≤ OV[3:0] ≤ 1111
5.8
VOUT falling, 0101 ≤ OV[3:0] ≤ 1111
VP-P
4.65
4.8
V
6.0
6.2
V
0.15
V
POWER SWITCH
rDS(on)
Switch MOSFET on-resistance
VOUT = VGS = 3.6 V
90
Rectifier MOSFET on-resistance
VOUT = VGS = 3.6 V
135
Ilkg(SW)
Leakage into SW
VOUT = 0V, SW = 3.6V, –40°C ≤ TJ ≤ +85°C
0.3
Ilim
Rectifier valley current limit (open-loop)
VOUT = 4.95V, HC_SEL = 0
–20°C ≤ TJ ≤ +85°C
PWM operation, relative to selected ILIM
–15
mΩ
mΩ
4
mA
+15
%
OSCILLATOR
fOSC
Oscillator frequency
fACC
Oscillator frequency
1.92
–10
MHz
+7
%
THERMAL SHUTDOWN, HOT DIE DETECTOR
Thermal shutdown (1)
140
Thermal shutdown hysteresis (1)
Hot die detector accuracy (1)
(1)
160
°C
20
–8
°C
8
°C
Verified by characterization. Not tested in production.
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
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3
TPS61300, TPS61301, TPS61305
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤ TJ ≤ 125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LED CURRENT REGULATOR
LED1/3 current accuracy (1)
HC_SEL = 0
LED2 current accuracy
(1)
LED1/3 current accuracy
(1)
HC_SEL = 1
LED2 current accuracy (1)
0.4V ≤ VLED1/3 ≤ 2.0V
00 ≤ DCLC13[1:0] ≤ 11, TJ = +85°C
–10
+10
%
0.4V ≤ VLED1/3 ≤ 2.0V
00 ≤ FC13[1:0] ≤ 11, TJ = +85°C
–7.5
+7.5
%
0.4V ≤ VLED2 ≤ 2.0V
000 ≤ DCLC2[2:0] ≤ 111, TJ = +85°C
–10
+10
%
0.4V ≤ VLED2 ≤ 2.0V
000 ≤ FC2[2:0] ≤ 111, TJ = +85°C
–7.5
+7.5
%
0.4V ≤ VLED1/3 ≤ 2.0V
00 ≤ DCLC13[1:0] ≤ 11, TJ = +85°C
–10
+10
%
0.4V ≤ VLED1/3 ≤ 2.0V
00 ≤ FC13[1:0] ≤ 11, TJ = +85°C
–10
+10
%
0.4V ≤ VLED2 ≤ 2.0V
000 ≤ DCLC2[2:0] ≤ 111, TJ = +85°C
–10
+10
%
0.4V ≤ VLED1/3 ≤ 2.0V
000 ≤ FC2[2:0] ≤ 111, TJ = +85°C
–10
+10
%
LED1/3 current matching (1)
–10
LED1/2/3 current temperature coefficient
1.5V ≤ (VIN-VINDLED) ≤ 2.5V
2.6mA ≤ IINDLED ≤ 7.9mA
TJ = +25°C
INDLED current accuracy
–20
INDLED current temperature coefficient
VDO
(1)
4
+10
0.05
%
%/°C
+20
%
0.04
%/°C
LED1/2/3 sense voltage
ILED1-3 = full-scale current, HC_SEL = 0
400
mV
LED1/2/3 sense voltage
ILED1-3 = full-scale current, HC_SEL = 1
400
VOUT dropout voltage
IOUT = -7.5mA, device not switching
LED1/2/3 input leakage current
VLED1/2/3 = VOUT = 5V, –40°C ≤ TJ ≤ +85°C
INDLED input leakage current
VINDLED = 0V, –40°C ≤ TJ ≤ +85°C
450
mV
220
mV
0.1
4
mA
0.1
1
mA
Verified by characterization. Not tested in production.
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤ TJ ≤ 125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.7
3.0
mA
100
mV
STORAGE CAPACITOR ACTIVE CELL BALANCING
Active cell balancing circuitry
quiescent current into VOUT
HC_SEL = 1, storage capacitor balanced
–40°C ≤ TJ ≤ +85°C
Active cell balancing accuracy
(VOUT – BAL) vs. BAL voltage difference
Storage capacitor balanced HC_SEL = 1
VOUT = 5.7V
BAL output drive capability
VOUT = 4.95V, Sink and source current
Active discharge resistor
HC_SEL = 0, device in shutdown mode
VOUT to BAL and BAL to GND
–100
±10
±15
0.85
mA
1.5
kΩ
LED TEMPERATURE MONITORING (TPS61305)
IO(TS)
Temperature Sense Current Source
Thermistor bias current
TS Resistance (Warning Temperature) LEDWARN bit = 1, TJ≥ 25°C
TS Resistance (Hot Temperature)
LEDHOT bit = 1, TJ≥ 25°C
23.8
mA
39
44.5
50
kΩ
12.5
14.5
16.5
kΩ
SDA, SCL, GPIO/PG, ENVM, Tx-MASK, ENDCL, NRESET, FLASH_SYNC, HC_SEL
V(IH)
High-level input voltage
V(IL)
Low-level input voltage
V(OL)
V(OH)
I(LKG)
RPD
C(IN)
1.2
V
0.4
V
Low-level output voltage (SDA)
IOL = 8mA
0.3
V
Low-level output voltage (GPIO)
DIR = 1, IOL = 5mA
0.3
V
High-level output voltage (GPIO)
DIR = 1, GPIOTYPE = 0, IOH = 8mA
Logic input leakage current
Input connected to VIN or GND
–40°C ≤ TJ ≤ +85°C
0.01
ENVM pull-down resistance
ENVM ≤ 0.4 V
350
kΩ
ENDCL, NRESET pull-down
resistance
ENDCL, NRESET ≤ 0.4 V
350
kΩ
FLASH_SYNC pull-down resistance
FLASH_SYNC ≤ 0.4 V
350
kΩ
Tx-MASK pull-down resistance
Tx-MASK ≤ 0.4 V
350
kΩ
HC_SEL pull-down resistance
HC_SEL ≤ 0.4 V
350
kΩ
SDA Input Capacitance
SDA = VIN or GND
9
pF
SCL Input Capacitance
SCL = VIN or GND
4
pF
GPIO/PG Input Capacitance
DIR = 0, GPIO/PG = VIN or GND
9
pF
ENVM Input Capacitance
ENVM = VIN or GND
4
pF
ENDCL Input Capacitance
ENDCL = VIN or GND
3
pF
HC_SEL Input Capacitance
HC_SEL = VIN or GND
3.5
pF
Tx-MASK Input Capacitance
Tx-MASK = VIN or GND
4
pF
FLASH_SYNC Input Capacitance
FLASH_SYNC = VIN or GND
3
pF
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
VIN–0.4
V
0.1
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mA
5
TPS61300, TPS61301, TPS61305
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤ TJ ≤ 125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING
tNRESET
Reset pulse width
10
Start-up time
LED current settling time (1) triggered
by a rising edge on FLASH_SYNC
LED current settling time (1) triggered
by Tx-MASK
(1)
ms
From shutdown into DC light mode
HC_SEL = 0, ILED = 100mA
1.4
ms
From shutdown into voltage mode via ENVM
HC_SEL = 0, IOUT = 0mA
550
ms
MODE_CTRL[1:0] = 10, HC_SEL = 0
ILED2 = from 0mA to 800mA
400
ms
MODE_CTRL[1:0] = 10, HC_SEL = 1
ILED2 = from 0mA to 1800mA
16
ms
MODE_CTRL[1:0] = 10, HC_SEL = 0
ILED2 = from 800mA to 350mA
15
ms
Settling time to ±15% of the target value.
I2C INTERFACE TIMING CHARACTERISTICS (1)
PARAMETER
f(SCL)
TEST CONDITIONS
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
tBUF
MIN
MAX
UNIT
Standard mode
100
kHz
Fast mode
400
kHz
High-speed mode (write operation), CB – 100 pF max
3.4
MHz
High-speed mode (read operation), CB – 100 pF max
3.4
MHz
High-speed mode (write operation), CB – 400 pF max
1.7
MHz
High-speed mode (read operation), CB – 400 pF max
1.7
MHz
Standard mode
4.7
ms
Fast mode
1.3
ms
4
ms
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
4.7
ms
Standard mode
tHD, tSTA
tLOW
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
Fast mode
1.3
ms
High-speed mode, CB – 100 pF max
160
ns
High-speed mode, CB – 400 pF max
320
ns
4
ms
600
ns
High-speed mode, CB – 100 pF max
60
ns
High-speed mode, CB – 400 pF max
120
ns
Standard mode
4.7
ms
Standard mode
tHIGH
Fast mode
HIGH Period of the SCL Clock
tSU, tSTA
Setup Time for a Repeated START
Condition
tSU, tDAT Data Setup Time
tHD, tDAT Data Hold Time
(1)
6
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
High-speed mode
10
Standard mode
0
3.45
ms
Fast mode
0
0.9
ms
High-speed mode, CB – 100 pF max
0
70
ns
High-speed mode, CB – 400 pF max
0
150
ns
ns
Specified by design. Not tested in production.
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
I2C INTERFACE TIMING CHARACTERISTICS(1) (continued)
PARAMETER
tRCL
TEST CONDITIONS
Rise Time of SCL Signal
MIN
MAX
UNIT
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
10
40
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
tRCL1
tFCL
tRDA
tFDA
Rise Time of SCL Signal After a
Repeated START Condition and After
an Acknowledge BIT
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
tSU, tSTO Setup Time for STOP Condition
CB
20
80
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
Standard mode
4
ms
Fast mode
600
ns
High-speed mode
160
ns
Capacitive Load for SDA and SCL
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
400
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ns
pF
7
TPS61300, TPS61301, TPS61305
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
www.ti.com
I2C TIMING DIAGRAMS
SDA
tf
tLOW
tsu;DAT
tr
tf
tBUF
tr
thd;STA
SCL
thd;STA
thd;DAT
S
tsu;STA
tsu;STO
HIGH
Sr
P
S
Figure 2. Serial Interface Timing for F/S-Mode
Sr
Sr P
tfDA
trDA
SDAH
tsu;STA
thd;DAT
thd;STA
tsu;STO
tsu;DAT
SCLH
tfCL
trCL1
See Note A
trCL1
trCL
tHIGH
tLOW
tLOW
tHIGH
See Note A
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 3. Serial Interface Timing for H/S-Mode
8
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
DEVICE INFORMATION
APPLICATION DIAGRAMS
TPS61305
TPS61300
L
L
CI
PHONE POWER ON
BAL
AVIN
D1
D2
CI
2.5 V..5.5 V
HC_SEL
LED1
ENDCL
CAMERA ENGINE
VOUT
2.2 mH
CO
10 mF
D1
D2
LED1
LED3
SCL
SDA
CO
10 mF
NRESET
FLASH_SYNC LED2
I2C I/F
BAL
SUPER-CAP
2.5 V.. 5.5 V
SW
SW
VOUT
AVIN
HC_SEL
SUPER-CAP
2.2 mH
SW
SW
FLASH_SYNC
LED2
LED3
INDLED
Privacy
Indicator
High-Speed
I2C I/F
SCL
SDA
INDLED
Privacy
Indicator
Tx- MASK
Tx-MASK
ENVM
GPIO/PG
AGND
PGND
PGND
GPIO/PG
TS
NTC
AGND
Figure 4. TPS61300, Typical Application
Figure 5. : TPS61305, Typical Application
TPS61301
TPS61305
L
SW
SW
VOUT
2.2 mH
SUPER-CAP
2.2 mH
AVIN
2.5 V..5.5 V
CI
HC_SEL
SW
SW
BAL
VOUT
AVIN
CO
10mF
D1
D2
CI
2.5 V..5.5 V
HC _SEL
CO
10 mF D1
D2
ENDCL
NRESET
LED1
LED1
FLASH_SYNC
LED2
FLASH_SYNC
LED3
High- Speed
I2C I/F
BAL
SUPER-CAP
L
PGND
PGND
SCL
SDA
LED2
LED3
High-Speed
I2C I/F
INDLED
SCL
SDA
INDLED
Privacy
Indicator
Privacy
Indicator
Tx-MASK
Tx -MASK
ENVM
GPIO/PG
AGND
PGND
PGND
GPIO /PG
TS
NTC
AGND
Figure 6. TPS61301, Typical Application
PGND
PGND
Figure 7. TPS61306, Typical Application
PIN ASSIGNMENTS
CSP-20
(TOP VIEW)
CSP-20
(BOTTOM VIEW)
A4
B4
C4
D4
E4
E4
D4
C4
B4
A4
A3
B3
C3
D3
E3
E3
D3
C3
B3
A3
A2
B2
C2
D2
E2
E2
D2
C2
B2
A2
A1
B1
C1
D1
E1
E1
D1
C1
B1
A1
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TPS61300, TPS61301, TPS61305
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www.ti.com
PIN FUNCTIONS (TPS61300)
PIN
I/O
DESCRIPTION
NAME
NO.
AVIN
E4
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT
A2
O
This is the output voltage pin of the converter.
LED1
E2
I
LED2
E1
I
LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
(HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3
E3
I
FLASH_SYNC
B4
I
Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current level
(DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current level
(FC).
HC_SEL
B3
I
Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 400mA/800mA/400mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 925mA/1850mA/925mA
(ILED1/ILED2/ILED3).
SCL
B2
I
Serial interface clock line. This pin must not be left floating and must be terminated.
SDA
B1
I/O
Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG
D4
I/O
This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain or
a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
ENVM
C4
I
Enable pin for voltage mode converter. Pulling this pin high forces the device into voltage regulation mode
(VOUT is preset to a fixed value, 4.95V).
INDLED
A1
O
This pin provides a constant current source to drive low VF LEDs. Connect to LED anode.
ENDCL
D3
I
Hardware control pin for DC light operation. Pulling this pin high forces the device into DC light operation.
The ENDCL input is only active when the device is programmed into shutdown or voltage mode regulation.
LED1-3 inputs are controlled according to ENLED[3:1] bit settings.
Tx-MASK
C3
I
RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light operation,
thereby reducing almost instantaneously the peak current loading from the battery.
SW
C1
C2
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor. SW
is high impedance during shutdown.
BAL
A3
O
Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND
D1
D2
Power ground. Connect to AGND underneath IC.
AGND
A4
Analog ground.
10
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
PIN FUNCTIONS (TPS61301)
PIN
I/O
DESCRIPTION
NAME
NO.
AVIN
E4
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT
A2
O
This is the output voltage pin of the converter.
LED1
E2
I
LED2
E1
I
LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
(HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3
E3
I
FLASH_SYNC
B4
I
Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current
level (DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current
level (FC).
HC_SEL
B3
I
Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 400mA/800mA/400mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 925mA/1850mA/925mA
(ILED1/ILED2/ILED3).
SCL
B2
I
Serial interface clock line. This pin must not be left floating and must be terminated.
SDA
B1
I/O
Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG
D4
I/O
This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain
or a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
ENVM
C4
I
Enable pin for voltage mode converter. Pulling this pin high forces the device into voltage regulation mode
(VOUT is preset to a fixed value, 4.95V).
INDLED
A1
O
This pin provides a constant current source to drive low VF LEDs. Connect to LED anode.
NRESET
D3
I
Master hardware reset input. NRESET = LOW: The device is forced in shutdown mode and the I2C
control I/F is reset. NRESET = HIGH: The device is operating normally under the control of the I2C
interface.
Tx-MASK
C3
I
RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light
operation, thereby reducing almost instantaneously the peak current loading from the battery.
SW
C1
C2
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
SW is high impedance during shutdown.
BAL
A3
O
Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND
D1
D2
Power ground. Connect to AGND underneath IC.
AGND
A4
Analog ground.
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
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TPS61300, TPS61301, TPS61305
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www.ti.com
PIN FUNCTIONS (TPS61305)
PIN
I/O
DESCRIPTION
NAME
NO.
AVIN
E4
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT
A2
O
This is the output voltage pin of the converter.
LED1
E2
I
LED2
E1
I
LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
(HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3
E3
I
FLASH_SYNC
B4
I
Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current level
(DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current
level (FC).
HC_SEL
B3
I
Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 445mA/890mA/445mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 1025mA/2050mA/1025mA
(ILED1/ILED2/ILED3).
SCL
B2
I
Serial interface clock line. This pin must not be left floating and must be terminated.
SDA
B1
I/O
Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG
D4
I/O
This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain
or a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
TS
C4
I/O
NTC resistor connection. This pin can be used to monitor the LED temperature. Connect a 220kΩ NTC
resistor from the TS input to ground. In case this functionality is not desired, the TS input should be tied to
AVIN or left floating.
INDLED
A1
O
This pin provides a constant current source to drive low VF LEDs. Connect to LED anode.
NRESET
D3
I
Master hardware reset input.
NRESET = LOW: The device is forced in shutdown mode and the I2C control I/F is reset.
NRESET = HIGH: The device is operating normally under the control of the I2C interface.
Tx-MASK
C3
I
RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light
operation, thereby reducing almost instantaneously the peak current loading from the battery.
SW
C1
C2
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
SW is high impedance during shutdown.
BAL
A3
O
Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND
D1
D2
Power ground. Connect to AGND underneath IC.
AGND
A4
Analog ground.
12
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
PIN FUNCTIONS (TPS61306)
PIN
I/O
DESCRIPTION
NAME
NO.
AVIN
E4
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT
A2
O
This is the output voltage pin of the converter.
LED1
E2
I
LED2
E1
I
LED return input. This feedback pin regulates the LED current through the internal sense resistor by
regulating the voltage across it. The regulation operates with typically 400mV (HC_SEL = L) or 400mV
(HC_SEL = H) dropout voltage. Connect to the cathode of the LEDs.
LED3
E3
I
FLASH_SYNC
B4
I
Flashlight strobe pulse synchronization input.
FLASH_SYNC = LOW: The device is operating and regulating the LED current to the DC light current level
(DCLC).
FLASH_SYNC = HIGH: The device is operating and regulating the LED current to the flashlight current
level (FC).
HC_SEL
B3
I
Extended high-current mode selection input. This pin must not be left floating and must be terminated.
HC_SEL = LOW: LED direct drive mode. The power stage is active and the maximum LED currents are
defined as 445mA/890mA/445mA (ILED1/ILED2/ILED3).
HC_SEL = HIGH: Energy storage mode. In flash mode, the power stage is either active with reduced
current capability or disabled. The maximum LED current is defined as 1025mA/2050mA/1025mA
(ILED1/ILED2/ILED3).
SCL
B2
I
Serial interface clock line. This pin must not be left floating and must be terminated.
SDA
B1
I/O
Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG
D4
I/O
This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain
or a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
TS
C4
I/O
NTC resistor connection. This pin can be used to monitor the LED temperature. Connect a 220kΩ NTC
resistor from the TS input to ground. In case this functionality is not desired, the TS input should be tied to
AVIN or left floating.
INDLED
A1
O
This pin provides a constant current source to drive low VF LEDs. Connect to LED anode.
ENDCL
D3
I
Hardware control pin for DC light operation. Pulling this pin high forces the device into DC light operation.
The ENDCL input is only active when the device is programmed into shutdown or voltage mode regulation.
LED1-3 inputs are controlled according to ENLED[3:1] bit settings.
Tx-MASK
C3
I
RF PA synchronization control input. Pulling this pin high turns the LED from flashlight to DC light
operation, thereby reducing almost instantaneously the peak current loading from the battery.
SW
C1
C2
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
SW is high impedance during shutdown.
BAL
A3
O
Balancing output for dual cells super-capacitor. In steady-state operation, this output compensates for
leakage current mismatch between the cells.
PGND
D1
D2
Power ground. Connect to AGND underneath IC.
AGND
A4
Analog ground.
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
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TPS61300, TPS61301, TPS61305
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM (TPS61300)
SW
AVIN
Undervoltage
Lockout
Bias Supply
Bandgap
OVP
COMPARATOR
VREF = 1.238V
REF
Backgate
Control
VOUT
Hot Die
Indicator
TON
Control
ERROR
AMPLIFIER
VREF
HC _SEL
SQ
RQ
COMPARATOR
VOUT
EN
VOUT
2
P
CONTROL LOGIC
Z
Z
CURRENT
REGULATION
BAL
VOLTAGE
REGULATION
VLED Sense
SENSE FB
SCL
Max tON Timer
I 2C I/F
CURRENT
CONTROL
DAC
SDA
LED2
ON /OFF
P
SENSE FB
Slew-Rate
Controller
Oscillator
LED1
ON /OFF
CURRENT
CONTROL
DAC
FLASH_SYNC
P
SENSE FB
LED3
Control
Logic
Tx-MASK
ENDCL
P
Low-Side LED Current Regulator
ENVM
AVIN
INDLED
HC_SEL
INDC [1:0 ]
350 kΩ
High-Side LED Current Regulator
AGND
14
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PGND
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
FUNCTIONAL BLOCK DIAGRAM (TPS61301)
SW
AVIN
Undervoltage
Lockout
Bias Supply
Bandgap
OVP
COMPARATOR
VREF = 1.238V
REF
Backgate
Control
VOUT
Hot Die
Indicator
TON
Control
ERROR
AMPLIFIER
VREF
HC_SEL
S
Q
R
Q
VOUT
CONTROL LOGIC
P
EN
VOUT
2
COMPARATOR
Z
BAL
Z
VOLTAGE
REGULATION
CURRENT
REGULATION
VLED Sense
SENSE FB
Max tON Timer
SCL
I2C I/F
CURRENT
CONTROL
DAC
SDA
LED2
ON/OFF
P
SENSE FB
NRESET
Slew-Rate
Controller
Oscillator
LED1
ON/OFF
CURRENT
CONTROL
DAC
P
FLASH_SYNC
SENSE FB
LED3
Control
Logic
Tx- MASK
P
ENVM
Low-Side LED Current Regulator
AVIN
INDLED
HC_SEL
INDC[1:0]
350 kΩ
High-Side LED Current Regulator
AGND PGND
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TPS61300, TPS61301, TPS61305
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM (TPS61305)
SW
AVIN
Undervoltage
Lockout
Bias Supply
Bandgap
OVP
COMPARATOR
VREF = 1.238V
REF
Backgate
Control
VOUT
Hot Die
Indicator
TON
Control
ERROR
AMPLIFIER
VREF
S
Q
R
Q
HC_SEL
VOUT
CONTROL LOGIC
P
EN
VOUT
2
COMPARATOR
Z
BAL
Z
VOLTAGE
REGULATION
CURRENT
REGULATION
VLED Sense
SENSE FB
Max tON Timer
SCL
I2C I/F
CURRENT
CONTROL
DAC
SDA
LED2
ON/OFF
P
SENSE FB
NRESET
Slew-Rate
Controller
Oscillator
LED1
ON/OFF
CURRENT
CONTROL
DAC
P
FLASH_SYNC
SENSE FB
LED3
Tx-MASK
P
HC_SEL
Low-Side LED Current Regulator
Control
Logic
350 kΩ
AVIN
INDLED
INDC[1:0]
AVIN
High-Side LED Current Regulator
23µA
TS
WARNING
VREF = 1.05V
HOT
VREF = 0.345V
AGND
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PGND
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
FUNCTIONAL BLOCK DIAGRAM (TPS61306)
SW
AVIN
Undervoltage
Lockout
Bias Supply
OVP
COMPARATOR
VREF = 1.238V
Bandgap
REF
Backgate
Control
VOUT
Hot Die
Indicator
TON
Control
ERROR
AMPLIFIER
VREF
S
Q
R
Q
HC_SEL
VOUT
CONTROL LOGIC
P
EN
VOUT
2
COMPARATOR
Z
BAL
Z
VOLTAGE
REGULATION
CURRENT
REGULATION
VLED Sense
SENSE FB
Max tON Timer
SCL
I2C I/F
CURRENT
CONTROL
DAC
SDA
LED2
ON/OFF
P
SENSE FB
ENDCL
Slew-Rate
Controller
Oscillator
LED1
ON/OFF
CURRENT
CONTROL
DAC
P
FLASH_SYNC
SENSE FB
LED3
Tx-MASK
P
HC_SEL
Low-Side LED Current Regulator
Control
Logic
350 kΩ
AVIN
INDLED
INDC[1:0]
AVIN
High-Side LED Current Regulator
23µA
TS
WARNING
VREF = 1.05V
HOT
VREF = 0.305V
AGND PGND
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
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TPS61300, TPS61301, TPS61305
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www.ti.com
TIMER BLOCK DIAGRAM
(GPIO Bit)
Tx-MASK
350 kW
Port Direction
(DIR)
MODE 0
CURRENT REGULATOR MODE – DC LIGHT / FLASH ACTIVE
MODE 0 = LOW
MODE 1 = HIGH
MODE 1
GPIO/PG
Port Type
(PG)
0
FLASH_SYNC
1
1
(GPIO Bit)
350 kW
Safety Timer Trigger
(STT)
Edge Detect
PWROK
Start
Flash/Timer
(SFT)
MODE 0
MODE 1
DC Light
Safety Timer
(11.2s)
0: NORMAL OPERATION
1: DISABLE CURRENT SINK
Start
LED1-3 CURRENT CONTROL
CLOCK
16-bit Prescaler
Safety Timer
0: DC LIGHT CURRENT LEVEL
1: FLASH CURRENT LEVEL
tPULSE
Time-Out (TO)
Dimming
(DIM)
Timer
Value
(STIM)
Duty-Cycle Generator (0.8% … 8.6%)
LED1-3 ON/OFF CONTROL
0: LED1-3 OFF
1: DC LIGHT CURRENT LEVEL
18
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TPS61300, TPS61301, TPS61305
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
PARAMETER MEASUREMENT INFORMATION
TPS61300
L
2.2 mH
SW
SW
VOUT
CO
AVIN
2.5 V..5.5 V
CI
HC_SEL
BAL
ENDCL
LED1
FLASH_SYNC
LED2
10 mF
D1
D2
D1
D2
LED3
SCL
SDA
I2C I/F
INDLED
Privacy
Indicator
Tx-MASK
ENVM
GPIO/PG
AGND
PGND
PGND
TPS61305
L
SW
SW
VOUT
AVIN
2.5 V..5.5 V
CI
HC_SEL
BAL
SUPER-CAP
2.2 mH
CO
10 mF
NRESET
LED1
FLASH_SYNC
LED2
LED3
2
I C I/F
SCL
SDA
INDLED
Privacy
Indicator
Tx-MASK
TS
GPIO/PG
NTC
AGND
PGND
PGND
List of Components:
L = 2.2mH, Wuerth Elektronik WE-TPC Series
CI, CO = 10mF 6.3V X5R 0603 – TDK C1605X5R0J106MT
Storage Capacitor = TDK EDLC262020-500mF
NTC = 220kΩ, muRata NCP18WM224J03RB
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
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www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
LED Power Efficiency
vs. Input Voltage
DC Input Current
vs. Input Voltage
Figure 8, Figure 9
Figure 10
LED Current
vs. LED Pin Headroom Voltage
Figure 11, Figure 12,
Figure 13
LED Current
vs. LED Current Digital Code
Figure 14, Figure 15,
Figure 16, Figure 17
INDLED Current
vs. LED Pin Headroom Voltage
Voltage Mode Efficiency
vs. Output Current
Figure 19, Figure 20
DC Output Voltage
vs. Output Current
Figure 21, Figure 22
Maximum Output Current
vs. Input Voltage
DC Pre-Charge Current
vs. Differential Input-Output Voltage
Figure 18
Figure 23
Valley Current Limit
Figure 24, Figure 25
Figure 26, Figure 27
Balancing Current
vs. Balance Pin Voltage
Figure 28
Supply Current
vs. Input Voltage
Figure 29
Standby Current
vs. Ambient Temperature
Figure 30
Temperature Detection Threshold
Figure 31, Figure 32
Junction Temperature
vs. Port Voltage
Figure 33
Flash Sequence (Direct Drive Mode)
Figure 34
Figure 35, Figure 36,
Figure 37
Tx-Masking Operation
Low-Light Dimming Mode Operation
Figure 38
PWM Operation
Figure 39
PFM Operation
Figure 40
Down-Mode Operation (Voltage Mode)
Figure 41
Voltage Mode Load Transient Response
Figure 42
Start-up Into DC Light Operation
Figure 43
Start-up Into Voltage Mode Operation
Figure 44
Storage Capacitor Pre-Charge
Figure 45
Storage Capacitor Charge-Up
Figure 46, Figure 47,
Figure 48
DC Light Operation (Energy Storage Mode)
Figure 49
Figure 50, Figure 51,
Figure 52, Figure 53,
Figure 54
Flash Sequence (Energy Storage Mode)
Junction Temperature Monitoring
Figure 55
Shutdown (Energy Storage Mode)
Figure 56
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
100
100
TPS61300
TPS61300
80
70
60
ILED2 = 75 mA
ILED2 = 100 mA
ILED2 = 150 mA
50
ILED2 = 200 mA
40
ILED2 = 250 mA
30
20
ILIM = 1750 mA,
HC_SEL = Tx-MASK = Low
LED2 Channel Only
10
0
2.5
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
80
70
1750
40
30
20
ILIM = 1750 mA,
HC_SEL = Tx-MASK = Low
10
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
Figure 9. LED Power Efficiency
vs.
Input Voltage
ILED2 = 800 mA
ILED1 = ILED3 = 350 mA
ILED2 = 600 mA
TPS61300
800
ILED2 = 700 mA
700
LED2 Current - mA
1500
DC Input Current - mA
ILED1 = ILED3 = 100 mA
ILED2 = 200 mA
ILED1 = ILED3 = 250 mA
ILED2 = 450 mA
ILED1 = ILED3 = 250 mA
ILED2 = 550 mA
900
TPS61300
1250
1000
ILED1 = ILED3 = 250 mA
ILED2 = 550 mA
ILED1 = ILED3 = 250 mA
ILED2 = 450 mA
500
3.3
3.7
4.1
4.5
VI - Input Voltage - V
Figure 10. DC Input Current
vs.
Input Voltage
500
400
300
ILED2 = 550 mA
ILED2 = 450 mA
ILED2 = 350 mA
ILED2 = 300 mA
ILIM = 1750 mA,
HC_SEL = Low
100
ILIM = 1750 mA,
HC_SEL = Tx-MASK = Low
2.9
600
200
ILED1 = ILED3 = 250 mA
ILED2 = 275 mA
0
2.5
ILED1 = ILED3 = 75 mA
ILED2 = 150 mA
50
0
2.5
5.3
2000
250
ILED1 = ILED3 = 50 mA
ILED2 = 100 mA
60
Figure 8. LED Power Efficiency
vs.
Input Voltage
750
ILED1 = ILED3 = 350 mA
ILED2 = 600 mA
90
LED Power Efficiency (PLED/PIN) - %
LED Power Efficiency (PLED/PIN) - %
90
4.9
5.3
0
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED2 Pin Headroom Voltage - mV
Figure 11. LED2 Current
vs.
LED2 Pin Headroom Voltage (HC_SEL=0)
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TYPICAL CHARACTERISTICS (continued)
900
ILED1 = ILED3 = 400 mA
2400
TPS61300
2300
800
ILED2 = 2050 mA, TA = 85°C
ILED1 = ILED3 = 350 mA
LED2 Current - mA
LED1 + LED3 Current - mA
ILED1 = ILED3 = 300 mA
600
ILED1 = ILED3 = 250 mA
500
400
300
2100
2000
1800
1600
ILIM = 1750 mA,
HC_SEL = Low
100
1500
0
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED1, LED3 Pin Headroom Voltage - mV
ILED2 = 2050 mA, TA = -40°C
1900
1700
200
1400
ILED2 = 1775 mA,
TA = 85°C
ILED2 = 1775 mA,
TA = -40°C
ILED2 = 1775 mA,
TA = 25°C
VIN = 3.6 V, VOUT = 4.95 V
HC_SEL = High
300 400 500 600 700
800 900 1000 1100 1200 1300 1400
LED2 Pin Headroom Voltage - mV
Figure 12. LED1+LED3 Current
vs.
LED1+LED3 Pin Headroom Voltage (HC_SEL=0)
Figure 13. LED2 Current
vs.
LED2 Pin Headroom Voltage (HC_SEL=1)
300
275
ILED2 = 2050 mA, TA = 25°C
2200
700
TPS61305
125
ILIM = 1750 mA,
HC_SEL = Low
TPS61300
ILIM = 1750 mA,
HC_SEL = Low
VIN = 2.5 V
LED2 Current - mA
225
200
VIN = 4.5 V
175
150
125
VIN = 3.6 V
100
75
LED1, LED3 Current - mA
250
VIN = 3.6 V
100
VIN = 4.5 V
75
VIN = 2.5 V
50
50
TPS61300
25
0
0 25 50 75 100 125 150 175 200 225 250 275 300
LED2 Current Digital Code - mA
Figure 14. LED2 Current
vs.
LED2 Current Digital Code (HC_SEL=0)
22
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25
25
50
75
100
LED1, LED3 Current Digital Code - mA
125
Figure 15. LED1, LED3 Current
vs.
LED1, LED3 Current Digital Code (HC_SEL=0)
Copyright © 2009–2010, Texas Instruments Incorporated
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
450
900
850
800
ILIM = 1750 mA,
HC_SEL = Low
VIN = 2.5 V
TPS61300
425
VIN = 2.5 V
400
LED1, LED3 Current - mA
750
700
LED2 Current - mA
TPS61300
ILIM = 1750 mA,
HC_SEL = Low
650
VIN = 4.5 V
VIN = 3.6 V
600
550
500
450
400
350
375
350
VIN = 3.6 V
VIN = 4.5 V
325
300
275
250
300
225
250
200
200
300
400
500
600
700
800
LED2 Current Digital Code - mA
200
200 225 250 275 300 325 350 375 400 425 450
LED1, LED3 Current Digital Code - mA
900
Figure 16. LED2 Current
vs.
LED2 Current Digital Code (HC_SEL=0)
9
8
TPS61300
TA = 25°C
INDLED = 0011
Figure 17. LED1, LED3 Current
vs.
LED1, LED3 Current Digital Code (HC_SEL=0)
100
TA = -40°C
VIN = 4.2 V
90
TA = 85°C
80
VIN = 2.5 V
6
TA = 85°C
70
TA = 25°C
INDLED = 0010
5
4
3
TA = 25°C
INDLED = 0001
TA = 85°C
TA = -40°C
0
0.5
0.7
VIN = 3 V
PFM/PWM Operation
60
50
40
Forced PWM Operation
TPS61300
VOUT = 4.95 V
ILIM = 1750 mA
Voltage Mode Regulation
20
VIN = 3.6 V
VIN = 3.6 V
30
2
1
Efficiency - %
INDLED Current - mA
7
TA = -40°C
10
0.9
1.1
1.3
1.5
1.7
INDLED Pin Headroom Voltage - V
Figure 18. INDLED Current
vs.
INDLED Pin Headroom Voltage
1.9
0
1
10
100
1000
IO - Output Current - mA
10000
Figure 19. Efficiency
vs.
Output Current
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TYPICAL CHARACTERISTICS (continued)
100
5.2
VIN = 3.6 V
90
5.15
VO - Output Voltage (DC) - V
VIN = 3 V
VIN = 2.5 V
80
Forced PWM Operation
Efficiency - %
70
VIN = 4.2 V
60
50
PFM/PWM Operation
40
30
TPS61300
VOUT = 3.825 V
ILIM = 1750 mA
Voltage Mode Regulation
20
10
10
100
1000
IO - Output Current - mA
PFM/PWM Operation
5.1
5.05
5
VIN = 4.2 V
4.95
Forced PWM Operation
4.9
VIN = 3.6 V
VIN = 2.5 V
4.8
1
10000
10
Figure 20. Efficiency
vs.
Output Current
1500
1400
IOUT = 0 mA
3.94
3.902
IOUT = 100 mA
3.863
IOUT = 1000 mA
3.787
VOUT = 3.825 V
ILIM = 1750 mA
3.749
3.71
2.5
2.9
3.3
3.7
4.1
4.5
4.9
IO - Output Current - mA
Figure 22. DC Output Voltage
vs.
Load Current
24
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10000
TPS61300
Voltage Mode Regulation
1300
IO - Output Current (max) - mA
VO - Output Voltage (DC) - V
TPS61300
Voltage Mode Regulation
3.825
100
1000
IO - Output Current - mA
Figure 21. DC Output Voltage
vs.
Load Current
4.016
3.978
VOUT = 4.95 V,
ILIM = 1750 mA
4.85
0
1
TPS61300
Voltage Mode Regulation
1200
1100
VOUT = 4.95 V,
ILIM = 1250 mA
VOUT = 5.7 V,
ILIM = 1250 mA
1000
900
800
700
VOUT = 5.7 V,
ILIM = 500 mA
600
500
400
300
200
VOUT = 4.95 V,
ILIM = 250 mA
100
5.3
0
2.5
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
TA = 25°C
4.9
5.3
Figure 23. Maximum Output Current
vs.
Input Voltage
Copyright © 2009–2010, Texas Instruments Incorporated
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
400
400
TPS61305
TPS61305
350
VIN = 3.6 V, TA = -40°C
VIN = 3.6 V, TA = 25°C
300
VIN = 4.2 V, TA = 25°C
250
200
VIN = 2.5 V, TA = 25°C
150
100
DC Pre-Charge Current - mA
300
250
200
VIN = 3.6 V, TA = 85°C
150
VIN = 3.6 V, TA = 25°C
100
50
50
HC_SEL = 1
HC_SEL = 1
0
0
0
4.2
ILIM - Valley Current Limit - mA
Figure 26. Valley Current Limit (HC_SEL=1)
TA = -40°C
24
21
18
15
12
9
720
750
660
690
Sample Size = 70
540
6
3
0
570
375
345
360
315
330
285
300
270
240
255
210
225
Sample Size = 70
TA = 85°C
420
TA = -40°C
39
36
33
30
27
TA = 25°C
450
480
510
TA = 85°C
Sample Percentage - %
TA = 25°C
TPS61305
VIN = 3.6 V
HC_SEL = 1,
Tx-MASK = 1,
ILIM bit = 1
600
48
45
42
360
390
HC_SEL = 1,
Tx-MASK = 1,
ILIM bit = 0
4.2
Figure 25. DC Pre-Charge Current
vs.
Differential Input-Output Voltage (HC_SEL=1)
TPS61305
VIN = 3.6 V
165
180
195
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
150
Sample Percentage - %
Figure 24. DC Pre-Charge Current
vs.
Differential Input-Output Voltage (HC_SEL=1)
0.6
1.2
1.8
2.4
3
3.6
Differential Input - Output Voltage - V
300
0.6
1.2
1.8
2.4
3
3.6
Differential Input - Output Voltage - V
330
0
630
DC Pre-Charge Current - mA
350
ILIM - Valley Current Limit - mA
Figure 27. Valley Current Limit (HC_SEL=1)
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TYPICAL CHARACTERISTICS (continued)
25
1500
TPS61305
VOUT = 4.95 V,
HC_SEL = 1
1300
TA = 85°C
15
TA = 25°C
10
TA = -40°C
5
0
-5
-10
1200
VOUT = 4.95 V, TA = 85°C
1100
VOUT = 5.7 V, TA = 25°C
1000
900
800
VOUT = 4.95 V,
TA = -40°C V
OUT = 4.95 V,
TA = 25°C
700
-15
600
-20
2.30
2.35
2.40 2.45 2.50 2.55 2.60 2.65
VBAL - Balance Pin Voltage - V
500
2.5
2.70
Figure 28. Balancing Current
vs.
Balance Pin Voltage
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
26
TPS61305
24
2.5
VIN = 3.6 V
TPS61305
22
VIN = 4.8 V
20
2
VIN = 3.6 V
1.5
VIN = 2.5 V
1
Sample Percentage - %
ISTBY - Standby Current - mA
2.9
VOUT = 3.825 V,
TA = 25°C
Figure 29. Supply Current
vs.
Input Voltage
3
18
16
14
12
10
Sample Size = 76
8
6
0.5
4
HC_SEL = 1
Storage capacitor balanced (IOUT = 0 mA)
0
-35 -25 -15 -5 5 15 25 35 45 55 65 75 85
TA - Ambient Temperature - °C
Figure 30. Standby Current
vs.
Ambient Temperature (HC_SEL=1)
26
TPS61305
IOUT = 0 mA
ENPSM bit = ENVM bit = 1
1400
ICC - Supply Current - mA
IBAL - Balance Pin Current - mA
20
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2
0
50
51 52 53 54 55 56 57 58 59
Temperature Detection (55°C Threshold)
60
Figure 31. Temperature Detection Threshold
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
200
28
TPS61300
175 IPORT = -100 mA
Sample Percentage - %
22
20
18
16
14
12
Sample Size = 76
10
8
6
TJ - Junction Temperature - °C
24
150
Tx-MASK Input
ENDCL Input
125
ENVM Input
100
75
50
Port
Input Buffer
25
0
VPORT
26
TPS61305
VIN = 3.6 V
4
-25
2
0
64 65 66 67 68 69 70 71 72 73 74 75
Temperature Detection (70°C Threshold)
Figure 32. Temperature Detection Threshold
FLASH_SYNC
(2V/div)
ILED2
(500mA/div)
TPS61300, HC_SEL = 0
LED2 Channel Only
DCLC2[2:0] = 000
FC2[2:0] = 111
100 mA
-50
-0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1
Port Voltage - V
Figure 33. Junction Temperature
vs.
Port Voltage
FLASH_SYNC
(2V/div)
TPS61300, HC_SEL = 0
Tx-MASK
(2V/div)
DCLC13[1:0] = 00
FC13[1:0] = 01
ILED1 + ILED3
(200mA/div)
VOUT
(1V/div - 3.6V Offset)
LED2 Pin Headroom Voltage
(1V/div)
VIN = 3.6V, VOUT = 4.95V, ILIM = 1750mA
t - Time = 1 ms/div
Figure 34. FLASH SEQUENCE (HC_SEL=0)
ILED2
(200mA/div)
DCLC2[2:0] = 000
FC2[2:0] = 100
VIN = 3.6V, VOUT = 4.95V, ILIM = 1750mA
t - Time = 500 µs/div
Figure 35. Tx-MASKING OPERATION (HC_SEL=0)
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TYPICAL CHARACTERISTICS (continued)
Tx-MASK
(2V/div)
TPS61300, HC_SEL = 0
ILED2
(200mA/div)
Tx-MASK
(2V/div)
TPS61300, HC_SEL = 0
ILED2
(200mA/div)
IL
(200mA/div)
IL
(500mA/div)
LED2 Channel Only
DCLC2[2:0] = 110
FC2[2:0] = 111
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
t - Time = 5 µs/div
Figure 36. Tx-MASKING OPERATION (HC_SEL=0)
TPS61300, HC_SEL = 0
ILED2
(20 mA/div)
LED2 Channel Only
DCLC2[2:0] = 001
FC2[2:0] = 111
t - Time = 100 µs/div
Figure 37. Tx-MASKING OPERATION (HC_SEL=0)
TPS61300, HC_SEL = 0
VOUT
(20mV/div - 4.95V Offset)
Frequency = 121 Hz
Duty Cycle = 6.3 %
IL
(200mA/div)
VOUT
(500 mV/div - 3.6 V Offset)
VIN = 3.6 V, IDCLIGHT2 = 75 mA
LED2 Channel Only
INDC[3:0] = 1110
t - Time = 2 ms/div
Figure 38. LOW-LIGHT DIMMING MODE OPERATION
28
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SW
(2V/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 300mA, ILIM = 1750mA
Forced PWM Operation
ENPSM bit = 0
t - Time = 125 ns/div
Figure 39. PWM OPERATION
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
TPS61300
HC_SEL = 0
TPS61300, HC_SEL = 0
VOUT
(100mV/div - 4.95V Offset)
VOUT
(100mV/div - 3.825V Offset)
IL
(200mA/div)
IL
(200mA/div)
SW
(5V/div)
SW
(5V/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 50mA, ILIM = 1750mA
PFM/PWM Operation
ENPSM bit = 1
VIN = 4.2V, VOUT = 3.825V
IOUT = 50mA, ILIM = 1750mA
t - Time = 2 ms/div
t - Time = 2 ms/div
Figure 40. PFM OPERATION
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
TPS61300, HC_SEL = 0
PFM/PWM Operation
ENPSM bit = 1
Figure 41. DOWN-MODE OPERATION (VOLTAGE MODE)
ENDCL
(2V/div)
TPS61300, HC_SEL = 0
ILED2
(50mA/div)
VOUT
(500mV/div - 4.95V Offset)
VOUT
(2V/div)
IL
(500mA/div)
IL
(200mA/div)
50mA to 500mA Load Step
IOUT
(500mA/div)
PFM/PWM Operation
ENPSM bit = 1
t - Time = 50 ms/div
Figure 42. VOLTAGE MODE LOAD TRANSIENT
RESPONSE
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
LED2 Channel Only
DCLC2[2:0] = 011
t - Time = 200 µs/div
Figure 43. START-UP INTO DC LIGHT OPERATION
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TYPICAL CHARACTERISTICS (continued)
ENVM
(2V/div)
TPS61300, HC_SEL = 0
HC_SEL (2V/div)
TPS61305 (NRESET = 1)
PG (2V/div)
VOUT
(2V/div)
VOUT
(1V/div)
IL
(200mA/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 0mA, ILIM = 1750mA
IL
(100mA/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 0mA
t - Time = 100 µs/div
t - Time = 1 s/div
Figure 44. START-UP INTO VOLTAGE MODE OPERATION
TPS61305
(NRESET = 1)
HC_SEL, ENVM (2V/div)
ENPSM bit = 1
PG (2V/div)
Figure 45. STORAGE CAPACITOR PRE-CHARGE
(HC_SEL=1)
HC_SEL, ENVM (2V/div)
PG (2V/div)
VOUT
(2V/div)
TPS61305
(NRESET = 1)
VOUT
(1V/div)
IL
(500mA/div)
IL
(200mA/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 0mA
ENPSM bit = 1, ILIM bit = 0
Tx-MASK = 1
VIN = 3.6V, VOUT = 4.95V
IOUT = 0mA
t - Time = 2 s/div
Figure 46. STORAGE CAPACITOR CHARGE-UP
(HC_SEL=1)
30
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ENPSM bit = 1, ILIM bit = 0
Tx-MASK = 0
t - Time = 1 s/div
Figure 47. STORAGE CAPACITOR CHARGE-UP
(HC_SEL=1)
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
TPS61305
(NRESET = 1)
PG (2 V/div)
VOUT
(1 V/div)
ENVM bit = 1
TPS61305
(NRESET = 1)
PG (2V/div)
VOUT
(1V/div)
ILED1 + ILED3
(50mA/div)
DCLC13[1:0] = 01
DCLC2[2:0] = 010
DC Light
Turn-On Command
ILED2
(50mA/div)
IL
(200 mA/div)
VIN = 3.6 V, VOUT = 4.95 V, ENPSM bit = 1, ILIM bit = 0,
IOUT = 0 mA
Tx-MASK = 1, HC_SEL = 1
t - Time = 1 s/div
VIN = 3.6V, VOUT = 4.95V
ENPSM bit = 1, ILIM bit = 0
All LED Channels Active Tx-MASK = 1
t - Time = 500 ms/div
Figure 48. STORAGE CAPACITOR CHARGE-UP
(HC_SEL=1)
TPS61305
(NRESET = 1)
FLASH_SYNC
(2V/div)
DC Light
Turn-Off Command
Figure 49. DC LIGHT OPERATION (HC_SEL=1)
TPS61305
(NRESET = 1)
FLASH_SYNC
(2V/div)
PG (2V/div)
VOUT
(200mV/div - 4.95V Offset)
VOUT
(500mV/div - 4.95V Offset)
IL
(200mA/div)
DCLC2[2:0] = 000
FC2[2:0] = 111
ENPSM bit = 1,
ILIM bit = 0,
Tx-MASK = 1
ILED2
(1A/div)
VIN = 3.6V, VOUT = 4.95V, LED2 Channel Only
t - Time = 50 ms/div
Figure 50. FLASH SEQUENCE (HC_SEL=1)
ILED2
(1A/div)
DCLC2[2:0] = 000
FC2[2:0] = 111
ENPSM bit = 1,
ILIM bit = 0,
Tx-MASK = 1
VIN = 3.6V, VOUT = 4.95V, LED2 Channel Only
t - Time = 100 ms/div
Figure 51. FLASH SEQUENCE (HC_SEL=1)
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TYPICAL CHARACTERISTICS (continued)
TPS61305
(NRESET = 1)
FLASH SYNC
(2 V/div)
TPS61305
(NRESET = 1)
PG
(2 V/div)
LED VF Calibrated Circuit,
ca. 500 mV LED Pin Headroom Pin (e/o Strobe)
VOUT
(200 mV/div
- 4.7 V Offset)
VOUT
(500 mV/div - 4.95 V Offset)
IL
(500 mA/div)
ILED1 + ILED3
(1 A/div)
Tx-MASK Input = 1
ENPSM bit = 1,
Tx-MASK bit = 0,
ILIM bit = 1
Tx-MASK Input = 1
ILED2
(1 A/div)
ILED2
(1 A/div)
ENPSM bit = 1,
Tx-MASK bit = 0,
ILIM bit = 0
DCLC2 [2:0] = 000
FC2 [2:0] = 111
VIN = 3.6 V, VOUT = 4.95 V, LED2 Channel Only
DCLC2 [2:0] = 000
FC2 [2:0] = 111
VIN = 3.6 V, VOUT = 4.7 V, All LED Channels Active
t - Time = 20 ms/div
Figure 52. FLASH SEQUENCE (HC_SEL=1)
TPS61305
(NRESET = 1)
PG
(2 V/div)
LED VF Calibrated Circuit,
ca. 500 mV LED Pin Headroom Pin (e/o Strobe)
VOUT
(500 mV/div - 4.95 V Offset)
DCLC13 [1:0] = 00
FC13 [1:0] = 11
t - Time = 10 ms/div
Figure 53. FLASH SEQUENCE (HC_SEL=1)
TPS61305
(NRESET = 1)
ENPSM bit = 1,
Tx-MASK bit = 0,
ILIM bit = 1
Tx-MASK
(10 mV/div - -0.55 V Offset)
TJ = 55°C
TJ = 25°C
ILED1 + ILED3
(1 A/div)
Tx-MASK Input = 1
ENPSM bit = 1,
Tx-MASK bit = 0,
ILIM bit = 1
ILED2
(1 A/div)
DCLC13 [1:0] = 00 DCLC2 [2:0] = 000
FC13 [1:0] = 11
FC2 [2:0] = 111
VIN = 3.6 V, VOUT = 4.95 V, All LED Channels Active
t - Time = 50 ms/div
Figure 54. FLASH SEQUENCE (HC_SEL=1)
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LED VF Calibrated Circuit,
ca. 500 mV LED Pin Headroom Pin (e/o Strobe)
DCLC13 [1:0] = 01
FC13 [1:0] = 11
DCLC2 [2:0] = 011
FC2 [2:0] = 111
ILED1 + ILED3
(1 A/div)
ILED2
(1 A/div)
DC Light = 2 s
Flash Strobe = 35 ms
VIN = 3.6 V, VOUT = 4.7 V, All LED Channels Active
t - Time = 500 ms/div
Figure 55. JUNCTION TEMPERATURE MONITORING
(HC_SEL=1)
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TYPICAL CHARACTERISTICS (continued)
HC_SEL (2V/div)
TPS61305 (NRESET = 1)
PG (2V/div)
VOUT
(500mV/div)
VIN = 3.6V, IOUT = 0mA
t - Time = 100 s/div
Figure 56. SHUTDOWN (HC_SEL=1)
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DETAILED DESCRIPTION
OPERATION
The TPS6130x family employs a 2MHz fixed on-time, PWM current-mode converter to generate the output
voltage required to drive up to three high power LEDs in parallel. The device integrates a power stage based on
an NMOS switch and a synchronous PMOS rectifier. The device also implements a set of linear low-side current
regulators to control the LED current when the battery voltage is higher than the diode forward voltage.
A special circuit is applied to disconnect the load from the battery during shutdown of the converter. In
conventional synchronous rectifier circuits, the back-gate diode of the high-side PMOS is forward biased in
shutdown and allows current flowing from the battery to the output. This device however uses a special circuit
which takes the cathode of the back-gate diode of the high-side PMOS and disconnects it from the source when
the regulator is in shutdown (HC_SEL = L).
The TPS6130x device cannot only operate as a regulated current source but also as a standard voltage boost
regulator featuring power-save mode for improved efficiency at light load. The voltage mode operation can be
activated either by a software command or by means of a hardware signal (ENVM). This additional operating
mode can be useful to properly synchronize the converter when supplying other high power consuming devices
in the system (e.g. hands-free audio power amplifier…) or any other component requiring a supply voltage higher
than the battery voltage.
The TPS6130x device also supports storage capacitor on its output (so called energy storage mode). In this
operating mode (HC_SEL = H), the inductive power stage is used to charge-up the super-capacitor to a user
selectable value. Once the charge-up is complete, the LEDs can be fired up to 1025mA (LED1 and LED3) and
2050mA (LED2) without causing a battery overload.
In general, a boost converter only regulates output voltages which are higher than the input voltage. This device
operates differently. For example, in the voltage mode operation the device is capable to regulate 4.2V at the
output from a battery voltage pulsing as high 5.5V. To control these applications properly, a down conversion
mode is implemented.
If the input voltage reaches or exceeds the output voltage, the converter changes to a down conversion mode. In
this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the voltage drop across the
PMOS as high as needed to regulate the output voltage. This means the power losses in the converter increase.
This has to be taken into account for thermal consideration.
In direct drive mode (HC_SEL = L), the power stage is capable of supplying a maximum total current of roughly
1300 to 1500mA. The TPS61300 provides three constant current inputs, capable of sinking up to 400mA (LED1
and LED3) and 800mA (LED2) in flashlight mode.
The TPS6130x integrates an I2C compatible interface allowing transfers up to 3.4Mbits/s. This communication
interface can be used to set the operating mode (shutdown, constant output current mode vs. constant output
voltage mode), to control the brightness of the external LED (DC light and flashlight modes), to adjust the output
voltage (between 3.825V and 5.7V in 125mV steps) or to program the safety timer for instance. For more details,
refer to the I2C register description section.
In the TPS6130x device, the DC light and flash can be controlled either by the I2C interface or by the means of
hardware control signals (ENDCL and FLASH_SYNC). To simplify flashlight synchronization with the camera
module, the device offers a FLASH_SYNC strobe input pin to turn, with zero latency, the LED current from DC
light to flashlight.
The maximum duration of the flashlight pulse can be limited by means of an internal user programmable safety
timer (STIM). To avoid the LEDs to be kept accidentally on in DC light mode by software control, the device
implements a 11.2s watchdog timer.
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DOWN MODE IN VOLTAGE REGULATION MODE
In general, a boost converter only regulates output voltages which are higher than the input voltage. The featured
devices come with the ability to regulate 4.2 V at the output with an input voltage being has high as 5.5V. To
control these applications properly, a down conversion mode is implemented.
In voltage regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to
the down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets
the voltage drop across the PMOS as high as needed to regulate the output voltage. This means the power
losses in the converter increase. This has to be taken into account for thermal consideration. The down
conversion mode is automatically turned-off as soon as the input voltage falls about 200mV below the output
voltage.
For proper operation in down conversion mode the output voltage should not be programmed higher than ca.
5.3V. Care should be taken not to violate the absolute maximum ratings at the SW pins.
The TPS6130x device uses a control architecture that allows to “recycle” excessive energy that might be stored
in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of
transferring energy from its output back into the input source.
In high-current mode (HC_SEL = 1), this feature becomes useful to dynamically adjust the output voltage (VOUT)
depending on the operating conditions (e.g. +4.95V constant output voltage to support audio applications or
variable storage capacitor pre-charge voltage, refer to “storage capacitor pre-charge voltage calibration” section).
Notice that this reverse operating mode can only perform within an output voltage range higher than the input
supply. For example, if the storage capacitor is initially pre-charged to 4.95V, the input voltage is around 4.1V
and the target output voltage is set to 3.825V, the converter will only be able to lower the output node down to
the input level.
LED HIGH-CURRENT REGULATORS, UNUSED INPUTS
The TPS6130x device utilizes LED forward voltage sensing circuitry on LED1-3 pins to optimize the power stage
boost ratio for maximum efficiency. Due to the nature of the sensing circuitry, it is not recommended to leave any
of the LED1-3 pins unused if the operation has been selected via ENLED[3:1] bits. Leaving LED1-3 pins
unconnected, whilst the respective ENLEDx bits have been set, will force the control loop into high gain and
eventually trip the output over-voltage protection.
The LED1-3 inputs may be connected together to drive one or two LEDs at higher currents. Connecting the
current sink inputs in parallel does not affect the internal operation of the TPS6130x. For best operation, it is
recommended to disabled the LED inputs that are not used (refer to ENLED[3:1] bits description).
To achieve smooth LED current waveforms, the TPS61300 device actively controls the LED current
ramp-up/down sequence.
Table 1. LED Current Ramp-Up/Down Control vs Operating Mode
LED CURRENT RAMP-UP
LED CURRENT RAMP-DOWN
DIRECT DRIVE MODE (HC_SEL = 0)
HIGH-CURRENT MODE (HC_SEL = 1)
ISTEP = 25 mA
ISTEP = 56.25 mA
tRISE = 12 ms
tRISE = 0.5 ms
Slew-rate ≉ 2.08 mA/ms
Slew-rate ≉ 112.5 mA/ms
ISTEP = 25 mA
ISTEP = 56.25 mA
tFALL = 0.5 ms
tFALL = 0.5 ms
Slew-rate ≉ 50 mA/ms
Slew-rate ≉ 112.5 mA/ms
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LED
CURRENT
ISTEP
Time
t RISE
t FALL
Figure 57. LED Current Slew-Rate Control
In high-current mode (HC_SEL = 1), the LED current settings are defined as a fixed ratio (x2.25) versus the
direct drive mode values (HC_SEL = L).
POWER-SAVE MODE OPERATION, EFFICIENCY
The TPS6130x device integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the
set threshold voltage.
Output
Voltage
PFM mode at light load
PFM ripple about 0.015 x VOUT
1.013 x VOUT NOM.
VOUT NOM.
PWM mode at heavy load
Figure 58. Operation in PFM Mode and Transfer to PWM Mode
The power save mode can be enabled and disabled via the ENPSM bit. In down conversion mode, power save
mode is always active and the device cannot be forced into fixed frequency operation at light loads.
The LED sense voltage has a direct effect on the converter’s efficiency. Because the voltage across the low-side
current regulator does not contribute to the output power (LED brightness), the lower the sense voltage the
higher the efficiency will be.
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. The
integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on
the LED forward voltage and current requirements. The low-side current regulators will be dropping the voltage
difference between the input voltage and the LEDs forward voltage (VF(LED) < VIN). When running in boost mode
(VF(LED) > VIN), the voltage present at the LED1-3 pins of the low-side current regulators will be typically 400mV
leading to high power conversion efficiency. Depending on the input voltage and the LEDs forward voltage
characteristic the converter will show efficiency in the range of about 75% to 90%.
In high-current mode (HC_SEL = H), the device is only supplying a limited amount of energy directly from the
battery (i.e. DC light, contribution to flash current or voltage regulation mode). During a flash strobe, the bulk of
the energy supplied to the LEDs is provided by the reservoir capacitor. The low-side current regulators will be
typically operating with 400mV headroom voltage. This means the power losses in the device increase and
special care should be taken for thermal considerations.
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MODE OF OPERATION: DC LIGHT AND FLASHLIGHT
Operation is understood best by referring to the timer block diagram. Depending on the settings of
MODE_CTRL[1:0] bits the device can enter 4 different operating modes. The below section details the
converter’s operation for ENVM = 0.
• MODE_CTRL[1:0] = 00: The device is in shutdown mode.
• MODE_CTRL[1:0] = 01: The device is regulating the LED current to the DC light current level (DCLC bits)
regardless of the FLASH_SYNC input and START_FLASH/TIMER (SFT) bit. To avoid device shutdown by
DC light safety timeout, MODE_CTRL[1:0] needs to be refreshed within less than 11.2s.
• MODE_CTRL[1:0] = 11: The device is regulating a constant output voltage according to OV[3:0] bits settings.
The low-side LED1-3 current sinks are disabled and the LEDs are disconnected from the output. In this
operating mode, the safety timer is disabled.
• MODE_CTRL[1:0] = 10: The flashlight pulse can be either trigger by a hardware signal (FLASH_SYNC) or by
a software bit (SFT). LED strobe pulse follows FLASH_SYNC.
FLASH STROBE IS LEVEL SENSITIVE (STT = 0): LED STROBE FOLLOWS FLASH_SYNC INPUT
FLASH_SYNC and (SFT) = 0: LED operation is set to the DC light current level. To avoid device shutdown by
DC light safety timeout, MODE_CTRL[1:0] needs to be refreshed within less than 11.2s.
FLASH_SYNC or (SFT) = 1: The LED is driven at the flashlight current level and the safety timer is running. The
maximum duration of the flashlight pulse is defined in the STIM[2:0] register.
FLASH
DC LIGHT
LED Current
LED Current
I2C Bus
FREE
FREE
FREE
LED Turn-Off Command
MODE_CTRL[1:0] = “00"
LED Turn-On Command
MODE_CTRL [1:0] = “01"
FLASH_SYNC
I2C Bus
FREE
DC/DC Turn-On Command
MODE_CTRL [1:0] = “10"
Figure 59. DC Light Operation
FREE
DC/DC Turn-Off Command
MODE_CTRL [1:0] = “00"
Figure 60. Synchronized Flashlight Strobe
FLASH_SYNC or (SFT)
FLASH _SYNC or (SFT )
STIM
TIMER
STIM
TIMER
FLASH
FLASH
TIME-OUT RESET (SF)
LED CONTROL
LED CONTROL
TIME-OUT RESET (SF)
DC LIGHT
DC LIGHT
Figure 61. Level Sensitive Safety Timer
(Timeout)
Figure 62. Level Sensitive Safety Timer
(Normal Operation + Timeout)
The safety timer is started by:
• a rising edge of FLASH_SYNC signal.
• a rising edge of START_FLASH/TIMER (SFT) bit.
The safety timer is stopped by:
• a low level of FLASH_SYNC signal or START_FLASH/TIMER (SFT) bit.
• a timeout signal (TO).
START-FLASH/TIMER (SFT) bit is being reset by the timeout (TO) signal.
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FLASH STROBE IS LEADING EDGE SENSITIVE (STT = 1): ONE-SHOT LED STROBE
When FLASH_SYNC and START_FLASH/TIMER (SFT) are both low the LED operation is set to the DC Light
current level. To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] needs to be refreshed
within less than 11.2s.
The duration of the flashlight pulse is defined in the STIM register. The flashlight strobe is started by:
• a rising edge of START_FLASH/TIMER (SFT) bit.
• a rising edge of FLASH_SYNC signal.
Once running, the timer ignores all kind of triggering signal and only stops after a timeout (TO).
START-FLASH/TIMER (SFT) bit is being reset by the timeout (TO) signal.
FLASH _SYNC or (SFT )
FLASH_ SYNC or (SFT )
STIM
TIMER
FLASH
LED CONTROL
STIM
TIMER
FLASH
RESET (SFT)
LED CONTROL
DC LIGHT
DC LIGHT
Figure 63. Edge Sensitive Timer
(Single Trigger Event)
RESET (SFT)
Figure 64. Edge Sensitive Timer
(Single Trigger Event)
FLASH _SYNC or (SFT )
STIM
TIMER
FLASH
RESET (SFT)
LED CONTROL
DC LIGHT
Figure 65. Edge Sensitive Timer
(Multiple Trigger Events)
SAFETY TIMER ACCURACY
The LED strobe timer uses the internal oscillator as reference clock. As a matter of fact, the timer execution
speed (refer to STIM[2:0]) scales according to the reference clock accuracy.
OSCILLATOR FREQUENCY
Minimum
Typical
Maximum
(1)
(2)
38
SAFETY TIMER DURATION
Maximum = Typical × (1 + fACC)
Typical
(1)
(2)
Minimum = Typical x (1 - fACC) (1)
Refer to REGISTER3, STIM[2:0] definition.
Refer to the Electrical Characteristics table.
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CURRENT LIMIT OPERATION
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off
time through sensing of the voltage drop across the synchronous rectifier. The detection threshold is user
selectable via the ILIM bit. The ILIM bit can only be set before the device enters operation (i.e., initial shutdown
state).
Figure 66 illustrates the inductor and rectifier current waveforms during current limit operation. The output
current, IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such
that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease
to this threshold before the next on-time begins (so called frequency fold-back mechanism).
Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a
constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit operation,
can be defined as:
V
V
- VIN
1
D
IOUT(CL) = (1 - D) ´ (IVALLEY + DIL ) with DIL = IN ´
and D » OUT
2
L
f
VOUT
(1)
The TPS6130x device also provides a negative current limit (c.a. 300mA) to prevent an excessive reverse
inductor current when the power stage sinks current from the output (i.e., storage capacitor) in the forced
continuous conduction mode.
IPEAK
DIL
Current Limit
Threshold
Rectifier
Current
IVALLEY = ILIM
IOUT (CL)
DIL
IOUT(DC) (= ILED)
Increased
Load Current
IIN (DC)
f
Inductor
Current
IIN (DC)
DIL
ΔI L =
V IN D
×
L f
Figure 66. Inductor/Rectifier Currents in Current Limit Operation
To minimize the requirements on the energy storage capacitor present at the output of the driver (HC_SEL = 1),
the TPS6130x device can contribute to a larger extent in supporting directly the high-current LED flash strobe. In
fact, the device can dynamically adjust it’s current limit setting according to the Tx-MASK input.
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Table 2. Inductor Current Limit Operation vs HC_SEL/Tx-MASK Inputs
CURRENT LIMIT SETTING
ILIM BIT
HC_SEL INPUT
Tx-MASK INPUT
1250 mA
Low
Low
Low
1750 mA
High
Low
Low
1250 mA
Low
High
Low
1750 mA
High
High
Low
1250 mA
Low
Low
High
1750 mA
High
Low
High
250 mA
Low
High
High
500 mA
High
High
High
LED FAILURE MODES AND OVER-VOLTAGE PROTECTION
If a high-power LED fails as a short circuit, the low-side current regulator will limit the maximum output current
and the HIGH-POWER LED FAILURE (HPLF) flag will be set.
If a high-power LED fails as an open circuit, the control loop will initially attempt to regulate off of its low-side
current regulator feedback signal. This will drive VOUT higher. As the open circuited LED will never accept its
programmed current, VOUT must be voltage-limited by means of a secondary control loop.
The TPS6130x device limits VOUT according to the over-voltage protection settings (refer to OVP specification). In
this failure mode, VOUT is either limited to 4.65V (typ.) or 6.0V (typ.) and the HIGH-POWER LED FAILURE
(HPLF) flag is set.
OVP THRESHOLD
OPERATING CONDITIONS
4.65 V typ
HC_SEL = L and 0000 ≤ OV[3:0] ≤ 0100
6.0 V typ
HC_SEL = H or 0101 ≤ OV[3:0] ≤ 1111
Refer to the section “LED High-Current Regulators, Unused inputs” for additional information.
OVP Threshold
4.65 V ±150 mV
1.02 VOUT (NOM)
VOUT (NOM) = 4.2 V
0.98 VOUT (NOM)
Dynamic Load Transient
LED Disconnect
Figure 67. Over-Voltage Protection Operation (4.65V typ)
HARDWARE VOLTAGE MODE SELECTION
The TPS6130x device integrates a logic input (ENVM) and/or a software control bit (ENVM bit) that can be used
to force the converter to run in voltage mode regulation. Pulling the ENVM pin high forces the device into voltage
regulation mode (VOUT is preset to a fixed value, 4.95V). This additional operating mode can be useful to supply
other high power consuming devices in the system (e.g., hands-free audio power amplifier…) or any other
component requiring a regulated supply voltage higher or lower than the battery voltage.
Table 3 gives an overview of the different mode of operation.
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Table 3. Operating Mode Description
INTERNAL REGISTER
SETTINGS
MODE_CTRL[1:0]
ENVM BIT
00
0
The converter is in shutdown mode and the load is disconnected from the battery.
01
0
LEDs are turned-on for DC light operation (i.e. movie-light). The converter is operating in
the current regulation mode (CM). The output voltage is controlled by the forward voltage
characteristic of the LED. The energy is being directly transferred from the battery to the output.
10
0
The converter is operating in the current regulation mode (CM). The output voltage is controlled
by the forward voltage characteristic of the LED. LEDs are ready for flashlight operation and
DC light operation is supported directly from the battery.
OPERATING MODES
In high-current mode (HC_SEL = H), the energy is supplied by the output reservoir
capacitor and the inductive power stage is turned-off for the flash strobe period of time.
11
0
LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The
output voltage is set via the register OV[3:0].
00
1
LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The
output voltage is set via the register OV[3:0].
01
1
The converter is operating in the voltage regulation mode (VM) and it’s output voltage is
set via the register OV[3:0]. The LEDs are turned-on for DC light operation and the
energy is being directly transferred from the battery to the output. The LED currents are
regulated by the means of the low-side current sinks.
10
1
The converter is operating in the voltage regulation mode (VM) and it’s output voltage is set via
the register OV[3:0]. The LED currents are regulated by the means of the low-side current
sinks. The LEDs are ready for flashlight operation.
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to
the output.
In high-current mode (HC_SEL = H), the energy is largely supplied by the output
reservoir capacitor. The inductive power stage is turned-on to support DC light
operation and to contribute the flash strobe itself.
11
1
LEDs are turned-off and the converter is operating in the voltage regulation mode (VM). The
output voltage is set via the register OV[3:0].
START-UP SEQUENCE
To avoid high inrush current during start-up, special care is taken to control the inrush current. When the device
enables, the internal startup cycle starts with the first step, the pre-charge phase.
During pre-charge, the rectifying switch is turned on until the output capacitor is either charged to a value close
to the input voltage or ca. 3.3V, whichever occurs first. The rectifying switch is current limited during that phase.
The current limit increases with decreasing input to output voltage difference. This circuit also limits the output
current under short-circuit conditions at the output. Figure 68 shows the typical pre-charge current vs. input
minus the output voltage for a specific input voltage.
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400
TPS61305
350
VIN = 3.6 V, TA = -40°C
DC Pre-Charge Current - mA
VIN = 3.6 V, TA = 25°C
300
250
200
150
VIN = 3.6 V, TA = 85°C
100
50
HC_SEL = 1
0
0
0.6
1.2
1.8
2.4
3
3.6
4.2
Differential Input - Output Voltage - V
Figure 68. Typical DC Pre-charge and Short-Circuit Current
In direct drive mode (HC_SEL = L, TPS6130x), after having pre-charged the output capacitor, the device
starts-up switching and increases its current limit in three steps of typically 250mA, 500mA and full current limit
(ILIM setting). The current limit transitions from the first to the second step occurs after a milli-second operation.
Full current limit operation is set once the output voltage has reached its regulation limits. In this mode, the active
balancing circuit is disabled.
In high-current mode (HC_SEL = H), the pre-charge voltage of the storage capacitor is depending on the input
voltage and operating mode (i.e., voltage regulation vs. current regulation mode). In case the device is set for
exclusive current regulation operation (i.e., MODE_CTRL[1:0] = 01 or 10 and ENVM = 0), the output capacitor
pre-charge voltage will be close to the input voltage. Under all other operating conditions, the pre-charge voltage
will either be close to the input voltage or to approximately 3.3V, whichever is lower.
After having pre-charged the storage capacitor, the device starts-up switching. During down-mode operation, the
inductor valley current is actively limited either to 250mA or 500mA (refer to ILIM setting). As the device enters
boost mode operation, the current limit transitions to its full capability (refer to ILIM setting and Tx-MASK input
logic state). As a consequence, the output voltage ramps-up linearly and the start-up time needed to reach the
programmed output voltage (refer to OV[3:0] bits) will mainly depend on the super-capacitor value and load
current. In this mode, the active balancing circuit is enabled.
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POWER GOOD (FLASH READY)
The TPS6130x integrates a power good circuitry that is activated when the device is operating in voltage
regulation mode (MODE_CTRL[1:0] = 11 or ENVM = 1). In shutdown mode (MODE_CTRL[1:0] = 00, ENDCL = 0
and ENVM = 0), the GPIO/PG pin state is defined as following:
GPIOTYPE
GPIO/PG SHUTDOWN STATE
0
Reset/pulled to ground
1
Open-drain
Depending on the GPIO/PG output stage type selection (i.e., push-pull or open-drain), the polarity of the
power-good output signal (PG) can be inverted or not. The power-good software bit and hardware signal polarity
is defined as following:
GPIOTYPE
0: push-pull output
1: open-drain output
PG BIT
GPIO/PG OUTPUT PORT
0
0
1
1
0
Open-drain
1
Low
COMMENTS
Output is active high signal polarity
Output is active low signal polarity
The power good signal is valid when the output voltage is within –1.5% and +2.5% of its nominal value.
Conversely, it is asserted low when the voltage mode operation gets suspended (MODE_CTRL[1:0] ≠ 11 and
ENVM = 0).
Forced PWM mode operation
Output Voltage
Down Regulation
Voltage Mode Request
1.025 VOUT (NOM )
Nom. Voltage
Output Voltage, VOUT
VOUT (NOM )
Start-up phase
0.985 VOUT (NOM )
Output Voltage
Up Regulation
Power Good Bit, (PG)
Power Good Output,
GPIO/PG
Hi-Z
Hi-Z
Forced PWM mode operation
(PG) Bit
Figure 69. Power Good Operation (DIR = 1, GPIOTYPE = 1)
The TPS6130x device uses a control architecture that allows to “recycle” excessive energy that might be stored
in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of
transferring energy from its output back into the input source. In this case, the power good signal is de-asserted
whilst the output voltage is decreasing towards its target value (i.e., the closest fit voltage the converter can
support, refer to the section “Down-Mode in Voltage Regulation Mode” for additional information).
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LED TEMPERATURE MONITORING (TPS61305, TPS61306)
The TPS61305 and TPS61306 devices monitor the LED temperature by measuring the voltage between the TS
and AGND pins. An internal current source provides the bias (c.a. 24 mA) for a negative-temperature coefficient
resistor (NTC), and the TS pin voltage is compared to internal thresholds (1.05V and 0.345V) to protect the LEDs
against overheating.
The temperature monitoring related blocks are always active in DC light or flashlight modes. In voltage mode
operation (MODE_CTRL[1:0] = 11), the device only activates the TS input when the ENTS bit is set to high. In
shutdown mode, the LED temperature supervision is disabled and the quiescent current of the device is
dramatically reduced.
The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage seen
at the TS pin is lower than 1.05V. This threshold corresponds to an LED warning temperature value, the device
operation is still permitted.
While regulating LED current (i.e.. DC light or flashlight modes), the LEDHOT bit is latched when the voltage
seen at the TS pin is lower than 0.345V. This threshold corresponds to an excessive LED temperature value, the
device operation is immediately suspended (MODE_CTRL[1:0] bits are reset and HOTDIE[1:0] bits are set).
HOT DIE DETECTOR
The hot die detector monitors the junction temperature but does not shutdown the device. It provides an early
warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown
during the next high-power flash strobe.
The hot die detector (HOTDIE[1:0] bits) reflects the instantaneous junction temperature and is always enabled
excepted when the device is in shutdown mode (MODE_CTRL[1:0] = 00, ENVM = 0 and ENDCL = 0).
NRESET INPUT: HARDWARE ENABLE / DISABLE
Some devices out of the TPS6130x family feature a hardware reset pin (NRESET). This reset pin allows the
device to be disabled by an external controller without requiring an I2C write command. Under normal operation,
the NRESET pin should be held high to prevent an unwanted reset. When the NRESET is driven low, the I2C
control interface and all internal control registers are reset to the default states and the part enters shutdown
mode.
ENDCL INPUT: DC LIGHT HARDWARE CONTROL
Some devices out of the TPS6130x family feature a dedicated DC light control input (ENDCL). This logic input
can be used to turn-on the LEDs for DC light operation. This hardware control pin can be useful to control the
torch light functionality from a separate engine (e.g., base-band). In this mode of operation, the DC light safety
timer is not activated.
The ENDCL input is only active when the device is programmed into shutdown (MODE_CTRL[1:0] = 00) or into
voltage regulation mode (MODE_CTRL[1:0] = 11 or ENVM = 1) and the indicator control is turned-off (INDC[3:0]
= 0000). LED1-3 inputs are controlled according to ENLED[3:1] bit settings.
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FLASHLIGHT BLANKING (Tx-MASK)
In direct drive mode (HC_SEL = 0), the Tx-MASK input signal can be used to disable the flashlight operation,
e.g., during a RF PA transmission pulse. This blanking function turns the LED from flashlight to DC light thereby
reducing almost instantaneously the peak current loading from the battery. The Tx-MASK function has no
influence on the safety timer duration.
FLASH
LED Current
DC LIGHT
FLASH_SYNC
Tx- MASK
Figure 70. Synchronized Flashlight With Blanking Periods
In high-current mode (HC_SEL = 1), the Tx-MASK input pin is also used to dynamically adjusts the device’s
current limit setting (i.e. controls the maximum current drawn from the input source). Refer to the section “Current
Limit Operation” for additional information.
UNDERVOLTAGE LOCKOUT
The under-voltage lockout circuit prevents the device from mis-operation at low input voltages. It prevents the
converter from turning on the switch–MOSFET, or rectifier–MOSFET for battery voltages below 2.3V. The I2C
compatible interface is fully functional down to 2.1V input voltage.
SHUTDOWN
MODE_CTRL[1:0] bits low force the device into shutdown. The shutdown state can only be entered when the
voltage regulation and DC light modes are both turned-off (ENVM = 0 and ENDCL = 0).
In direct drive mode (HC_SEL = L), the regulator stops switching, the high-side PMOS disconnects the load from
the input and the LEDx pins are high impedance thus eliminating any DC conduction path. The TPS6130x device
actively discharges the output capacitor when it turns off.
The integrated discharge resistor has a typical resistance of 2kΩ equally split-off between VOUT to BAL and BAL
to GND outputs. The required time to discharge the output capacitor at VOUT depends on load current and the
effective output capacitance. The active balancing circuit is disabled and the device consumes only a shutdown
current of 1mA (typ).
In high-current mode (HC_SEL = H), the device maintains its output biased at the input voltage level. In this
mode, the synchronous rectifier is current limited (i.e. pre-charge current) allowing external load (e.g. audio
amplifier) to be powered with a restricted supply. The active balancing circuit is enabled and the device
consumes only a standby current of 5mA (typ).
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 160°C typical, the device goes into thermal shutdown. In this
mode, the power stage and the low-side current regulators are turned-off, the HOTDIE[1:0] bits are set and can
only be reset by a readout.
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In the voltage mode operation (MODE_CTRL[1:0] = 11 or ENVM = 1), the device continues its operation when
the junction temperature falls below 140°C typ. again. In the current regulation mode (i.e., DC light or flashlight
modes) the device operation is suspended.
STORAGE CAPACITOR ACTIVE CELL BALANCING
A fully charged super-capacitor will typically have leakage current of under 1mA. The TPS6130x device integrates
an active balancing feature to cut the total leakage current from the super-capacitor and balance circuit to less
than 1.7mA typ.
The device integrates a window comparator monitoring the tap point of the multi-cell super-capacitor. The
balancing output (BAL) is substantially half the actual output voltage (VOUT). If the internal leakage current in one
of the capacitors is larger than that in the other, then the voltage at their junction will tend to change in such a
way that the voltage on the capacitor with the larger (or largest) leakage current will reduce.
When this happens, a current will begin to flow from the BAL output in such a direction as to reduce the amount
by which the voltage changes. The current that will flow after a long period of steady-state conditions will be
approximately equal to the difference between the leakage currents of the pair of capacitors which is being
balanced by the circuit. The output resistance of the balancing circuit (c.a. 250Ω) determines how quickly an
imbalance will be corrected.
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RED LIGHT PRIVACY INDICATOR
The TPS6130x device provides a high-side linear constant current source to drive low VF LEDs. The LED current
is directly regulated off the battery and can be controlled via the INDC[3:0] bits. Operation is understood best by
referring to the Figure 71 and Figure 72.
AVIN
Backgate
Control
SW
L
VOUT
VBAT
CIN
CO
INDC [3:2] = 01 && INDC[1:0] 00
P
P
P
VOUT < TBD V
P
D1
SHUTDOWN ACTIF
D2
P
LED2
ON/OFF
Hi-Z
P
LED1
LED3
ON/OFF
Hi-Z
P
AVIN
INDLED
INDC[3:0]
High-Side LED Current Regulator
Figure 71. RED Light Indicator, Configuration 1
AVIN
L
Backgate
Control
SW
VOUT
VBAT
CIN
CO
INDC[3:2] = 01 && INDC[1:0] 00
P
P
P
VOUT < TBD V
P
SHUTDOWN ACTIF
D1
D2
P
LED2
ON/OFF
Hi-Z
P
LED1
LED3
ON/OFF
Hi-Z
P
AVIN
INDLED
INDC[3:0]
High-Side LED Current Regulator
Figure 72. RED Light Indicator, Configuration 2
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The device can provide a path to allow for reverse biasing of white LEDs (refer to Figure 72). To do so, the
output of the converter (VOUT) is pulled to ground thus allowing a reverse current to flow. This mode of
operation is only possible when the converter’s power stage is in shutdown (MODE_CTRL[1:0] = 00, ENVM = 0,
ENDCL = 0 and HC_SEL = 0).
WHITE LED PRIVACY INDICATOR
The TPS6130x device features white LED drive capability at very low light intensity. To generate a reduced LED
average current, the device employs a 122Hz fixed frequency PWM modulation scheme. Operation is understood
best by referring to the timer block diagram.
The DC light current is modulated with a duty cycle defined by the INDC[3:0] bits. The low light dimming mode
can only be activated in the software controlled DC light only mode (MODE_CTRL[1:0] = 01, ENVM = X, ENDCL
= 0) and applies to the LEDs selected via ENLED[3:1] bits. In this mode, the DC light safety timeout feature is
disabled.
PWM Dimming Steps
0.8%, 1.6%, 2.3%, 3.1%, 3.9%, 4.7%, 6.3%, 8.6%
I DCLIGHT
t1
I LED (DC ) = I DCLIGHT x PWM Dimming Step
0
T PWM
Figure 73. PWM Dimming Principle
STORAGE CAPACITOR, PRE-CHARGE VOLTAGE CALIBRATION
High-power LEDs tend to exhibit a wide forward voltage distribution. The TPS6130x device integrates a
self-calibration procedure that can be used to determine the optimum super-capacitor pre-charge voltage based
on the actual worst case LED forward voltage and ESR of the storage capacitor. This calibration procedure is
meant to start-off at a min. output voltage and can be initiated by setting the SELFCAL bit (preferably with
MODE_CTRL[1:0] = 00, ENVM = 0, ENDCL = 0).
The calibration procedure monitors the sense voltage across the low-side current regulators (according to
ENLED[3:1] bits setting) and registers the worst case LED (i.e. the LED featuring the largest forward voltage).
The TPS6130x device automatically sweeps through its output voltage range and performs a short duration flash
strobe for each step (refer to FC13[1:0] and FC2[2:0] bits settings).
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. In
high-current mode (HC_SEL = H), the energy is supplied exclusively by the output reservoir capacitor and the
inductive power stage is turned-off for the flash strobe period of time.
The sequence is stopped as soon as the device detects that each of the low-side current regulators have enough
headroom voltage (i.e. 400mV typ.). The device returns the according output voltage in the register OV[3:0] and
sets the SELFCAL bit. This bit is only being reset at the (re-)start of a calibration cycle. In other words, when
SELFCAL is asserted the output voltage register (OV[3:0]) returns the result of the last calibration sequence.
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Output Voltage, VOUT
ESR x ILED
~200 ms
Feedback Sense
Comparator Information
VBAT
Power Good, PG
~200 ms
LED Flash Current, IFLASH
Feedback Sense Comparator Output
VLED > 400 mV
OV[3:0]
0000
0001
0010
0011
0100
0101
Self-Calibration,
SELFCAL bit (write)
Self-Calibration,
SELFCAL bit (read)
X
Figure 74. LED Forward Voltage Self-Calibration Principle
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STORAGE CAPACITOR, ADAPTIVE PRE-CHARGE VOLTAGE
In high-power LED camera flash applications, the storage capacitor is supposed to be charged to an optimum
voltage level in order to:
• Maintain sufficient headroom voltage across the LED current regulators for the entire strobe time.
• Minimize the power dissipation in the device.
High-power LEDs tend to exhibit large dynamic forward voltage variation relating to own self-heating effects. In
addition, the energy storage capacitor (i.e., Electrochemical Double-Layer Capacitor or Super-Capacitor) also
shows a relatively large effective capacitance and ESR spread. The main factors contributing to these variations
are:
• Flash strobe duration
• Temperature
• Ageing effects
In practice, it normally becomes very challenging to compensate for all these variations and a worst-case design
would presumably be too pessimistic. As a consequence, designers would have to give-up on the benefits
coming along with the “Storage Capacitor, Pre-Charge Voltage Calibration” approach.
The TPS6130x device offers the possibility of controlling the storage capacitor pre-charge voltage in a
closed-loop manner. The principle is to dynamically adjust the initial pre-voltage to the minimum value, as
required for the particular components characteristic and operating conditions.
The reference criteria used to evaluate proper operation is the headroom voltage across the LED current
regulators. In case of a critical headroom voltage (VLED1-3) at the end of a flash strobe (i.e., n cycle), the
pre-charge voltage should be increased prior to the next capture sequence (i.e., n+1 cycle).
Output Voltage, VOUT
ESR x ILED
Critical Headroom Voltage
LED Flash Current, IFLASH
Feedback Sense Comparator Output
(VLED > 400 mV)
Power Good, PG
LEDHDR bit
FLASH_SYNC
Figure 75. Storage Capacitor, Simple Adaptive Pre-Charge Voltage
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SERIAL INTERFACE DESCRIPTION
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with
pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices
connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or
a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives and/or transmits data on the bus under control of the master device.
The TPS6130x device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps).
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.1V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as
HS-mode. The TPS6130x device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7bit address is defined as ‘011 0011’.
F/S-MODE PROTOCOL
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 76. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 76. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 77). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 78) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 77. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
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To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 76). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 78. Acknowledge on the I2C Bus
Figure 79. Bus Protocol
HS-MODE PROTOCOL
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
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TPS6130x I2C UPDATE SEQUENCE
The TPS6130x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6130x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I2C address selects the TPS6130x. TPS6130x performs an update
on the falling edge of the acknowledge signal that follows the LSB byte.
1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A
P
“0” Write
A
S
Sr
P
From Master to TPS6130x
From TPS6130x to Master
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 80. : “Write” Data Transfer Format in F/S-Mode
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
“0” Write
“1” Read
From Master to TPS6130x
A
S
Sr
P
From TPS6130x to Master
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 81. “Read” Data Transfer Format in F/S-Mode
F/S Mode
HS Mode
F/S Mode
1
8
1
1
7
1
1
8
1
8
1
1
S
HS-Master Code
A
Sr
Slave Address
R/W
A
Register Address
A
Data
A/A
P
Data Transferred
(n x Bytes + Acknowledge)
HS Mode Continues
Sr
A
A
S
Sr
P
From Master to TPS6130x
From TPS6130x to Master
Slave Address
= Acknowledge
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 82. Data Transfer Format in H/S-Mode
SLAVE ADDRESS BYTE
MSB
X
LSB
X
X
X
X
X
A1
A0
The slave address byte is the first byte received following the START condition from the master device.
REGISTER ADDRESS BYTE
MSB
0
LSB
0
0
0
00
D2
D1
D0
Following the successful acknowledgement of the slave address, the bus master will send a byte to the
TPS6130x, which will contain the address of the register to be accessed.
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REGISTER1 DESCRIPTION (TPS61300, TPS61301)
Memory location: 0x01
Description
Bits
Memory type
Default value
ENVM
D7
R/W
0
MODE_CTRL[1:0]
D6
D5
R/W
R/W
0
0
DCLC13[1:0]
D4
D3
R/W
R/W
0
1
D2
R/W
0
DCLC2[1:0]
D1
R/W
0
D0
R/W
1
Bit
Description
ENVM
Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0]
Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER1[6:5] automatically updates REGISTER2[6:5].
DCLC13[1:0]
DC Light Current Control bits (LED1/3).
00: 0mA. LEDs are off, VOUT set according to OV[3:0]. (1)
01: 50mA
10: 75mA
11: 100mA
DCLC2[2:0]
DC Light Current Control bits (LED2).
000: 0mA. LEDs are off, VOUT set according to OV[3:0]. (1)
001: 50mA
010: 75mA
011: 100mA
100: 125mA
101: 150mA
110: 200mA, 350mA current level can be activated simultaneously with Tx-MASK = 1.
111: 250mA, 500mA current level can be activated simultaneously with Tx-MASK = 1.
(1)
54
When DCLC2[2:0] and DCLC13[1:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according
to OV[3:0].
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REGISTER1 DESCRIPTION (TPS61305, TPS61306)
Memory location: 0x01
Description
Bits
Memory type
Default value
ENVM
D7
R/W
0
MODE_CTRL[1:0]
D6
D5
R/W
R/W
0
0
DCLC13[1:0]
D4
D3
R/W
R/W
0
1
D2
R/W
0
DCLC2[1:0]
D1
R/W
0
D0
R/W
1
Bit
Description
ENVM
Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0]
Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER1[6:5] automatically updates REGISTER2[6:5].
DCLC13[1:0]
DC Light Current Control bits (LED1/3).
00: 0mA. LEDs are off, VOUT set according to OV[3:0]. (1)
01: 55mA
10: 85mA
11: 110mA
DCLC2[2:0]
DC Light Current Control bits (LED2).
000: 0mA. LEDs are off, VOUT set according to OV[3:0]. (1)
001: 55mA
010: 85mA
011: 110mA
100: 140mA
101: 165mA
110: 220mA, 350mA current level can be activated simultaneously with Tx-MASK = 1.
111: 275mA, 500mA current level can be activated simultaneously with Tx-MASK = 1.
(1)
When DCLC2[2:0] and DCLC13[1:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according
to OV[3:0].
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REGISTER2 DESCRIPTION (TPS61300, TPS61301)
Memory location: 0x02
Description
Bits
Memory type
Default value
ENVM
D7
R/W
0
MODE_CTRL[1:0]
D6
D5
R/W
R/W
0
0
FC13[1:0]
D4
R/W
0
D3
R/W
0
D2
R/W
0
FC2[1:0]
D1
R/W
1
D0
R/W
1
Bit
Description
ENVM
Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0]
Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5].
FC13[1:0]
Flash Current Control bits (LED1/3).
HC_SEL = 0
00: 250mA
01: 300mA
10: 350mA
11: 400mA
FC2[2:0]
Flash Current Control bits (LED2).
HC_SEL = 0
000: 275mA
001: 300mA
010: 350mA
011: 450mA
100: 550mA
101: 600mA
110: 700mA
111: 800mA
56
HC_SEL = 1
00: 600mA
01: 700mA
10: 800mA
11: 925mA
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HC_SEL = 1
000: 650mA
001: 700mA
010: 825mA
011: 1050mA
100: 1300mA
101: 1400mA
110: 1600mA
111: 1850mA
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REGISTER2 DESCRIPTION (TPS61305, TPS61306)
Memory location: 0x02
Description
Bits
Memory type
Default value
ENVM
D7
R/W
0
MODE_CTRL[1:0]
D6
D5
R/W
R/W
0
0
FC13[1:0]
D4
R/W
0
D3
R/W
0
D2
R/W
0
F2[1:0]
D1
R/W
1
D0
R/W
1
Bit
Description
ENVM
Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
MODE_CTRL[1:0]
Mode Control bits.
00: Device in shutdown mode.
01: Device operates in DC light mode.
10: Device operates in DC light and flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by DC light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less than
11.2s.
Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5].
FC13[1:0]
Flash Current Control bits (LED1/3).
HC_SEL = 0
00: 275mA
01: 335mA
10: 385mA
11: 445mA
FC2[2:0]
HC_SEL = 1
00: 665mA
01: 775mA
10: 890mA
11: 1025mA
Flash Current Control bits (LED2).
HC_SEL = 0
000: 305mA
001: 335mA
010: 385mA
011: 500mA
100: 610mA
101: 665mA
110: 775mA
111: 885mA
HC_SEL = 1
000: 720mA
001: 775mA
010: 915mA
011: 1165mA
100: 1450mA
101: 1550mA
110: 1775mA
111: 2050mA
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REGISTER3 DESCRIPTION
Memory location: 0x03
Description
Bits
Memory type
Default value
STIM[2:0]
D7
R/W
1
D6
R/W
1
Bit
Description
STIM[2:0]
Safety Timer bits.
HPLF
D5
R/W
0
D4
R
0
SELSTIM (W)
TO (R)
D3
R
0
STIM[2:0]
RANGE 0
RANGE 1
STIM[2:0]
RANGE 0
RANGE 1
000
68.2ms
5.3ms
100
204.5ms
26.6ms
001
102.2ms
10.7ms
101
340.8ms
32.0ms
010
136.3ms
16.0ms
110
579.3ms
37.3ms
011
170.4ms
21.3ms
111
852ms
207.7ms
STT
SFT
Tx-MASK
D2
R/W
0
D1
R/W
0
D0
R/W
1
HPFL
High-Power LED Failure flag.
0: Proper LED operation.
1: LED failed (open or shorted).
High-power LED failure flag is reset after readout
SELSTIM
Safety Timer Selection Range (Write Only).
0: Safety timer range 0.
1: Safety timer range 1.
TO
Time-Out Flag (Read Only).
0: No time-out event occurred.
1: Time-out event occurred. Time-out flag is reset at re-start of the safety timer.
STT
Safety Timer Trigger bit.
0: LED safety timer is level sensitive.
1: LED safety timer is rising edge sensitive.
This bit is only valid for MODE_CTRL[1:0] = 10.
SFT
Start/Flash Timer bit.
In write mode, this bit initiates a flash strobe sequence.
0: No change in the high-power LED current.
1: High-power LED current ramps to the flash current level.
In read mode, this bit indicates the high-power LED status.
0: High-power LEDs are idle.
1: Ongoing high-power LED flash strobe.
Tx-MASK
Flash Blanking Control bit.
In write mode, this bit enables/disables the flash blanking/LED current reduction function.
0: Flash blanking disabled.
1: LED current is reduced to DC light level when Tx-MASK input is high.
In read mode, this flag indicates whether or not the flashlight masking input has been activated. Tx-MASK flag is reset
after readout of the flag.
0: No flash blanking event occurred.
1: Tx-MASK input triggered.
58
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REGISTER4 DESCRIPTION
Memory location: 0x04
Description
Bits
Memory type
Default value
PG
D7
R/W
0
HOTDIE[1:0]
D6
D5
R
R
0
0
ILIM
D4
R/W
0
INC[3:0]
D3
R/W
0
D2
R/W
0
Bit
Description
PG
Power Good bit.
In write mode, this bit selects the functionality of the GPIO/PG output.
0: PG signal is routed to the GPIO port.
1: GPIO PORT VALUE bit is routed to the GPIO port.
In read mode, this bit indicates the output voltage conditions.
0: The converter is not operating within the voltage regulation limits.
1: The output voltage is within its nominal value.
HOTDIE[1:0]
Instantaneous Die Temperature bits.
00: TJ < +55°C
01: +55°C < TJ < +70°C
10: TJ > +70°C
11: Thermal shutdown tripped. Indicator flag is reset after readout.
ILIM
Inductor Valley Current Limit bit.
The ILIM bit can only be set before the device enters operation (i.e. initial shutdown state).
CURRENT LIMIT
SETTING
INDC[3:0]
ILIM BIT
SETTING
HC_SEL
INPUT LEVEL
Tx-MASK
INPUT LEVEL
1250mA
Low
Low
Low
1750mA
High
Low
Low
1250mA
Low
High
Low
1750mA
High
High
Low
1250mA
Low
Low
High
1750mA
High
Low
High
250mA
Low
High
High
500mA
High
High
High
D0
R/W
0
Indicator Light Control bits.
INDC[3:0]
PRIVACY INDICATOR
INDLED CHANNEL
INDC[3:0]
PRIVACY INDICATOR
LED1-3 CHANNELS (1)
0000
Privacy indicator turned-off
1000
0.8% PWM dimming ratio
0001
INDLED current = 2.6mA
1001
1.6% PWM dimming ratio
0010
INDLED current = 5.2mA
1010
2.3% PWM dimming ratio
0011
INDLED current = 7.9mA
1011
3.1% PWM dimming ratio
0100
Privacy indicator turned-off
1100
3.9% PWM dimming ratio
0101
INDLED current = 2.6mA (2)
1101
4.7% PWM dimming ratio
0110
INDLED current = 5.2mA (2)
1110
6.3% PWM dimming ratio
1111
8.6% PWM dimming ratio
0111
(1)
(2)
D1
R/W
0
INDLED current = 7.9mA
(2)
This mode of operation can only be activated for MODE_CTRL[1:0] = 01 & ENDCL = 0.
The output node is internally pulled to ground. This mode is only possible for HC_SEL = L.
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REGISTER5 DESCRIPTION
Memory location: 0x05
Description
Bits
Memory type
Default value
SELFCAL
ENPSM
D7
R/W
0
D6
R/W
1
DIR (W)
STENDCL
(R)
D5
R/W
1
GPIO
GPIOTYPE
ENLED3
ENLED2
ENLED1
D4
R/W
0
D3
R/W
1
D2
R/W
0
D1
R/W
1
D0
R/W
0
Bit
Description
SELFCAL
High-Current LED Forward Voltage Self-Calibration Start bit.
In write mode, this bit enables/disables the output voltage vs. LED forward voltage/current self-calibration procedure.
0: Self-calibration disabled.
1: Self-calibration enabled.
In read mode, this bit returns the status of the self-calibration procedure.
0: Self-calibration ongoing
1: Self-calibration done Notice that this bit is only being reset at the (re-)start of a calibration cycle.
ENPSM
Enable / Disable Power-Save Mode bit.
0: Power-save mode disabled.
1: Power-save mode enabled.
STENDCL
ENDCL Input Status bit (Read Only).
This bit indicates the logic state on the ENDCL state. This bit is only active in TPS61300.
DIR
GPIO Direction bit.
0: GPIO configured as input.
1: GPIO configured as output.
GPIO
GPIO Port Value.
This bit contains the GPIO port value.
GPIOTYPE
GPIO Port Type.
0: GPIO is configured as push-pull output.
1: GPIO is configured as open-drain output.
ENLED3
Enable / Disable High-Current LED3 bit.
0: LED3 input is disabled.
1: LED3 input is enabled.
ENLED2
Enable / Disable High-Current LED2 bit.
0: LED2 input is disabled.
1: LED2 input is enabled.
ENLED1
Enable / Disable High-Current LED1 bit.
0: LED1 input is disabled.
1: LED1 input is enabled.
60
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REGISTER6 DESCRIPTION (TPS61300, TPS61301)
Memory location: 0x06
Description
Bits
Memory type
Default value
D7
R/W
0
NOT USED
D6
R/W
0
D5
R/W
0
LEDHDR
D4
R
0
OV[3:0]
D3
R/W
1
D2
R/W
0
D1
R/W
0
D0
R/W
1
Bit
Description
LEDHDR
LED High-Current Regulator Headroom Voltage Monitoring bit.
This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the end of a
flash strobe, prior to the LED current ramp-down phase.
0: Low headroom voltage.
1: Sufficient headroom voltage.
OV[3:0]
Output Voltage Selection bits. In read mode, these bits return the result of the high-current LED forward voltage
self-calibration procedure.
In write mode, these bits are used to set the target output voltage (refer to voltage regulation mode). In applications
requiring dynamic voltage control, care should be take to set the new target code after voltage mode operation has been
enabled (MODE_CTRL[1:0] = 11 and/or ENVM bit = 1).
OV[3:0]
Target Output Voltage
0000
3.825V
0001
3.950V
0010
4.075V
0011
4.200V
0100
4.325V
0101
4.450V
0110
4.575V
0111
4.700V
1000
4.825V
1001
4.950V
1010
5.075V
1011
5.200V
1100
5.325V
1101
5.450V
1110
5.575V
1111
5.700V
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REGISTER6 DESCRIPTION (TPS61305)
Memory location: 0x06
Description
Bits
Memory type
Default value
ENTS
D7
R/W
0
LEDHOT
D6
R/W
0
LEDWARN
D5
R
0
LEDHDR
D4
R
0
OV[3:0]
D3
R/W
1
D2
R/W
0
D1
R/W
0
D0
R/W
1
Bit
Description
ENTS
Enable / Disable LED Temperature Monitoring.
0: LED temperature monitoring disabled.
1: LED temperature monitoring enabled
LEDHOT
LED Excessive Temperature Flag.
This bit can be reset by writing a logic level zero.
0: TS input voltage > 0.345V.
1: TS input voltage < 0.345V.
LEDWARN
LED Temperature Warning Flag (Read Only).
This flag is reset after readout.
0: TS input voltage > 1.05V.
1: TS input voltage < 1.05V.
LEDHDR
LED High-Current Regulator Headroom Voltage Monitoring bit.
This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the end of a
flash strobe, prior to the LED current ramp-down phase.
0: Low headroom voltage.
1: Sufficient headroom voltage.
0V[3:0]
Output Voltage Selection bits.
In read mode, these bits return the result of the high-current LED forward voltage self-calibration procedure.
In write mode, these bits are used to set the target output voltage (refer to voltage regulation mode). In applications
requiring dynamic voltage control, care should be take to set the new target code after voltage mode operation has been
enabled (MODE_CTRL[1:0] = 11 and/or ENVM bit = 1).
62
OV[3:0]
Target Output Voltage
0000
3.825V
0001
3.950V
0010
4.075V
0011
4.200V
0100
4.325V
0101
4.450V
0110
4.575V
0111
4.700V
1000
4.825V
1001
4.950V
1010
5.075V
1011
5.200V
1100
5.325V
1101
5.450V
1110
5.575V
1111
5.700V
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
REGISTER7 DESCRIPTION
Memory location: 0x07
Description
Bits
Memory type
Default value
D7
R/W
0
D6
R/W
0
Bit
Description
REVID[2:0]
Silicon Revision ID.
NOT USED
D5
R/W
0
D4
R/W
0
D3
R/W
0
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D2
R
1
REVID[2:0]
D1
R
0
D0
R
0
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APPLICATION INFORMATION
INDUCTOR SELECTION
A boost converter requires two main passive components for storing energy during the conversion. A boost
inductor and a storage capacitor at the output are required. The TPS6130x device integrates a current limit
protection circuitry. The valley current of the PMOS rectifier is sensed to limit the maximum current flowing
through
the
synchronous
rectifier
and
the
inductor.
The
valley
peak
current
limit
(250mA/500mA/1250mA/1750mA) is user selectable via the I2C interface.
In order to optimize solution size the TPS6130x device has been designed to operate with inductance values
between a minimum of 1.3 mH and maximum of 2.9 mH. In typical high current white LED applications a 2.2mH
inductance is recommended.
The highest peak current through the inductor and the power switch depends on the output load, the input and
output voltages. Estimation of the maximum average inductor current and the maximum inductor peak current
can be done using Equation 2 and Equation 3:
VOUT
IL » IOUT ´
η ´ VIN
(2)
IL(PEAK) =
VIN ´ D
2 ´ f ´ L
+
IOUT
(1 - D) ´ h
with D =
VOUT - VIN
VOUT
(3)
With
f = switching frequency (2MHz)
L = inductance value (2.2mH)
h = estimated efficiency (85%)
The losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for
total circuit efficiency.
Table 4. List of Inductors
MANUFACTURER
SERIES
DIMENSIONS
MIPST2520
2.5mm x 2.0mm x 0.8mm max. height
MIP2520
2.5mm x 2.0mm x 1.0mm max. height
MIPSA2520
2.5mm x 2.0mm x 1.2mm max. height
LQM2HP-G0
2.5mm x 2.0mm x 1.0mm max. height
LQM2HP-GC
2.5mm x 2.0mm x 1.0mm max. height
TDK
VLF3014AT
2.6mm x 2.8mm x 1.4mm max. height
COILCRAFT
LPS3015
3.0mm x 3.0mm x 1.5mm max. height
MURATA
LQH2HPN
2.5mm x 2.0mm x 1.2mm max. height
TOKO
FDSE0312
3.0mm x 3.0mm x 1.2mm max. height
MURATA
LQM32PN
3.2mm x 2.5mm x 1.2mm max. height
FDK
MURATA
ILIM SETTINGS
250mA (typ.)
500mA (typ.)
1250mA (typ.)
1750mA (typ.)
INPUT CAPACITOR
For good input voltage filtering low ESR ceramic capacitors are recommended. A 10-mF input capacitor is
recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit.
The input capacitor should be placed as close as possible to the input pin of the converter.
64
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OUTPUT CAPACITOR
The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by
using Equation 4:
IOUT × (V OUT - VIN)
Cmin »
f ´ DV ´ V OUT
(4)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 10mV, a minimum capacitance of 10mF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 5:
ΔVESR = IOUT × RESR
(5)
(5)
The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the
capacitor. Additional ripple is caused by load transients. This means that the output capacitor has to completely
supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends
on the speed of the load transients and the load current during the load change.
For the standard current white LED application (HC_SEL = 0, TPS6130x), a minimum of 3mF effective output
capacitance is usually required when operating with 2.2mH (typ) inductors. For solution size reasons, this is
usually one or more X5R/X7R ceramic capacitors.
Depending on the material, size and therefore margin to the rated voltage of the used output capacitor,
degradation on the effective capacitance can be observed. This loss of capacitance is related to the DC bias
voltage applied. It is therefore always recommended to check that the selected capacitors are showing enough
effective capacitance under real operating conditions.
To support high-current camera flash application (HC_SEL = 1), the converter is designed to work with a low
voltage super-capacitor on the output to take advantage of the benefits they offer. A low-voltage super-capacitor
in the 0.1F to 1.5F range, and with ESR larger than 40mΩ, is suitable in the TPS6130x application circuit. For
this device the output capacitor should be connected between the VOUT pin and a good ground connection.
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NTC SELECTION (TPS61305, TPS61306)
The TPS61305/306 requires a negative thermistor (NTC) for sensing the LED temperature. Once the
temperature monitoring feature is activated, a regulated bias current (c.a. 24mA) will be driven out of the TS port
and produce a voltage across the thermistor.
If the temperature of the NTC-thermistor rises due to the heat dissipated by the LED, the voltage on the TS input
pin decreases. When this voltage goes below the “warning threshold”, the LEDWARN bit in REGISTER6 is set.
This flag is cleared by reading the register.
If the voltage on the TS input decreases further and falls below “hot threshold”, the LEDHOT bit in REGISTER6
is set and the device goes automatically in shutdown mode to avoid damaging the LED. This status is latched
until the LEDHOT flag gets cleared by software.
The selection of the NTC-thermistor value strongly depends on the power dissipated by the LED and all
components surrounding the temperature sensor and on the cooling capabilities of each specific application. With
a 220kΩ (at 25°C) thermistor, the valid temperature window is set between 60°C to 90°C. The temperature
window can be enlarged by adding external resistors to the TS pin application circuit. In order to ensure proper
triggering of the LEDWARN and LEDHOT flags in noisy environments, the TS signal may require additional
filtering capacitance.
Figure 83. Temperature Monitoring Characteristic
Table 5. List of Negative Thermistor (NTC)
66
MANUFACTURER
PART NUMBER
VALUE
MURATA
NCP18WM224J03RB
220kΩ
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CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations the
regulation loop may be unstable. This is often a result of improper board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop the load transient response needs to be tested. VOUT can
be monitored for settling time, overshoot or ringing that helps judge the converter's stability. Without any ringing,
the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
output current range, and temperature range.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks.
The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a
common ground node for power ground and a different one for control ground to minimize the effects of ground
noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To lay out the control ground, it is recommended to use short traces as well, separated from the power ground
traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and
control ground current.
L1
GND
SDA
COUT
INDLED
B2: SCL
B3: HC_SEL
C3: Tx_MASK
D3: ENDCL (TPS61300)
nRESET (TPS61301/5)
D4: GPIO/PG
BAL
FLASH_SYNC
1
ENVM (TPS61300/1)
TS
(TPS61305)
CIN
GND
VIN
LED2
LED1 LED3
Figure 84. Suggested Layout (Top)
Copyright © 2009–2010, Texas Instruments Incorporated
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TPS61300, TPS61301, TPS61305
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www.ti.com
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
The maximum junction temperature (TJ) of the TPS6130x is 150°C.
PDIS - Single Pulse Constant Power Dissipation - W
The maximum power dissipation is especially critical when the device operates in the linear down mode at high
LED current. For single pulse power thermal analysis (e.g., flashlight strobe), the allowable power dissipation for
the device is given by Figure 85. These values are derived using the reference design.
10
9
8
TJ = 65°C rise
7
6
5
4
3
2
TJ = 40°C rise
1
No Airflow
0
0
20
40
60
80 100 120 140 160 180 200
Pulse Width - ms
Figure 85. Single Pulse Power Capability
68
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TYPICAL APPLICATIONS
TPS61305
2.2 mH
SW
SW
VOUT
SUPER-CAP
L
AVIN
2.5 V..5.5 V
CI
PHONE POWER ON
CAMERA ENGINE
HC_ SEL
BAL
NRESET
LED 1
CO
D1
10 mF
D2
FLASH_SYNC LED 2
LED 3
SCL
SDA
I2C I/F
INDLED
Privacy
Indicator
Tx-MASK
1.8 V
NTC
GPIO/PG
TS
220k
AGND
PGND
PGND
FLASH READY
Figure 86. 4100mA Two White High-Power LED Flashlight Featuring Storage Capacitor
TPS61300
L
2.2 mH
SW
SW
VOUT
CO
AVIN
2.5 V..5.5 V
HC_SEL
CI
CAMERA ENGINE
BAL
ENDCL
LED1
FLASH_SYNC
LED2
10 mF
D1
D2
LED3
I2C I/F
SCL
SDA
INDLED
Privacy
Indicator
RF PA TX ACTIVE
Tx-MASK
ENVM
GPIO/PG
AGND
PGND
PGND
Figure 87. 2x 600mA High Power White LED Solution Featuring Privacy Indicator
Copyright © 2009–2010, Texas Instruments Incorporated
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TPS61300
L
2.2 mH
SW
SW
CO
AVIN
2.5V..5.5V
BAL
HC_SEL
CI
+5.0 V
VOUT
10mF
D1
D2
CLASS-D APA
Audio Input
Audio Input
ENABLE TORCH(BB)
CAMERA ENGINE
ENDCL
LED 1
FLASH_SYNC
LED 2
EN
LED 3
SCL
SDA
I2C I/F
INDLED
Privacy
Indicator
RF PA TX ACTIVE
Tx-MASK
ENABLE APA (BB)
ENVM
GPIO/PG
AGND
PGND
PGND
Figure 88. White LED Flashlight Driver and Audio Amplifier Power Supply Operating Simultaneously
TPS61300
L
2.2 mH
SW
SW
CO
AVIN
2.5 V..5.5 V
CI
+4.2 V
VOUT
HC_SEL
BAL
10mF
D1
D2
Audio Input
Audio Input
ENABLE TORCH(BB)
CAMERA ENGINE
ENDCL
LED1
FLASH_SYNC
LED2
CLASS-D APA
FEATURING I2C CONTROL I/F
Note:
Reduce audio gain to allow simultaneous
operation together this the camera engine
.
LED3
High Speed
I 2C I/F
SCL
SDA
INDLED
Privacy
Indicator
RF PA TX ACTIVE
Tx-MASK
ENVM
GPIO/PG
AGND
PGND
PGND
Figure 89. White LED Flashlight Driver and Audio Amplifier Power Supply Operating Simultaneously
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TPS61300, TPS61301, TPS61305
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
TPS 61300
L
2.2 mH
SW
SW
+5.0 V
VOUT
CO
AVIN
2.5 V..5.5 V
HC_SEL
CI
10mF
BAL
D1
D2
Audio Input
Audio Input
ENABLE TORCH (BB)
CAMERA ENGINE
ENDCL
LED 1
FLASH_SYNC
LED 2
EN_APA
GAIN _SEL
0:Nominal Gain
1:-6 dB Gain
LED 3
I2C I/F
SCL
SDA
INDLED
Privacy
Indicator
RF PA TX ACTIVE
Tx-MASK
ENABLE APA (BB)
ENVM
GPIO/PG
AGND
PGND
PGND
Figure 90. White LED Flashlight Driver and Audio Amplifier Power Supply Exclusive Operation
TPS 61300
L
2.2mH
2.5 V..5.5 V
CI
ENABLE TORCH (BB)
CAMERA ENGINE
SW
SW
AVIN
HC_SEL
ENDCL
VOUT
BAL
CO
10 mF
D1
Dx
D2
Dy
Dz
LED1
FLASH_SYNC LED2
LED3
CAMERA ENGINE
I2C I/F
RF PA TX ACTIVE
SCL
SDA
+1.8V TCA6507
VCC
P0
INDLED
Privacy
Indicator
BASE-BAND ENGINE
I2C I/F
SCL
SDA
EN
P1
P2
Tx-MASK
ENVM
GPIO/PG
AGND
PGND
PGND
GND
VOLTAGE MODE ENABLE
BASE-BAND ENGINE
Figure 91. White LED Flashlight Driver and Auxiliary Lighting Zone Power Supply
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS61300, TPS61301, TPS61305
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SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
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PACKAGE SUMMARY
CHIP SCALE PACKAGE
(BOTTOM VIEW)
D
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
E
CHIP SCALE PACKAGE
(TOP VIEW)
TIYMLLLLS
TPS613__
A1
Code:
•
YM — Year Month date code
•
LLLL — Lot trace code
•
S — Assembly site code
CHIP SCALE PACKAGE DIMENSIONS
The TPS6130x device is available in a 20-bump chip scale package (YFF, NanoFree™). The package
dimensions are given as:
• D = 2170 ±30 mm
• E = 1928 ±30 mm
72
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TPS61300, TPS61301, TPS61305
www.ti.com
SLVS957A – JUNE 2009 – REVISED SEPTEMBER 2010
NOTE: Page numbers of current version may differ from previous versions.
Changes from Original (June 2009) to Revision A
Page
•
Deleted product preview device number TPS61306 from data sheet header. ..................................................................... 1
•
Deleted "Product Preview" cross reference from TPS61301 device in Available Options table. ......................................... 2
•
Added "TI" to package marking illustration example .......................................................................................................... 72
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PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS61300YFFR
DSBGA
YFF
20
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.2
2.35
0.8
4.0
8.0
Q1
TPS61300YFFT
DSBGA
YFF
20
250
180.0
8.4
2.2
2.35
0.8
4.0
8.0
Q1
TPS61301YFFR
DSBGA
YFF
20
3000
180.0
8.4
2.18
2.18
0.81
4.0
8.0
Q1
TPS61301YFFT
DSBGA
YFF
20
250
180.0
8.4
2.18
2.18
0.81
4.0
8.0
Q1
TPS61305YFFR
DSBGA
YFF
20
3000
180.0
8.4
2.18
2.18
0.81
4.0
8.0
Q1
TPS61305YFFT
DSBGA
YFF
20
250
180.0
8.4
2.18
2.18
0.81
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS61300YFFR
DSBGA
YFF
20
3000
190.5
212.7
31.8
TPS61300YFFT
DSBGA
YFF
20
250
190.5
212.7
31.8
TPS61301YFFR
DSBGA
YFF
20
3000
190.5
212.7
31.8
TPS61301YFFT
DSBGA
YFF
20
250
190.5
212.7
31.8
TPS61305YFFR
DSBGA
YFF
20
3000
190.5
212.7
31.8
TPS61305YFFT
DSBGA
YFF
20
250
190.5
212.7
31.8
Pack Materials-Page 2
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