CY7B9930V, CY7B9940V:High Speed Multifrequency PLL Clock Buffer

CY7B9930V/CY7B9940V
RoboClockII™ Junior
High-Speed Multifrequency
PLL Clock Buffer
High-Speed Multifrequency PLL Clock Buffer
Features
Functional Description
■
12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)
input/output operation
The CY7B9930V and CY7B9940V High-Speed Multifrequency
PLL Clock Buffers offer user-selectable control over system
clock functions. This multiple output clock driver provides the
system integrator with functions necessary to optimize the timing
of high performance computer or communication systems.
■
Matched pair output skew < 200 ps
■
Zero input-to-output delay
■
10 LVTTL 50% duty-cycle outputs capable of driving 50
terminated lines
■
Commercial temperature range with eight outputs at 200 MHz
■
Industrial temperature range with eight outputs at 200 MHz
■
3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot
insertable reference inputs
■
Multiply ratios of (1–6, 8, 10, 12)
■
Operation up to 12x input frequency
■
Individual output bank disable for aggressive power
management and EMI reduction
■
Output high impedance option for testing purposes
■
Fully integrated PLL with lock indicator
■
Low cycle-to-cycle jitter (<100 ps peak-peak)
■
Single 3.3V ± 10% supply
■
44-pin TQFP package
Ten configurable outputs can each drive terminated transmission
lines with impedances as low as 50 while delivering minimal and
specified output skews at LVTTL levels. The outputs are arranged
in three banks. The FB feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12. Any one of
these ten outputs can be connected to the feedback input as well
as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change over to secondary clock source, when the
primary clock source is not in operation. The reference inputs are
configurable to accommodate both LVTTL or differential
(LVPECL) inputs. The completely integrated PLL reduces jitter
and simplifies board layout.
For a complete list of related documentation, click here.
Logic Block Diagram
FBKA
LOCK
Phase
Freq.
Detector
REFA+
REFA–
REFB+
REFB–
REFSEL
Feedback Bank
FBDS0
FBDS1
3
3
VCO
Filter
FS
Output_Mode
3
3
QFA0
QFA1
Divide
Matrix
2QA0
2QA1
Bank 2
2QB0
2QB1
DIS2
1QA0
1QA1
Bank 1
1QB0
1QB1
DIS1
Cypress Semiconductor Corporation
Document Number: 38-07271 Rev. *J
Control Logic
Divide
Generator
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 3, 2016
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Contents
Logic Block Diagram Description ......................................3
Phase Frequency Detector and Filter .............................3
VCO, Control Logic, and Divide Generator ....................3
Divide Matrix ...................................................................3
Output Disable Description .............................................3
Lock Detect Output Description ......................................4
Factory Test Mode Description ......................................4
Pin Configuration ................................................................5
Pin Definitions .....................................................................6
Absolute Maximum Conditions ..........................................7
Operating Range ..................................................................7
Electrical Characteristics ....................................................7
Capacitance .........................................................................9
Thermal Resistance .............................................................9
AC Test Loads and Waveforms ..........................................9
Document Number: 38-07271 Rev. *J
Switching Characteristics ...................................................10
AC Timing Diagrams ...........................................................11
Ordering Information ...........................................................12
Ordering Code Definitions ..............................................12
Package Diagram .................................................................13
Acronyms .............................................................................14
Document Conventions ......................................................14
Units of Measure ............................................................14
Document History Page ......................................................15
Sales, Solutions, and Legal Information ...........................16
Worldwide Sales and Design Support ............................16
Products .........................................................................16
PSoC®Solutions ............................................................16
Cypress Developer Community ......................................16
Technical Support ..........................................................16
Page 2 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Logic Block Diagram Description
selected feedback input (FBKA+). This feedback bank also has
two divider function selects FBDS[0:1].
Phase Frequency Detector and Filter
The divide capabilities for each bank are shown in Table 2.
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+ or REFB–) and the FB input (FBKA). Correction
information is then generated to control the frequency of the
Voltage Controlled Oscillator (VCO). These two blocks, along
with the VCO, form a Phase-Locked Loop (PLL) that tracks the
incoming REF signal.
The RoboClockII Junior has a flexible REF input scheme.
These inputs allow the use of either differential LVPECL or single
ended LVTTL inputs. To configure as single ended LVTTL inputs,
leave the complementary pin to 1.5V), then use the other input
pin as an LVTTL input. The REF inputs are also tolerant to hot
insertion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (tMIN = tREF
(nominal reference clock period) – tCCJ (cycle-to-cycle jitter) –
tPDEV (max. period deviation)) while reacquiring lock.
VCO, Control Logic, and Divide Generator
The VCO accepts analog control inputs from the PLL filter block.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the device.
fNOM is directly related to the VCO frequency. There are two
versions of the RoboClockII Junior, a low speed device
(CY7B9930V) where fNOM ranges from 12 MHz to 100 MHz, and
a high speed device (CY7B9940V), which ranges from 24 MHz
to 200 MHz. The FS setting for each device is shown in Table 1.
The fNOM frequency is seen on “divide-by-one” outputs.
Table 1. Frequency Range Select
FS[1]
CY7B9930V
CY7B9940V
fNOM (MHz)
fNOM (MHz)
Min.
Max.
Min.
Max.
LOW
12
26
24
52
MID
24
52
48
100
HIGH
48
100
96
200[2]
Divide Matrix
The Divide Matrix is comprised of three independent banks: two
banks of clock outputs and one bank for feedback. Each clock
output bank has two pairs of low-skew, high fanout output buffers
([1:2]Q[A:B][0:1]), and an output disable (DIS[1:2]).
Table 2. Output Divider Function
Function
Selects
Output Divider Function
Bank 1
Bank 2
Feedback
Bank
FBDS1
FBDS0
LOW
LOW
/1
/1
/1
LOW
MID
/1
/1
/2
LOW
HIGH
/1
/1
/3
MID
LOW
/1
/1
/4
MID
MID
/1
/1
/5
MID
HIGH
/1
/1
/6
HIGH
LOW
/1
/1
/8
HIGH
MID
/1
/1
/10
HIGH
HIGH
/1
/1
/12
Output Disable Description
The outputs of Bank 1 and Bank 2 can be independently put into
a HOLD OFF or high impedance state. The combination of the
Output_Mode and DIS[1:2] inputs determines the clock outputs’
state for each bank. When the DIS[1:2] is LOW, the outputs of
the corresponding bank are enabled. When the DIS[1:2] is HIGH,
the outputs for that bank are disabled to a high impedance (HI-Z)
or HOLD OFF state depending on the Output_Mode input.
Table 3 defines the disabled output functions.
The HOLD OFF state is designed as a power saving feature. An
output bank is disabled to the HOLD OFF state in a maximum of
six output clock cycles from the time when the disable input
(DIS[1:2]) is HIGH. When disabled to the HOLD OFF state,
outputs are driven to a logic LOW state on its falling edge. This
ensures the output clocks are stopped without glitch. When a
bank of outputs is disabled to HI-Z state, the respective bank of
outputs go HI-Z immediately.
Table 3. DIS[1:2] Pin Functionality
OUTPUT_MODE
DIS[1:2]/FBDIS
Output Mode
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HI-Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST
The feedback bank has one pair of low-skew, high fanout output
buffers (QFA[0:1]). One of these outputs may connect to the
Notes
1. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO. fNOM always appears on an output when the output is operating in
the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
2. The maximum output frequency is 200 MHz.
Document Number: 38-07271 Rev. *J
Page 3 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit (tPD).
When in the locked state, after four or more consecutive
feedback clock cycles with phase errors, the LOCK output is
forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase errorless
feedback clock cycles are required to allow the LOCK output to
indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH, a
Watchdog circuit is implemented to indicate the out-of-lock
condition after a timeout period by deasserting LOCK LOW. This
timeout period is based upon a divided down reference clock.
This assumes that there is activity on the selected REF input. If
there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal PLL.
its internal PLL disconnected; the input level supplied to the
reference input is used in place of the PLL output. In TEST mode
the selected FB input must be tied LOW. All functions of the
device remain operational in factory test mode except the
internal PLL and output bank disables. The OUTPUT_MODE
input is designed as a static input. Dynamically toggling this input
from LOW to HIGH may temporarily cause the device to go into
factory test mode (when passing through the MID state).
Factory Test Reset
When in factory test mode (OUTPUT_MODE = MID), the device
is reset to a deterministic state by driving the DIS2 input HIGH.
When the DIS2 input is driven HIGH in factory test mode, all
clock outputs go to HI-Z; after the selected reference clock pin
has five positive transitions, all the internal finite state machines
(FSM) are set to a deterministic state. The deterministic state of
the state machines depends on the configurations of the divide
selects and frequency select input. All clock outputs stay in high
impedance mode and all FSMs stay in the deterministic state
until DIS2 is deasserted. When DIS2 is deasserted (with
OUTPUT_MODE still at MID), the device reenters factory test
mode.
Factory Test Mode Description
The device enters factory test mode when the OUTPUT_MODE
is driven to MID. In factory test mode, the device operates with
Document Number: 38-07271 Rev. *J
Page 4 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Pin Configuration
Figure 1. 44-pin TQFP pinout
VCCQ
FBKA
GND
GND
QFA1
VCCN
QFA0
GND
FBDS0
FBDS1
LOCK
44-Pin TQFP
44 43 42 41 40 39 38 37 36 35 34
GND
1
33
VCCQ
2QB1
2
32
REFA+
VCCN
3
31
REFA –
2QB0
4
30
REFSEL
GND
5
29
REFB–
GND
6
28
REFB+
2QA1
7
27
FS
VCCN
8
26
GND
2QA0
9
25
VCCQ
GND
10
24
DIS2
GND
11
23
DIS1
CY7B9930V/40V
Output_Mode
GND
1QB1
VCCN
1QB0
GND
GND
1QA1
VCCN
GND
Document Number: 38-07271 Rev. *J
1QA0
12 13 14 15 16 17 18 19 20 21 22
Page 5 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Pin Definitions
Name
I/O
Type
Description
FBKA
Input
LVTTL
Feedback Input.
REFA+, REFA–
REFB+, REFB–
Input
LVTTL/
LVDIFF
Reference Inputs: These inputs operate as either differential PECL or single ended
TTL reference inputs to the PLL. When operating as a single ended LVTTL input, leave
the complementary input must be left open.
REFSEL
Input
LVTTL
Reference Select Input: The REFSEL input controls reference input configuration.
When LOW, it uses the REFA pair as the reference input. When HIGH, it uses the REFB
pair as the reference input. This input has an internal pull down.
FS[3]
Input
3 Level
Input
Frequency Select: Set this input according to the nominal frequency (fNOM). See
Table 1.
FBDS[0:1][3]
Input
3 Level
Input
Feedback Divider Function Select. These inputs determine the function of the QFA0
and QFA1 outputs. See Table 2.
DIS[1:2]
Input
LVTTL
Output Disable: Each input controls the state of the respective output bank. When
HIGH, the output bank is disabled to the “HOLD OFF” or “HI-Z” state; the disable state
is determined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See
Table 3. These inputs each have an internal pull down.
LOCK
Output
LVTTL
PLL Lock Indicator: When HIGH, this output indicates that the internal PLL is locked
to the reference signal. When LOW, the PLL is attempting to acquire lock.
Output_Mode[3]
Input
3 Level
Input
Output Mode: This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs disable to high impedance (HI-Z). When this input is LOW, the
clock outputs disables to “HOLD OFF” mode. When in MID, the device enters factory
test mode.
QFA[0:1]
Output
LVTTL
Clock Feedback Output: This pair of clock outputs connects to the FB input. These
outputs have numerous divide options. The function is determined by the setting of the
FBDS[0:1] pins.
[1:2]Q[A:B][0:1]
Output
LVTTL
Clock Output.
VCCN
PWR
Output Buffer Power: Power supply for each output pair.
VCCQ
PWR
Internal Power: Power supply for the internal circuitry.
GND
PWR
Device Ground.
Note
3. For all tri-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
Document Number: 38-07271 Rev. *J
Page 6 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Absolute Maximum Conditions
Static discharge voltage
(MIL-STD-883, Method 3015) ...................................... >2000 V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch up current ........................................................ >±200 mA
Storage temperature 40C to +125C
Operating Range
Ambient Temperature with power applied 40C to +125C
Supply voltage to ground potential 0.5V to +4.6V
DC input voltage  0.3V to VCC+0.5V
Output current into outputs (LOW) ..................................40 mA
Range
Ambient Temperature
VCC
0 °C to +70 °C
3.3 V 10%
–40 °C to +85 °C
3.3 V 10%
Commercial
Industrial
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Unit
QFA[0:1],
[1:2]Q[A:B][0:1]
VCC = Min., IOH = –30 mA
2.4
–
V
LOCK
IOH = –2 mA, VCC = Min.
2.4
–
V
QFA[0:1],
[1:2]Q[A:B][0:1]
VCC = Min., IOL= 30 mA
–
0.5
V
LOCK
IOL= 2 mA, VCC = Min.
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
LVTTL HIGH voltage
VOL
LVTTL LOW voltage
IOZ
High impedance state leakage current
–
0.5
V
–100
100
A
Min. < VCC < Max.
2.0
VCC + 0.3
V
2.0
VCC + 0.3
V
Min. < VCC < Max.
–0.3
0.8
V
LVTTL Compatible Input Pins (FBKA, REFA±, REFB±, REFSEL, DIS[1:2])
VIH
LVTTL Input HIGH
FBKA+, REF[A:B]±
VIL
LVTTL Input LOW
FBKA+, REF[A:B]±
II
LVTTL VIN > VCC
IlH
LVTTL Input HIGH Current
REFSEL, DIS[1:2]
REFSEL, DIS[1:2]
IlL
FBKA+, REF[A:B]±
LVTTL Input LOW Current
–0.3
0.8
V
VCC = GND, VIN = 3.63V
–
100
A
FBKA+, REF[A:B]±
VCC = Max., VIN = VCC
–
500
A
REFSEL, DIS[1:2]
VIN = VCC
–
500
A
FBKA+, REF[A:B]±
VCC = Max., VIN = GND
–500
–
A
–500
–
A
Min. < VCC < Max.
0.87 × VCC
–
V
Min. < VCC < Max.
0.47 × VCC 0.53 × VCC
REFSEL, DIS[1:2]
3-Level Input Pins (FBDS[0:1], FS, Output_Mode)
VIHH
Three level input HIGH[4]
MID[4]
VIMM
Three level input
VILL
Three level input LOW[4]
Min. < VCC < Max.
IIHH
Three level input HIGH current
Three level input pins VIN = VCC
IIMM
Three level input MID current
IILL
Three level input LOW current
Three level input pins VIN = VCC/2
Three level input pins VIN = GND
V
–
0.13 × VCC
V
–
200
A
–50
50
A
–200
–
A
Note
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all data sheet limits are achieved.
Document Number: 38-07271 Rev. *J
Page 7 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Unit
400
VCC
mV
LVDIFF Input Pins (REF[A:B]±)
VDIFF
Input differential voltage
VIHHP
Highest input HIGH voltage
1.0
VCC
V
VILLP
Lowest input LOW voltage
GND
VCC – 0.4
V
VCOM
Common mode range (crossing voltage)
0.8
VCC
V
Operating Current
ICCI
Internal operating current
CY7B9930V
VCC = Max., fMAX[5]
CY7B9940V
ICCN
Output current dissipation/pair[6] CY7B9930V
CY7B9940V
VCC = Max.,
CLOAD = 25 pF,
RLOAD = 50 at VCC/2,
fMAX
–
200
mA
–
200
mA
–
40
mA
–
50
mA
Notes
5. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B9930V, fNOM = 200 MHz for CY7B9940V),
and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of
25 pF terminated to 50 at VCC/2.
Document Number: 38-07271 Rev. *J
Page 8 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Capacitance
Parameter
CIN
Description
Test Conditions
Input capacitance
Min.
Max.
Unit
–
5
pF
Test Conditions
44-pin TQFP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
50
°C/W
15
°C/W
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Thermal Resistance
Parameter [7]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveform [8]
3.3V
OUTPUT
For all other outputs
R1 = 100
CL
R2 = 100
CL < 25 pF up to 185 MHz
10 pF from 185 to 200 MHz
(Includes fixture and
probe capacitance)
For LOCK output only
R1 = 910
R2 = 910 
CL < 30 pF
R1
R2
(a) LVTTL AC Test Load
3.3V
2.0V
0.8V
GND
< 1 ns
2.0V
0.8V
< 1 ns
(b) TTL Input Test Waveform
Notes
7. These parameters are guaranteed by design and are not tested.
8. These figures are for illustration only. The actual ATE loads may vary.
Document Number: 38-07271 Rev. *J
Page 9 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Switching Characteristics
Over the Operating Range [9, 10, 11, 12, 13]
Parameter
fin
fout
CY7B9930/40V-2 CY7B9930/40V-5
Description
Clock input frequency
Clock input frequency
Unit
Min.
Max.
Min.
Max.
CY7B9930V
12
100
12
100
MHz
CY7B9940V
24
200
24
200
MHz
CY7B9930V
12
100
12
100
MHz
CY7B9940V
24
200
24
200
MHz
[14, 15]
tSKEWPR
Matched pair skew
–
185
–
185
ps
tSKEWBNK
Intrabank skew [14, 15]
–
200
–
250
ps
tSKEW0
Output-Output skew (same frequency and phase, rise to rise,
fall to fall) [14, 15]
–
250
–
550
ps
tSKEW1
Output-Output skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall) [14, 15]
–
250
–
650
ps
tCCJ1-3
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
–
150
–
150
ps PeakPeak
tCCJ4-12
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
–
100
–
100
ps PeakPeak
tPD
Propagation delay, REF to FB Rise
–250
250
–500
500
ps
tPDDELTA
Propagation delay difference between two devices [16]
–
200
200
ps
tREFpwh
REF input (pulse width HIGH)
[17]
2.0
–
2.0
–
ns
tREFpwl
REF input (pulse width LOW) [17]
2.0
–
2.0
–
ns
[18]
tr/tf
Output rise/fall time
0.15
2.0
0.15
2.0
ns
tLOCK
PLL lock time from power up
–
10
–
10
ms
tRELOCK1
PLL relock time (from same frequency, different phase) with stable
power supply
–
500
–
500
s
tRELOCK2
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply [19]
–
1000
–
1000
s
tODCV
Output duty cycle deviation from 50% [13]
–1.0
1.0
–1.0
1.0
ns
tPWH
Output HIGH time deviation from 50% [20]
–
1.5
–
1.5
ns
tPWL
Output LOW time deviation from 50%
[20]
–
2.0
–
2.0
ns
tPDEV
Period deviation when changing from reference to reference [21]
–
0.025
–
0.025
UI
1.0
10
1.0
10
ns
0.5
14
0.5
14
ns
[14, 22]
tOAZ
DIS[1:2] HIGH to output high impedance from ACTIVE
tOZA
DIS[1:2] LOW to output ACTIVE from output is high impedance [22, 23]
Notes
9. This is for non-three level inputs.
10. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF.
11. Both outputs of pair must be terminated, even if only one is being used.
12. Each package must be properly decoupled.
13. AC parameters are measured at 1.5V, unless otherwise indicated.
14. Test Load CL= 25 pF, terminated to VCC/2 with 50.
15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all
outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
16. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
17. Tested initially and after any design or process changes that may affect these parameters.
18. Rise and fall times are measured between 2.0V and 0.8V.
19. fNOM must be within the frequency range defined by the same FS state.
20. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
21. UI = Unit Interval. Examples: 1 UI is a full period. 0.1 UI is 10% of period.
22. Measured at 0.5V deviation from starting voltage.
23. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 18 MHz, 10 pF from 185 to 200 MHz.
Document Number: 38-07271 Rev. *J
Page 10 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
AC Timing Diagrams
Figure 3. AC Timing Diagrams [24]
tREFpwl
QFA0 or
[1:4]Q[A:B]0
tREFpwh
REF
t SKEWPR
t SKEWPR
t PWH
tPD
t PWL
2.0V
FB
QFA1 or
[1:4]Q[A:B]1
0.8V
tCCJ1-3,4-12
Q
[1:4]QA[0:1]
t SKEWBNK
t SKEWBNK
[1:4]QB[0:1]
REF TO DEVICE 1 and 2
tODCV
tPD
tODCV
Q
FB DEVICE1
tPDELTA
tPDELTA
t SKEW0,1
t SKEW0,1
Other Q
FB DEVICE2
Note
24. AC parameters are measured at 1.5 V, unless otherwise indicated.
Document Number: 38-07271 Rev. *J
Page 11 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Ordering Information
Propagation Delay Max Speed
(ps)
(MHz)
Ordering Code
Package Type
Operating Range
Pb-free
500
100
CY7B9930V-5AXC
44-pin TQFP
Commercial
500
100
CY7B9930V-5AXCT
44-pin TQFP – Tape and Reel
Commercial
500
200
CY7B9940V-5AXC
44-pin TQFP
Commercial
500
200
CY7B9940V-5AXCT
44-pin TQFP – Tape and Reel
250
200
CY7B9940V-2AXC
44-pin TQFP
250
200
CY7B9940V-2AXCT
44-pin TQFP – Tape and Reel
Commercial
Ordering Code Definitions
CY 7B99X0 V - A
X
C
X
X blank or T
blank = Tube; T = Tape and Reel
Temperature Range: C = Commercial
X = Pb-free
Package Type: A = 44-pin TQFP package
V = 3.3 V
Base part number: 7B99X0 = 7B9930 or 7B9940
7B9930 = 12–100 MHz I/O operation clock buffer
7B9940 = 24–200 MHz I/O operation clock buffer
Company ID: CY = Cypress
Document Number: 38-07271 Rev. *J
Page 12 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Package Diagram
Figure 4. 44-pin TQFP (10 × 10 × 1.4 mm) A44S Package Outline, 51-85064
51-85064 *G
Document Number: 38-07271 Rev. *J
Page 13 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Acronyms
Acronym
Document Conventions
Description
EMI
Electromagnetic Interference
LVPECL
Low-Voltage Positive-Referenced Emitter
Coupled Logic
LVTTL
Low Voltage Transistor-Transistor Logic
PLL
Phase-Locked Loop
TQFP
Thin Quad Flat Pack
VCO
Voltage Controlled Oscillator
Document Number: 38-07271 Rev. *J
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
MHz
megahertz
µA
microampere
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond

ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
Page 14 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Document History Page
Document Title: CY7B9930V/CY7B9940V RoboClockII™ Junior, High-Speed Multifrequency PLL Clock Buffer
Document Number: 38-07271
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
110536
12/02/01
SZV
Change from Spec number: 38-01141
Description of Change
*A
115109
7/03/02
HWT
Add 44TQFP package for both CY7B9930/40V – Industrial Operating Range
*B
128463
7/29/03
RGL
Added clock input frequency (fin) specifications in the switching characteristics
table.
Added Min. values for the clock output frequency (fout) in the switching characteristics table.
*C
1346903
8/8/07
*D
2894960
03/18/2010
KVM
Added Table of Contents
Removed part numbers CY7B9930V-5AC, CY7B9930V-5AI,
CY7B9940V-5AC, CY7B9940V-5AI, CY7B9930V-2AC, CY7B9930V-2AI and
CY7B9940V-2AI in ordering information table.
Updated package diagram
Added Sales, Solutions, and Legal Information
*E
2906750
04/07/2010
KVM
Removed inactive part from Ordering Information table.
*F
3053421
10/08/2010
CXQ
Removed inactive parts CY7B9940V-2AXI, CY7B9940V-2AXIT from Ordering
Information table. Added Ordering Code Definition.
*G
3859773
01/07/2013
AJU
Updated Ordering Information (Updated part numbers).
Updated Package Diagram:
spec 51-85064 – Changed revision from *D to *E.
*H
4177300
10/29/2013
CINM
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
*I
4570131
11/14/2014
CINM
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagram:
spec 51-85064 – Changed revision from *E to *F.
*J
5256972
05/03/2016
PSR
Added Thermal Resistance.
Updated Package Diagram:
spec 51-85064 – Changed revision from *F to *G.
Updated to new template.
Document Number: 38-07271 Rev. *J
WWZ / Update the ordering info to reflect the current status and Pb-free part numbers.
VED / ARI Implemented new template. Updated the package diagram.
Page 15 of 16
CY7B9930V/CY7B9940V
RoboClockII™ Junior
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
cypress.com/clocks
Interface
Lighting & Power Control
cypress.com/interface
cypress.com/powerpsoc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/memory
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07271 Rev. *J
RoboClock II is a trademark of Cypress Semiconductor Corporation.
Revised May 3, 2016
Page 16 of 16