SDAS032A − DECEMBER 1983 − REVISED MARCH 1985 • • • • • • Package Options Include Plastic Small Outline Packages, Both Plastic and Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Buffered 3-State Outputs Drive Bus Lines Directly Cascadable to n-Bits Eight Selectable Transceiver/Port Functions: − B to A − Register to A and/or B − Off-Line Shifts (A and B Ports in High-Impedance State) − Shifted to A and/or B Particularly Suitable for Use in Diagnostics Analysis Circuitry Serial Register Provides: − Parallel Storage of Either A or B input Data − Serial Transmission of Data from Either A or B Port − Readback Mode B to A Dependable Texas Instruments Quality and Reliability description SN54AS856 . . . JT PACKAGE SN74AS856 . . . DW OR NT PACKAGE (TOP VIEW) OEB OEA MODE A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLK SERIN B1 B2 B3 B4 B5 B6 B7 B8 Q8 SN54AS856 . . . FK PACKAGE SN74AS856 . . . FN PACKAGE (TOP VIEW) MODE OEA OEB NC VCC CLK SERIN • A1 A2 A3 NC A4 A5 A6 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 B1 B2 B3 NC B4 B5 B6 A7 A8 GND NC Q8 B8 B7 21 The ’AS856 features two 8-bit I/O ports (A1-A8 10 20 and B1-B8), an 8-bit parallel-load, serial-in, 11 19 parallel-out shift register, and control logic. With 12 13 14 15 16 17 18 these features, this device is capable of performing eight selectable transceiver or port functions, depending on the state of the three control lines OEA, OEB, and MODE. These NC − No internal connection functions include: transferring data from port A to port B or vice versa (i.e., the transceiver function), serial shifting data to either or both ports, and performing off-line shifts (with A and B ports active as transceivers in a high-impedance state). Synchronous parallel loading of the internal register can be accomplished from either port on the positive transition of the clock while serially shifting data in via the SERIN input. The ’AS856 is ideally suited for applications needing signature-analysis circuitry to enhance system verification and/or fault analysis. All serial data is shifted right. All outputs are buffer-type outputs designed specifically to drive bus lines directly and all are 3-state except for Q8, which is a totem-pole output. The SN54AS856 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74AS856 is characterized for operation from 0°C to 70°C. Copyright 1985, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2 H H H L L L L L H H H H H H H H H H H H H H H H L L L H H H L L L H H L L H H L L OEB H L ↑ ↑ L X ↑ H or L H ↑ L X ↑ H or L H ↑ L X ↑ H or L X H ↑ X ↑ H or L X X ↑ H or L X X H or L X ↑ X H or L X ↑ SERIN H or L CLOCK Z Z Z Z Z Z L H Q1 L H Q1 Z Z Z Z B1 B1 Q1 Q1 A1 L H Qn L H Qn L H Qn L H Qn A1 Q1 A1 Q1 B1 Q1 Q1 Q1 Q1 L L L L L L L L L L L L L L L L L H H H B1 Z Z Z Z Z Z Q1 Q1 Q2 Q1 Q1 Q2 Z Z Z Z B2 B2 Q2 Q2 A2 Q1 Q1 Qn Q1 Q1 Qn Q1 Q1 Qn Q1 Q1 Qn A2 Q2 A2 Q2 B2 Q2 Q2 Q2 Q2 Z Z Z Q1 Q1 Q2 Z Z Z Q1 Q1 Q2 Z Z A2 Q2 Z Z Q2 Q2 B2 Z Z Z Z Z Z Q2 Q2 Q3 Q2 Q2 Q3 Z Z Z Z B3 B3 Q3 Q3 A3 Q2 Q2 Qn Q2 Q2 Qn Q2 Q2 Qn Q2 Q2 Qn A3 Q3 A3 Q3 B3 Q3 Q3 Q3 Q3 Z Z Z Q2 Q2 Q3 Z Z Z Q2 Q2 Q3 Z Z A3 Q3 Z Z Q3 Q3 B3 Z Z Z Z Z Z Q3 Q3 Q4 Q3 Q3 Q4 Z Z Z Z B4 B4 Q4 Q4 A4 Q3 Q3 Qn Q3 Q3 Qn Q3 Q3 Qn Q3 Q3 Qn A4 Q4 A4 Q4 B4 Q4 Q4 Q4 Q4 Z Z Z Q3 Q3 Q4 Z Z Z Q3 Q3 Q4 Z Z A4 Q4 Z Z Q4 Q4 B4 Z Z Z Z Z Z Q4 Q4 Q5 Q4 Q4 Q5 Z Z Z Z B5 B5 Q5 Q5 A5 Q4 Q4 Qn Q4 Q4 Qn Q4 Q4 Qn Q4 Q4 Qn A5 Q5 A5 Q5 B5 Q5 Q5 Q5 Q5 Z Z Z Q4 Q4 Q5 Z Z Z Q4 Q4 Q5 Z Z A5 Q5 Z Z Q5 Q5 B5 Z Z Z Z Z Z Q5 Q5 Q6 Q5 Q5 Q6 Z Z Z Z B6 B6 Q6 Q6 A6 Q5 Q5 Qn Q5 Q5 Qn Q5 Q5 Qn Q5 Q5 Qn A6 Q6 A6 Q6 B6 Q6 Q6 Q6 Q6 Z Z Z Q5 Q5 Q6 Z Z Z Q5 Q5 Q6 Z Z A6 Q6 Z Z Q6 Q6 B6 Z Z Z Z Z Z Q6 Q6 Q7 Q6 Q6 Q7 Z Z Z Z B7 B7 Q7 Q7 A7 Q6 Q6 Qn Q6 Q6 Qn Q6 Q6 Qn Q6 Q6 Qn A7 Q7 A7 Q7 B7 Q7 Q7 Q7 Q7 Z Z Z Q6 Q6 Q7 Z Z Z Q6 Q6 Q7 Z Z A7 Q7 Z Z Q7 Q7 B7 Z Z Z Z Z Z Q7 Q7 Q8 Q7 Q7 Q8 Z Z Z Z B8 B8 Q8 Q8 A8 Q7 Q7 Qn Q7 Q7 Qn Q7 Q7 Qn Q7 Q7 Qn A8 Q8 A8 Q8 B8 Q8 Q8 Q8 Q8 Z Z Z Q7 Q7 Q8 Z Z Z Q7 Q7 Q8 Z Z A8 Q8 Z Z Q8 Q8 B8 Shift B To Shift A To Shift A and B To Shift A to Q Q to B A to Q A to Q B to A Feedback FUNCTION n = level of Qn(n = 1, 2 . . 8) established on most recent ↑ transition of CLK. Q1 through Q8 are the shift register outputs; only Q8 is available externally. The double inversions that take place as the data travels from port to port are ignored in this table. L H H L H L H L L L L L L L L H L L H OEA MODE MODE FUNCTION TABLE 0 SDAS032A - DECEMBER 1983 - REVISED MARCH 1985 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 SDAS032A − DECEMBER 1983 − REVISED MARCH 1985 logic symbol† 1 OEB 2 OEA 3 MODE CLK 23 22 SERIN 4 A1 (PORT CONTROLLER) EN3 EN4 M0 M1 Z2 SRG8 2 1→/C5 ≥1 Z6 Z7 6 7 1,5D 0,5D I=0 21 3 4 8,0 9,1 A2 5 Z10 Z9 ≥1 10 0,5D I=0 Z12 19 18 17 16 15 6 7 8 9 10 11 Z28 B2 Z11 11,0 12,1 A8 20 3 4 A3 A4 A5 A6 A7 B1 Z8 ≥1 28 0,5D I=0 14 3 4 Z29 Z30 29,0 30,1 13 B3 B4 B5 B6 B7 B8 Q8 Pin numbers shown are for DW, JT, and NT packages. † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 0 SDAS032A − DECEMBER 1983 − REVISED MARCH 1985 logic diagram (positive logic) OEB OEA MODE CLK SERIN 1 2 3 23 22 I=0 A1 4 1D 21 B1 C1 I=0 A2 5 1D 20 B2 C1 Four Identical Channels Not Shown Inputs/Outputs Not Shown: (6) A3 (19) B3 (7) A4 (18) B4 (8) A5 (17) B5 (9) A6 (16) B6 I=0 A7 10 1D 15 B7 C1 I=0 A8 11 1D C1 Pin numbers shown are for DW, JT, and NT packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14 13 B8 Q8 0 SDAS032A − DECEMBER 1983 − REVISED MARCH 1985 absolute maximum ratings over free-air temperature range Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range: SN54AS856 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74AS856 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C recommended operating conditions SN54AS856 VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage IOH High-level output current IOL Low-level output current fclock tw Clock frequency SN74AS856 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 0.8 −12 −15 Q8 −2 −2 A1-A8, B1-B8 32 48 Q8 20 20 0 Duration of clock pulse 45 0 11 10 A1-A8, B1-B8 SERIN 5.5 5.5 OEB, OEA, MODE 5.5 5.5 A1-A8, B1-B8 SERIN 0 0 OEB, OEA, MODE 0 0 tsu Setup time before CLK↑ th Hold-time, data after CLK↑ TA Operating free-air temperature −55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 0 V V 0.8 A1-A8, B1-B8 UNIT 50 V mA mA MHz ns ns ns 70 °C 5 0 SDAS032A − DECEMBER 1983 − REVISED MARCH 1985 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = − 18 mA IOH = − 12 mA 2 VCC = 4.5 V, VCC = 4.5 V to 5.5 V, IOH = − 15 mA IOH = − 2 mA VCC −2 except Q8 VCC = 4.5 V, VCC = 4.5 V, IOL = 32 mA IOL = 48 mA Q8 VCC = 4.5 V, IOL = 20 mA CLK and SERIN VCC = 5.5 V, VI = 7 V A1-A8, B1-B8 VCC = 5.5 V, VI = 5.5 V VCC = 5.5 V, VI = 2.7 V B1-B8 All outputs All outputs VOL OEB, OEA, MODE II MIN VCC = 4.5 V, VCC = 4.5 V, A1-A8 VOH SN54AS856 TYP† MAX TEST CONDITIONS −1.2 CLK and SERIN A1-A8, B1-B8‡ IO§ CLK and SERIN A1-A8, B1-B8‡ Except Q8 Q8 VCC = 5.5 V, VCC = 5.5 V, 2 0.25 3.3 V 0.5 0.35 VI = 0.4 V VO = 2.25 V V VCC −2 OEB, OEA, MODE IIL −1.2 UNIT 3.2 OEB, OEA, MODE IIH SN74AS856 TYP† MAX MIN 0.5 0.5 0.5 0.2 0.2 0.1 0.1 0.2 0.2 40 40 20 20 70 70 −1 −1 −0.5 −0.5 −0.5 −0.5 −30 −112 −30 −112 −20 −112 −20 −112 V mA µA mA mA ICC VCC = 5.5 V 118 200 118 200 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters III and IIL include the output currents IOZH and IOZL, respectively. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 SDAS032A − DECEMBER 1983 − REVISED MARCH 1985 switching characteristics (see Note 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, PARAMETER FROM (INPUT) TO (OUTPUT) R2 = 500 Ω, TA = MIN to MAX SN54AS856 SN74AS856 MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHZ tPLZ tPZH MAX 45 Any B port ↑MODE ↓MODE † CLK CLK MIN MAX 50 8 2 7 2 10.5 2 9.5 Any A or B 2 8.5 2 7.5 port 5 20 5 19 Any A or B 2 8.5 2 7.5 port 2 9.5 2 8 Any A or B 3 12 3 9 port 3 12 3 11 2 9 2 7.5 2 10 2 9 2 9 2 7 2 12 2 9.5 2 8 2 Any A port Any A or B port tPZL 2 11 2 † The positive transition of the MODE control will cause low-level data at the A output bus or stored in Q to be invalid for 12 ns. NOTE 1: Load circuit and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 MHz 2 Q8 OEA or OEB UNIT • DALLAS, TEXAS 75265 7 10 ns ns ns ns ns ns ns 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AS856DW OBSOLETE SOIC DW 24 TBD Call TI Call TI SN74AS856NT OBSOLETE PDIP NT 24 TBD Call TI Call TI SN74AS856NT OBSOLETE PDIP NT 24 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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