Preliminary Datasheet RJE0617JSP R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 –60V, –1.5A, P Channel Thermal FET Power Switching Description This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of high junction temperature like applying over power consumption, over current etc.. Features • • • • • • • Logic level operation (3 V Gate drive). Built-in the over temperature shut-down circuit. High endurance capability against to the short circuit. Hysteresis type shut down operation. High density mounting. Built-in the current limitation circuit. Power supply voltage applies 12 V. Outline RENESAS Package code: PRSP0008DD-D (Package name: SOP-8 (FP-8DAV)) 8 7 65 7 3 1 2 5 6 4 2 Latch Circuit 4 Current Limitation Circuit Gate Resistor Temperature Sensing Circuit 8 Gate Resistor Gate Shut-down Circuit MOS1 Temperature Sensing Circuit 1 Latch Circuit MOS2 Current Limitation Circuit 1, 3 Source 2, 4 Gate 5, 6, 7, 8 Drain Gate Shut-down Circuit 3 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings –60 Drain to source voltage VDSS –16 Gate to source voltage VGSS 2.5 Gate to source voltage VGSS –1.5 Drain current ID Note4 –1.5 Body-drain diode reverse drain current IDR –1.5 Avalanche current IAP Note 3 9.6 Avalanche energy EAR Note 3 1 Channel dissipation Pch Note 1 1.5 Channel dissipation Pch Note 2 150 Channel temperature Tch Storage temperature Tstg –55 to +150 Notes: 1. 1 Drive operation : When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s 2. 2 Drive operation : When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s 3. Tch = 25°C, Rg ≥ 50 Ω 4. It provides by the current limitation lower bound value. R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 Unit V V V A A A mJ W W °C °C Page 1 of 7 RJE0617JSP Preliminary Typical Operation Characteristics (Ta = 25°C) Item Input voltage Input current (Gate non shut down) Input current (Gate shut down) Shut down temperature Return temperature Gate operation voltage Drain current (Current limitation value) Notes; 5. Pulse test Symbol VIH VIL IIH1 IIH2 IIL IIH(sd)1 IIH(sd)2 Tsd Thr Vop ID limt Min –3 — — — — — — — — –3 Typ — — — — — –0.8 –0.35 175 105 — Max — –1.2 –100 –50 –10 — — — — –12 –1.5 — — Unit V V µA µA µA mA mA °C °C V A Test Conditions Vi = –8 V, VDS = 0 Vi = –3.5 V, VDS = 0 Vi = –1.2 V, VDS = 0 Vi = –8 V, VDS = 0 Vi = –3.5 V, VDS = 0 Channel temperature Channel temperature VGS = –12 V, VDS = –10 V Note 5 Electrical Characteristics (Ta = 25°C) Item Drain current Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Input current (shut down) Zero gate voltage drain current Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance Output capacitance Symbol ID ID ID ID V(BR)DSS Min –1.5 — –1.5 –0.8 –60 Typ — — — — — Max –12 –40 — — — Unit A mA A V(BR)GSS V(BR)GSS IGSS IGSS IGSS IGSS IGS(OP) IGS(OP) IDSS IDSS –16 2.5 — — — — — — — — — — — — — — –0.8 –0.35 — — — — –100 –50 –1 100 — — –10 –10 V V μA μA μA μA mA mA μA μA VGS(off) |yfs| RDS(on) RDS(on) RDS(on) Coss –2.2 1.5 — — — — — 2.7 445 363 272 213 –3.4 — 800 425 350 — V S mΩ mΩ mΩ pF Turn-on delay time td(on) — 0.9 — Rise time tr — 3.4 — Turn-off delay time td(off) — 3.2 — Fall time tf — 6.3 — Body-drain diode forward voltage VDF — –0.8 — Body-drain diode reverse trr — 70 — recovery time Over load shut down — 5.4 — tos operation time Note 8 Notes: 6. Pulse test 7. Including the junction temperature rise of the over loaded condition. R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 V μs μs μs μs V ns ms Test Conditions VGS = –3.5 V, VDS = –10 V VGS = –1.2 V, VDS = –10 V VGS = –12 V, VDS = –10 V Note 7 ID = –10 mA, VGS = 0 IG = –800 μA, VDS = 0 IG = 100 μA, VDS = 0 VGS = –8 V, VDS = 0 VGS = –3.5 V, VDS = 0 VGS = –1.2 V, VDS = 0 VGS = 2.4 V, VDS = 0 VGS = –8 V, VDS = 0 VGS = –3.5 V, VDS = 0 VDS = –60 V, VGS = 0 VDS = –48 V, VGS = 0 Ta = 125°C VDS = –10 V, ID = –1 mA ID = –0.75 A, VGS = –10 V Note 7 ID = –0.4 A, VGS = –3V Note 7 ID = –0.75 A, VGS = –4 V Note 7 ID = –0.75 A, VGS = –10 V Note 7 VDS = –10 V, VGS = 0, f = 1MHz VGS = –10 V, ID= –0.75 A, RL = 40 Ω IF = –1.5 A, VGS = 0 IF = –1.5 A, VGS = 0 diF/dt = 50 A/μs VGS = –5 V, VDD = –16 V Page 2 of 7 RJE0617JSP Preliminary Main Characteristics Power vs. Temperature Derating Maximum Safe Operation Area −100 3.0 riv 1.0 2D er rive Op era rO tio per atio n 50 D C 100 150 ra tio n −0.1 −0.01 −0.01 200 O pe n 0 0 −1 s 1D −10 m 2.0 Thermal shut down operation area Ta = 25°C 1 shot Pulse 1 Driver Operation Drain Current ID (A) Test condition. When using the glass epoxy board. (FR4 40 x 40 x 1.6 mm), (PW ≤ 10s) 1 Channel Dissipation Pch (W) 4.0 PW Operation in this area is limited RDS(on) ≤ −0.1 −10 −1 10 sN ot e7 −100 Drain to Source Voltage VDS (V) Ambient Temperature Ta (°C) Note 7: When using the glass epoxy board. (FR4 40 x 40 x 1.6 mm) Typical Output Characteristics Typical Transfer Characteristics −1.5 −5 −4 V −4 −8 V −3 VDS = −10 V Pulse Test −3.5 V −10 V VGS = −3 V −2 −1 Drain Current ID (A) Drain Current ID (A) −6 V −5 V −1.0 −0.5 Tc = 150°C 25°C −40°C Pulse Test −2 −4 −6 −8 −10 −1 −2 −3 −4 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain Source Saturation Voltage vs. Gate to Source Voltage Static Drain to Source On State Resistance vs. Drain Current −500 Pulse Test −400 −300 −0.75 A −200 −0.4 A −100 0 0 ID = −0.2 A −2 −4 −6 −8 −10 −12 Gate to Source Voltage VGS (V) R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 Static Drain to Source On State Resistance RDS(on) (mΩ) Drain to Source Saturation Voltage VDS(on) (mV) 0 0 0 10000 Pulse Test 1000 VGS = −3 V −4 V −10 V 100 10 −0.1 −1 −10 Drain Current ID (A) Page 3 of 7 Preliminary Body-Drain Diode Reverse Recovery Time Static Drain to Source On State Resistance vs. Temperature 800 Pulse Test −0.75 A 600 ID = −1.5 A −0.4 A VGS = −3 V −0.4 A 400 −0.4 A −0.75 A 200 −4 V ID = −1.5 A −10 V 0 −50 −25 0 25 50 Reverse Recovery Time trr (ns) Static Drain to Source On State Resistance RDS(on) (mΩ) RJE0617JSP 75 100 125 150 −1 −10 Typical Capacitance vs. Drain to Source Voltage 1000 Capacitance C (pF) Switching Time t (μs) 10 −0.1 Switching Characteristics tf tr td(off) 1 td(on) VGS = −10 V, VDD = −30 V PW = 300 μs, duty ≤ 1 % 0.1 −0.1 −1 VGS = 0 f = 1 MHz Coss 100 10 −0 −10 −10 −20 −30 −40 −50 −60 Drain to Source Voltage VDS (V) Reverse Drain Current vs. Source to Drain Voltage Gate to Source Voltage vs. Shutdown Time of Load-Short Test Pulse Test –5 V VGS = 0 V –0.5 –0.5 –1.0 –1.5 Source to Drain Voltage VSD (V) R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 Gate to Source Voltage VGS (V) Drain Current ID (A) –1.5 Reverse Drain Current IDR (A) di / dt = 50 A /μs VGS = 0 Reverse Drain Current IDR (A) 10 0 100 Case Temperature Tc (°C) 100 –1.0 1000 −16 −14 −12 −10 VDD = −16 V −8 −6 −4 −2 0 0.1 1 10 100 Shutdown Time of Load-Short Test Pw (ms) Page 4 of 7 RJE0617JSP Preliminary Shutdown Case Temperature vs. Gate to Source Voltage Shutdown Case Temperature Tc ( °C) Forward transfer admittance |yfs| (S) Forward transfer admittance vs. Drain Current 10 Ta = –40°C 25°C 1 150°C VDS = –10 V Pulse Test 0.1 –0.1 –1 –10 200 180 160 140 120 100 0 ID = –0.2 A Gate to Source Voltage V GS (V) Drain Current ID (A) Normalized Transient Thermal Impedance vs. Pulse Width (1 Drive Operation) 10 1 D=1 0.5 0.1 0.1 0.05 0.2 0.02 0.01 0.01 When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) e uls tp o sh 0.001 PDM 1 D= PW T PW T 0.0001 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (S) 10 1 Normalized Transient Thermal Impedance vs. Pulse Width (Operatioon of 2 devices; allowable value per device) D=1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) 0.01 0.001 t ho lse PDM pu D= 1s PW T PW T 0.0001 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (S) R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 Page 5 of 7 RJE0617JSP Preliminary Switching Time Test Circuit Waveform Vout Monitor Vin Monitor Vin 10% D.U.T. Rg RL 90% VDD = –30 V Vin –10 V Vout 10% td(on) tr Avalanche Test Circuit VDS Monitor 90% 90% 10% td(off) tf Avalanche Waveform L EAR = 1 2 VDSS L · IAP2 · VDSS – VDD IAP Monitor Rg V(BR)DSS D. U. T VDD IAP VDS Vin –10 V 50 Ω ID 0 R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 VDD Page 6 of 7 RJE0617JSP Preliminary Package Dimensions Package Name SOP-8 JEITA Package Code P-SOP8-3.95 × 4.9-1.27 RENESAS Code PRSP0008DD-D MASS[Typ.] 0.085g F *1 D Previous Code FP-8DAV bp 1 c *2 E Index mark HE 5 8 4 Z Terminal cross section (Ni/Pd/Au plating) *3 b p x M NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. e Reference Symbol A1 A L1 L y Detail F D E A2 A1 A bp b1 c c1 HE e x y Z L L1 Dimension in Millimeters Min Nom Max 4.90 5.3 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.1 0.75 0.40 0.60 1.27 1.08 Ordering Information Orderable Part Number RJE0617JSP-00-J0 Note: Quantity 2500 pcs/reel Shipping Container Taping The symbol of 2nd "-" is occasionally presented as "#". R07DS1070EJ0200 Rev.2.00 Jun 06, 2013 Page 7 of 7 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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