NILMS4501N Power MOSFET with Current Mirror FET 24 V, 9.5 A, N−Channel, ESD Protected, 1:250 Current Mirror, SO−8 Leadless http://onsemi.com N−Channel MOSFET with 1:250 current mirror device utilizing the latest ON Semiconductor technology to achieve low figure of merit while keeping a high accuracy in the linear region. This device takes advantage of the latest leadless QFN package to improve thermal transfer. VDSS RDS(on) Typ ID MAX 24 V 12 mW @ 4.5 V 9.5 A N−Channel with Current Mirror FET Drain Features • • • • • Current Sense MOSFET "15% Current Mirror Accuracy ESD Protected on the Main and the Mirror MOSFET Low Gate Charge Pb−Free Package is Available* Main Gate Applications • DC−DC Converters • Voltage Regulator Modules • Small DC Motor Controls Sense Source MARKING DIAGRAM 4501N AYWW G PLLP4 CASE 508AA 4501N A Y WW G = Device Code = Assembly Location = Year = Work Week = Pb−Free Package PIN CONNECTIONS Sense (1) Drain (4) Source (2) Gate (3) (Bottom View) ORDERING INFORMATION Device NILMS4501NR2 NILMS4501NR2G *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 May, 2006 − Rev. 4 1 Package Shipping† PLLP4 2500/Tape & Reel PLLP4 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NILMS4501N/D NILMS4501N MAIN MOSFET MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 24 V Gate−to−Source Voltage VGS "10 V ID ID Adc Adc Apk W Drain Current (Note 1) Continuous @ TA = 25°C Continuous @ TA = 100°C Pulsed (tpv10 s) IDM 9.5 6.7 14 Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) PD PD 2.7 1.4 RqJA RqJA RqJA 55 110 25 TJ, TSTG −55 to 175 °C EAS 50 mJ ESDHBM CMD 4000 2000 °C/W Thermal Resistance Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Junction−to−Ambient (tpv10 s) (Note 3) Operating Junction and Storage Temperature Single Pulse Drain−to−Source Avalanche (VDD = 24 V, VGS = 10 V, IL = 9.5 A, L = 1.0 mH, RG = 25 W) Electrostatic Discharge Capability Human Body Model Charged Device Model V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0821 in sq). 3. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces) and 200 LFM airflow. MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 24 − 29 23 − − V mV/°C − − − 0.05 1.0 30 1.0 100 100 − − 40 1.3 100 10 nA mA 1.1 − 1.60 −5.0 2.0 − V mV/°C − − − 9.0 12 14 13 17 20 − − − 12 16 18 16 20 24 OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 V, ID = 250 mA) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 24 V, VGS = 0 V) (VDS = 24 V, VGS = 0 V, TJ = 125°C) (VDS = 24 V, VGS = 0 V, TJ = 175°C) IDSS Gate−Body Leakage Current (VGS = 3.0 V, VDS = 0 V) (VGS = 9.0 V, VDS = 0 V) IGSS mA ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 mA) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 4) (VGS = 10 V, ID = 6.0 A, TJ @ 25°C) (VGS = 10 V, ID = 6.0 A, TJ @ 125°C) (VGS = 10 V, ID = 6.0 A, TJ @ 175°C) RDS(on) Static Drain−to−Source On−Resistance (Note 4) (VGS = 4.5 V, ID = 6.0 A, TJ @ 25°C) (VGS = 4.5 V, ID = 6.0 A, TJ @ 125°C) (VGS = 4.5 V, ID = 6.0 A, TJ @ 175°C) RDS(on) mW mW Main/Mirror MOSFET Current Ratio (VGS = 4.5 V, ID = 1.0 A) (VGS = 4.5 V, ID = 1.0 A, TA = 175°C) IRAT 212 − 250 268 287 − − Forward Transconductance (Note 4) (VDS = 6.0 V, ID = 6.0 A) gFS 15 23 − Mhos 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. http://onsemi.com 2 NILMS4501N MAIN MOSFET ELECTRICAL CHARACTERISTICS (continued) (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Ciss − 1380 1500 pF Coss − 870 1000 Crss − 275 350 td(on) − 12 14 tr − 15 18 td(off) − 17 20 tf − 6.0 8.0 td(on) − 8.5 11 tr − 15 20 td(off) − 22.5 27 tf − 6.5 9.0 QT − 11 14 QG(th) − 1.7 2.5 Qgs − 3.5 4.5 Qgd − 3.6 4.3 QT − 23.5 25 QG(th) − 4.4 5.5 Qgs − 5.6 10 Qgd − 2.5 7.0 VSD − − 0.80 0.57 1.1 − V trr − 42 55 ns ta − 19.5 25 tb − 22.5 30 QRR − 0.042 0.06 DYNAMIC CHARACTERISTICS (Note 6) Input Capacitance Output Capacitance (VDS = 6.0 V, VGS = 0 V, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 6.0 V, ID = 2.0 A, VGS = 4.5 V, RG = 2.5 W) Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 6.0 V, ID = 2.0 A, VGS = 10 V, RG = 2.5 W) Fall Time Gate Charge (VDS = 6.0 V, ID = 2.0 A, VGS = 4.5 V) Gate Charge (VDS = 6.0 V, ID = 2.0 A, VGS = 10 V) ns ns nC nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Notes 5 & 6) (IS = 6.0 A, VGS = 0 V) (IS = 6.0 A, VGS = 0 V, TJ = 175°C) Reverse Recovery Time (Note 6) (IS = 3.0 A, VGS = 0 V, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge (Note 6) 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 mC NILMS4501N TYPICAL ELECTRICAL CHARACTERISTICS 25 VGS = 10 V 4.5 V 5 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 6 2.6 V 3.0 V 4 2.8 V 3 2.4 V 2 1 0 2.2 V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 20 2.8 V 10 2.6 V 5 2.4 V 2.2 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) VDS =10 V 15 TJ = 125°C TJ = 25°C TJ = 175°C TJ = − 55°C 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.5 1 1.5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4 0.024 0.022 VGS = 4.5 V 0.020 TJ = 125°C TJ = 25°C 0.012 0.010 0.008 0.006 0.004 0.002 0 TJ = −55°C 5 0 TJ = 125°C 0.012 0.010 TJ = 25°C 0.008 0.006 TJ = −55°C 0.004 0.002 0 0 5 10 15 ID, DRAIN CURRENT (AMPS) 20 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 175°C 0.014 10 15 20 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance versus Drain Current and Temperature 0.018 0.016 TJ = 175°C 0.018 0.016 0.014 Figure 3. Transfer Characteristics VGS = 10 V 2 Figure 2. On−Region Characteristics 20 5 3.0 V 15 Figure 1. On−Region Characteristics 10 3.2 V 4.0 V 0 1 3.6 V VGS = 10 V 4.6 V 0.03 ID = 10 A 0.025 0.02 TJ = 175°C 0.015 TJ = 125°C TJ = 25°C 0.01 TJ = −55°C 0.005 2 Figure 5. On−Resistance versus Drain Current and Temperature 3 5 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 6. On−Resistance versus Gate Voltage and Temperature http://onsemi.com 4 10 NILMS4501N 1E6 2.5 VGS = 0 V VGS = 10 V ID = 3 A 1E5 2.0 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TYPICAL ELECTRICAL CHARACTERISTICS TJ = 175°C 1000 1.5 1.0 100 TJ = 125°C 10 1.0 0.5 TJ = 25°C 0.1 0 −50 100 50 0 150 0.01 200 0 TJ, JUNCTION TEMPERATURE (°C) IRAT, MAIN/MIRROR MOSFET CURRENT RATIO IRAT, MAIN/MIRROR MOSFET CURRENT RATIO TJ = −55°C TJ = 25°C 1600 1400 TJ = 125°C 1200 1000 TJ = 175°C 800 600 400 200 0 0 2 4 6 8 10 12 14 16 RSENSE, EXTERNAL RESISTOR VALUE ON SENSE PIN (W) 450 25°C 1000 125°C 500 0.005 0.01 0.015 TJ = −55°C TJ = 25°C 400 TJ = 125°C 350 300 TJ = 175°C 250 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) IRAT, MAIN/MIRROR MOSFET CURRENT RATIO IRAT, MAIN/MIRROR MOSFET CURRENT RATIO ID = 1 A VSENSE = 0 V VGS = 4.5 V 1500 T = 175°C 0 J −0.01 −0.005 0 ID = 1 A VSENSE = 0 V VSOURCE = 0 V Figure 10. Current Ratio versus VGS 2500 TJ = −55°C 25 500 Figure 9. Current Ratio versus RSENSE 2000 20 Figure 8. Drain−To−Source Leakage Current versus Voltage 2000 1800 15 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. On−Resistance Variation with Temperature ID = 1 A VGS = 4.5 V 5 0.02 0.025 0.03 VSOURCE, VOLTAGE DROP FROM SOURCE PIN TO GROUND (V) 2000 −55°C ID = 1 A VSOURCE = 0 V 1600 VGS = 4.5 V 1800 25°C 125°C 175°C 1400 1200 1000 800 600 400 200 0 −0.01 −0.005 0 0.005 0.01 0.015 VSENSE, VOLTAGE DROP FROM SENSE PIN TO GROUND (V) Figure 11. IRATIO versus VSOURCE Figure 12. Current Ratio versus VSENSE http://onsemi.com 5 0.02 NILMS4501N POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 2800 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 2400 2000 Ciss 1600 Ciss 1200 Crss 800 Coss 400 Crss 0 10 5 0 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 13. Capacitance Variation http://onsemi.com 6 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NILMS4501N 30 12 QT 10 25 VDS VGS 8 20 6 15 10 4 Q1 Q2 2 0 5 ID = 2 A TJ = 25°C 0 5 10 15 20 QG, TOTAL GATE CHARGE (nC) 25 Figure 14. Gate−To−Source and Drain−To−Source Voltage versus Total Charge DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 7 NILMS4501N IS, SOURCE CURRENT (AMPS) 20 16 VGS = 0 V TJ = 25°C 12 8 4 0 0.4 0.5 0.6 0.7 0.8 0.9 1 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 16. Diode Forward Voltage versus Current SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the ID, DRAIN CURRENT (AMPS) 1000 Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max. 100 VGS = 10 V SINGLE PULSE TC = 25°C 10 ms 10 100 ms 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 ms dc 10 100 60 ID = 9.5 A 50 40 30 20 10 0 25 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 17. Maximum Rated Forward Biased Safe Operating Area Figure 18. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 8 NILMS4501N PACKAGE DIMENSIONS PLLP4 CASE 508AA−01 ISSUE O PIN 1 LOCATION A D B E 2X 0.15 C 2X 0.15 C É ÉÇ É É Ç ÉÇ ÉÇ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOLERANCES: $0.10 MM. TOP VIEW 0.10 C 0.08 C A3 ÇÉÇÉÉÉÉ ÉÉÉÉÉ SIDE VIEW H e 2X G MILLIMETERS MIN MAX 1.750 1.950 0.000 0.050 0.254 REF 0.500 0.700 6.200 BSC 3.979 4.179 5.200 BSC 4.087 4.287 1.905 BSC 1.860 1.880 0.500 0.700 0.379 REF 0.635 REF 0.507 REF 0.404 REF 0.507 REF A1 C SEATING PLANE H2 ÉÇÇÇÇ ÉÇÇÇÇ ÉÇÇÇÇ ÉÇÇÇÇ H1 F J A DIM A A1 A3 B D D1 E E1 e F G H H1 H2 J J1 B D1 E1 J1 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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