TI TPS1101PWLE

TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
D
D
D
D
D
D
D
Low rDS(on) . . . 0.09 Ω Typ at VGS = – 10 V
3 V Compatible
Requires No External VCC
TTL and CMOS Compatible Inputs
VGS(th) = – 1.5 V Max
Available in Ultrathin TSSOP Package (PW)
ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015
D PACKAGE
(TOP VIEW)
SOURCE
SOURCE
SOURCE
GATE
1
8
2
7
3
6
4
5
DRAIN
DRAIN
DRAIN
DRAIN
D PACKAGE
description
The TPS1101 is a single, low-rDS(on), P-channel,
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of the
Texas Instruments LinBiCMOS process. With a
maximum VGS(th) of – 1.5 V and an IDSS of only
0.5 µA, the TPS1101 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low rDS(on) and excellent ac
characteristics (rise time 5.5 ns typical) of the
TPS1101 make it the logical choice for
low-voltage switching applications such as power
switches for pulse-width-modulated (PWM)
controllers or motor/bridge drivers.
PW PACKAGE
PW PACKAGE
(TOP VIEW)
NC
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
GATE
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
NC
The ultrathin thin shrink small-outline package or
TSSOP (PW) version fits in height-restricted
places where other P-channel MOSFETs cannot.
The size advantage is especially important where
board height restrictions do not allow for an
small-outline integrated circuit (SOIC) package.
NC – No internal connection
Such applications include notebook computers,
personal digital assistants (PDAs), cellular
telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other
P-channel MOSFETs in SOIC packages.
AVAILABLE OPTIONS
PACKAGED DEVICES†
TJ
SMALL OUTLINE
(D)
TSSOP
(PW)
CHIP FORM
(Y)
– 40°C to 150°C
TPS1101D
TPS1101PWLE
TPS1101Y
† The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1101DR). The PW package is only available left-end taped and reeled (indicated by
the LE suffix on the device type; e.g., TPS1101PWLE). The chip form is tested at 25°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
schematic
SOURCE
ESDProtection
Circuitry
GATE
DRAIN
NOTE A: For all applications, all source terminals should be
connected and all drain terminals should be connected.
TPS1101Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1101. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(8)
(7)
(6)
(5)
SOURCE
SOURCE
SOURCE
GATE
(1)
(8)
(2)
(7)
(3)
TPS1100Y
(4)
(6)
(5)
DRAIN
DRAIN
DRAIN
DRAIN
80
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%
(1)
ALL DIMENSIONS ARE IN MILS
(2)
(3)
(4)
92
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
UNIT
Drain-to-source voltage, VDS
– 15
Gate-to-source voltage, VGS
2 or – 15
D package
TA = 25°C
TA = 125°C
± 0.62
PW package
TA = 25°C
TA = 125°C
± 0.61
D package
TA = 25°C
TA = 125°C
± 0.88
PW package
TA = 25°C
TA = 125°C
± 0.86
D package
TA = 25°C
TA = 125°C
± 1.52
PW package
TA = 25°C
TA = 125°C
± 1.44
D package
TA = 25°C
TA = 125°C
± 2.30
PW package
TA = 25°C
TA = 125°C
± 2.18
VGS = – 2.7
27V
VGS = – 3 V
Continuous drain current (TJ = 150°C)
150°C), ID‡
45V
VGS = – 4.5
VGS = – 10 V
V
V
± 0.39
± 0.38
± 0.47
± 0.45
A
± 0.71
± 0.67
± 1.04
± 0.98
± 10
A
– 1.1
A
Storage temperature range, Tstg
– 55 to 150
°C
Operating junction temperature range, TJ
– 40 to 150
°C
Operating free-air temperature range, TA
– 40 to 125
°C
Pulsed drain current, ID‡
TA = 25°C
TA = 25°C
Continuous source current (diode conduction), IS
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/ W for the D package and RθJA = 176°C/ W for the PW package.
These devices are mounted on an FR4 board with no special thermal considerations.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
791 mW
6.33 mW/°C
506 mW
411 mW
158 mW
PW
710 mW
5.68 mW/°C
454 mW
369 mW
142 mW
‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/ W for the D package and RθJA = 176°C/ W
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
electrical characteristics at TJ = 25°C (unless otherwise noted)
static
PARAMETER
VGS(th)
Gate-to-source
threshold voltage
VDS = VGS,
ID = – 250 µA
VSD
Source-to-drain voltage
(diode-forward voltage)†
IS = – 1 A,
VGS = 0 V
IGSS
Reverse gate current,
drain short circuited to
source
VDS = 0 V,
VGS = – 12 V
IDSS
Zero-gate-voltage
g
g drain
current
VDS = – 12 V
V,
VGS = 0 V
drain-to-source
Static drain
to source
on-state resistance†
VGS = – 10 V
VGS = – 4.5 V
VGS = – 3 V
ID = – 2.5 A
ID = – 1.5 A
rDS(
DS(on))
VGS = – 2.7 V
Forward
transconductance†
gfs
TPS1101
TEST CONDITIONS
VDS = – 10 V,
TPS1101Y
MIN
TYP
MAX
–1
– 1.25
– 1.5
MIN
– 1.04
TYP
MAX
– 1.25
V
– 1.04
V
± 100
TJ = 25°C
TJ = 125°C
nA
– 0.5
µA
– 10
90
ID = – 0
0.5
5A
ID = – 2 A
UNIT
90
134
190
134
198
310
198
232
400
232
4.3
mΩ
4.3
S
† Pulse test: pulse duration ≤ 300 µs, duty cycle ≤ 2%
dynamic
PARAMETER
TPS1101, TPS1101Y
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Qg
Total gate charge
Qgs
Gate-to-source charge
Qgd
Gate-to-drain charge
2.6
td(on)
td(off)
Turn-on delay time
6.5
ns
19
ns
tr
tf
Rise time
trr(SD)
Source-to-drain reverse recovery time
4
11.25
VDS = – 10 V,
Turn-off delay time
VDD = – 10 V,,
RG = 6 Ω,
VGS = – 10 V,
RL = 10 Ω,,
See Figures 1 and 2
Fall time
ID = – 1 A
ID = – 1 A,,
1.5
5.5
13
IF = 5.3 A,
POST OFFICE BOX 655303
di/dt = 100 A/µs
• DALLAS, TEXAS 75265
nC
16
ns
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
VGS
90%
RL
VDS
VGS
–
+
VDD
RG
0V
10%
DUT
– 10 V
VDS
td(on)
td(off)
tr
Figure 1. Switching-Time Test Circuit
tf
Figure 2. Switching-Time Waveforms
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Drain current
vs Drain-to-source voltage
3
Drain current
vs Gate-to-source voltage
4
Static drain-to-source on-state resistance
vs Drain current
5
Capacitance
vs Drain-to-source voltage
6
Static drain-to-source on-state resistance (normalized)
vs Junction temperature
7
Source-to-drain diode current
vs Source-to-drain voltage
8
Static drain-to-source on-state resistance
vs Gate-to-source voltage
9
Gate-to-source threshold voltage
vs Junction temperature
10
Gate-to-source voltage
vs Gate charge
11
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
– 10
– 10
VGS = – 8 V
–9
VDS = – 10 V
VGS = – 5 V
TJ = 25°C
–8
VGS = – 4 V
I D – Drain Current – A
I D – Drain Current – A
–8
–7
VGS = – 3 V
–6
–5
ÁÁ
ÁÁ
–3
VGS = – 2 V
TJ = 150°C
–6
ÁÁ
ÁÁ
–4
–2
TJ = – 40°C
–4
–2
–1
TJ = 25°C
0
0
0
– 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10
0
–1
VDS – Drain-to-Source Voltage – V
–3
Figure 4
CAPACITANCE†
vs
DRAIN-TO-SOURCE VOLTAGE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
800
0.5
TJ = 25°C
700
C – Capacitance – pF
0.3
VGS = – 2.7 V
0.2
VGS = – 3 V
VGS = – 4.5 V
600
500
Coss
400
300
0.1
VGS = – 10 V
VGS = 0 V
f = 1 MHz
TJ = 25°C
Ciss†
0.4
0
– 0.1
200
Crss‡
100
–1
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 –10 –11 –12
– 10
ID – Drain Current – A
VDS – Drain-to-Source Voltage – V
+ Cgs ) Cgd, Cds(shorted)
C gs C
gd
‡ C
rss + C gd, C oss + C ds ) C ) C
gs
† C
Figure 5
iss
gd
Figure 6
6
–5
–4
VGS – Gate-to-Source Voltage – V
Figure 3
r DS(on) – Static Drain-to-Source On-State
Resistance – Ω
–2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
≈ C
ds
) Cgd
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE (NORMALIZED)
vs
JUNCTION TEMPERATURE
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
– 10
1.5
Pulse Test
I SD – Source-to-Drain Diode Current – A
On-State Resistance (normalized)
r DS(on) – Static Drain-to-Source
1.4
VGS = – 10 V
ID = – 1A
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
– 50
0
50
100
TJ – Junction Temperature – °C
TJ = 150°C
TJ = – 40°C
– 0.1
– 0.1
150
– 0.3
– 0.5
– 0.7
– 0.9
– 1.1
VSD – Source-to-Drain Voltage – V
Figure 7
ID = – 1 A
TJ = 25°C
0.4
0.3
0.2
0.1
–5
–7
–9
– 11
– 13
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VGS(th) – Gate-to-Source Threshold Voltage – V
r DS(on) – Static Drain-to-Source On-State
Resistance – Ω
0.5
–3
– 1.3
Figure 8
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
GATE-TO-SOURCE VOLTAGE
0
–1
TJ = 25°C
–1
– 1.5
ID = – 250 µA
– 1.4
– 1.3
– 1.2
– 1.1
ÁÁ
ÁÁ
ÁÁ
– 15
–1
– 0.9
– 50
0
50
100
150
TJ – Junction Temperature – °C
VGS – Gate-to-Source Voltage – V
Figure 9
Figure 10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
VGS – Gate-to-Source Voltage – V
– 10
VDS = – 10 V
ID = – 1 A
TJ = 25°C
–8
–6
–4
–2
0
0
2
4
6
8
10
Qg – Gate Charge – nC
Figure 11
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
12
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
THERMAL INFORMATION
TRANSIENT JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
vs
PULSE DURATION
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
– 100
100
Single Pulse
See Note A
I D – Drain Current – A
– 10
ZθJA – Transient Junction-to-Ambient
Thermal Impedance – °C/W
Single Pulse
See Note A
0.001 s
0.01 s
–1
0.1 s
1s
10 s
– 0.1
DC
TJ = 150°C
TA = 25°C
– 0.01
– 0.1
–1
– 10
– 100
VDS – Drain-to-Source Voltage – V
NOTE A: Values are for the D package and are
FR4-board-mounted only.
10
1
0.1
0.001
0.01
0.1
1
tw – Pulse Duration – s
NOTE A: Values are for the D package and
FR4-board-mounted only.
10
are
Figure 13
Figure 12
APPLICATION INFORMATION
3 V or 5 V
5V
Microcontroller
Driver
Load
Figure 14. Notebook Load Management
POST OFFICE BOX 655303
Microcontroller
Charge
Pump
–4 V
GaAs FET
Amplifier
Figure 15. Cellular Phone Output Drive
• DALLAS, TEXAS 75265
9
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS1101D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS1101DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS1101DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS1101DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS1101PWLE
OBSOLETE
TSSOP
PW
16
TPS1101PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS1101PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS1101DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPS1101PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS1101DR
SOIC
D
8
2500
340.5
338.1
20.6
TPS1101PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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