TI TPIC3322L

SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
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Low rDS(on) . . . 0.6 Ω Typ
High-Voltage Outputs . . . 60 V
Pulsed Current . . . 2.25 A Per Channel
Fast Commutation Speed
Direct Logic-Level Interface
D PACKAGE
(TOP VIEW)
SOURCE1
GATE2
SOURCE2
SOURCE3
1
8
2
7
3
6
4
5
GATE1
GND
DRAIN
GATE3
description
The TPIC3322L is a monolithic logic-level power DMOS transistor array that consists of three isolated
N-channel enhancement-mode DMOS transistors configured with a common drain and open sources.
The TPIC3322L is offered in a standard 8-pin small-outline surface-mount (D) package and is characterized for
operation over the case temperature range of − 40°C to 125°C.
schematic diagram
DRAIN
6
Q1
GATE1
8
Q2
Z1
GATE2
1
SOURCE1
Q3
2
Z2
GATE3
3
SOURCE2
5
Z3
4
SOURCE3
D1
7
GND
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Gate-to-source voltage, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Continuous drain current, each output, all outputs on, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 A
Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 A
Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . 2.25 A
Single-pulse avalanche energy, EAS, TC = 25°C (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 mJ
Continuous total power dissipation at (or below) TC = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . 0.95 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms and duty cycle = 2%.
Copyright  1995, Texas Instruments Incorporated
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SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.85
2.2
Gate-to-source threshold voltage
ID = 250 µA,
ID = 1 mA,
V(BR)
Reverse drain-to-GND breakdown voltage
(across D1)
Drain-to-GND current = 250 µA
VDS(on)
Drain-to-source on-state voltage
ID = 0.75 A,
See Notes 2 and 3
VF
Forward on-state voltage, GND-to-drain
ID = 0.75 A,
See Notes 2 and 3
VF(SD)
Forward on-state voltage, source-to-drain
IS = 0.75 A,
VGS = 0,
See Notes 2 and 3 and Figure 12
IDSS
Zero-gate-voltage drain current
VDS = 48 V,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
IGSSR
Forward gate current, drain short circuited to source
VGS = 16 V,
VSG = 16 V,
VDS = 0
VDS = 0
Leakage current, drain-to-GND
VDGND = 48 V
TC = 25°C
TC = 125°C
0.5
10
TC = 25°C
0.6
0.7
Static drain-to-source on-state resistance
VGS = 5 V,
ID = 0.75 A,
See Notes 2 and 3
and Figures 6 and 7
TC = 125°C
0.94
1
V(BR)DSX
VGS(th)
Ilkg
rDS(on)
Drain-to-source breakdown voltage
Reverse gate current, drain short circuited to source
VGS = 0
VDS = VGS
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse transfer capacitance,
common source
VDS = 25 V,
f = 1 MHz,
V
100
VGS = 5 V,
V
V
0.45
0.53
1.8
V
V
0.85
1
V
0.05
1
0.5
10
10
100
nA
10
100
nA
0.05
1
µA
A
µA
A
Ω
VDS = 10 V,
ID = 0.5 A,
See Notes 2 and 3 and Figure 9
gfs
60
1.5
UNIT
0.75
VGS = 0,
See Figure 11
0.9
S
115
145
60
75
30
40
pF
NOTES: 2. Technique should limit TJ − TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER
trr(SD)
Reverse-recovery time
QRR
Total diode charge
2
TEST CONDITIONS
IS = 0.375 A,
di/dt = 100 A /µs,
See Figures 1 and 14
VGS = 0,
VDS = 48 V,
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MIN
TYP
Z1, Z2, Z3
30
D1
85
Z1, Z2, Z3
0.03
D1
0.19
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MAX
UNIT
ns
µC
SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
resistive-load switching characteristics, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
td(on)
td(off)
Turn-on delay time
tr2
tf2
Rise time
Fall time
13
26
Qg
Total gate charge
1.8
2.3
Qgs(th)
Threshold gate-to-source charge
0.4
0.5
Qgd
Gate-to-drain charge
1.1
1.4
LD
Internal drain inductance
5
LS
Internal source inductance
5
Rg
Internal gate resistance
Turn-off delay time
VDD = 25 V,
tf1 = 10 ns,
VDS = 48 V,
See Figure 3
RL = 67 Ω,
See Figure 2
ID = 0.375 A,
tr1 = 10 ns,
VGS = 5 V,
8
16
12
24
14
28
UNIT
ns
nC
nH
Ω
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
RθJA
Junction-to-ambient thermal resistance,
See Note 4
RθJC
Junction-to-case thermal resistance
MIN
TYP
130
All outputs with equal power
MAX
UNIT
°C/W
C/W
44
NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink.
PARAMETER MEASUREMENT INFORMATION
1.5
VDS = 48 V
VGS = 0
TJ = 25°C
Z1, Z2, and Z3 Only
I S − Source-to-Drain Diode Current − A
1
Reverse di/dt = 100 A/µs
0.5
0
25% of IRM†
− 0.5
−1
Shaded Area = QRR
− 1.5
IRM†
−2
trr(SD)
− 2.5
0
25
50
75
100 125 150
t − Time − ns
175
200
225
250
† IRM = maximum recovery current
NOTE A. The above waveform represents D1 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
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3
SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
RL
tr1
VDS
tf1
5V
Pulse Generator
VGS
VGS
0V
td(off)
DUT
Rgen
50 Ω
CL = 30 pF
(see Note A)
50 Ω
td(on)
tf2
tr2
VDD
VDS
VDS(on)
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
5V
0.3 µF
VDS
0
Qgs(th)
VDD = 48 V
VGS
DUT
IG = 1 µA
Qgd
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
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SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
tav†
tw
4.2 mH
5V
Pulse Generator
(see Note A)
VGS
VDS
ID
0V
VGS
50 Ω
DUT
IAS
(see Note B)
ID
0V
Rgen
50 Ω
V(BR)DSX = 60 V Min
VDS
0V
TEST CIRCUIT
VOLTAGE AND CURRENT WAVEFORMS
† Non-JEDEC symbol for avalanche time
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 2.25 A.
I
Energy test level is defined as E
AS
+
AS
V
t av
(BR)DSX
2
+ 19 mJ, where t av + avalanche time.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
2.5
1.5
2
ID = 1 mA
1.5
ID = 100 µA
1
0.5
0
−40 −20
ID = 0.75 A
1.2
Resistance − Ω
VDS = VGS
r DS(on) − Static Drain-to-Source On-State
V GS (th) − Gate-to-Source Threshold Voltage − V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
0.9
VGS = 4.5 V
0.6
0.3
0
−40 −20
20 40 60 80 100 120 140 160
TJ − Junction Temperature − °C
0
VGS = 5 V
Figure 5
0
20 40 60 80 100 120 140 160
TJ − Junction Temperature − °C
Figure 6
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SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
1
2.25
TJ = 25°C
2
0.8
VGS = 4 V
1.75
I D − Drain Current − A
On-State Resistance − Ω
r DS(on) − Static Drain-to-Source
0.9
VGS = 4.5 V
0.7
0.6
VGS = 5 V
1.50
VGS = 3.6 V
1.25
1
0.75
VGS = 3 V
0.5
0.50
TJ = 25°C
nVGS = 0.2 V
0.25
0
0.4
0.01
0.1
1
ID − Drain Current − A
10
0
1
2
3
4
VDS − Drain-to-Source Voltage − V
Figure 7
Figure 8
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
50
2
1.75
35
30
25
20
15
1.50
1.25
1
0.75
0.92
0.915
0
0.91
0
0.905
0.25
0.9
5
0.895
0.50
0.89
10
0.885
TJ = 25°C
TJ = 75°C
TJ = 125°C
VDS = 5 V
I D − Drain Current − A
40
Percentage of Units − %
2.25
Total Number of
Units = 639
VDS = 10 V
ID = 0.5 A
TJ = 25°C
45
TJ = 150°C
TJ = − 40°C
0
1
2
3
4
VGS − Gate-to-Source Voltage − V
gfs − Forward Transconductance − S
Figure 9
6
5
Figure 10
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SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
10
400
360
C − Capacitance − pF
160
I SD − Source-to-Drain Diode Current − A
VGS = 0
f = 1 MHz
TJ = 25°C
Ciss(0) = 158 pF
Coss(0) = 400 pF
Crss(0) = 78 pF
Ciss
120
80
Coss
40
Crss
4
8
12 16 20 24 28 32 36
VDS − Drain-to-Source Voltage − V
1
TJ = 75°C
0.1
40
Figure 12
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
100
14
ID = 0.375 A
TJ = 25°C
See Figure 3
VDS = 20 V
10
40
8
VDS = 30 V
6
VDS = 20 V
20
4
10
2
VDS = 48 V
0
t rr − Reverse-Recovery Time − ns
12
VGS − Gate-to-Source Voltage − V
VDS − Drain-to-Source Voltage − V
70
30
0.5
1
1.5
2
VGS = 0
VDS = 48 V
IS = 0.375 A
TJ = 25°C
See Figure 1
75
D1
50
Z1, Z2, and Z3
25
0
0
0
10
1
VSD − Source-to-Drain Voltage − V
DRAIN-TO-SOURCE AND GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
50
TJ = 25°C
TJ = 125°C
Figure 11
60
TJ = − 40°C
TJ = 150°C
0.01
0.1
0
0
VGS = 0
0
100
200
300
400
500
600
Reverse dl/dt − A/µs
Qg − Gate Charge − nC
Figure 13
Figure 14
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SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
THERMAL INFORMATION
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
4
I AS − Maximum Peak Avalanche Current − A
I D − Maximum Drain Current − A
TC = 25°C
1 µs†
10 ms†
1
1 ms†
500 µs†
DC Conditions
0.1
0.1
10
1
VDS − Drain-to-Source Voltage − V
See Figure 4
3
2
TC = 25°C
TC = 125°C
1
0.01
100
0.1
tav − Time Duration of Avalanche − ms
† Less than 2% duty cycle
Figure 16
Figure 15
8
1
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SLIS035B − JUNE 1994 − REVISED SEPTEMBER 1995
THERMAL INFORMATION
NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE†
vs
PULSE DURATION
R θJA − Normalized Junction-to-Ambient Thermal Resistance − Ω
10
1
DC Conditions
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
tc
tw
ID
0
0.0001
0.0001
0.001
0.01
0.1
1
10
tw − Pulse Duration − s
† Device mounted on FR4 printed-circuit board with no heat sink.
NOTE A: ZθA(t) = r(t) RθJA
t w + pulse duration
t c + cycle time
d + duty cycle + t wńt c
Figure 17
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9
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPIC3322LD
OBSOLETE
SOIC
D
Pins Package Eco Plan (2)
Qty
8
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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