SLIS037 − NOVEMBER 1994
•
•
•
•
•
Low rDS(on) . . . 0.23 Ω Typ
High Voltage Output . . . 60 V
Extended ESD Capability . . . 4000 V
Pulsed Current . . . 11.25 A Per Channel
Fast Commutation Speed
DW PACKAGE
(TOP VIEW)
OUTPUT1
GATE4
SOURCE4
SOURCE4
GND
GND
GATE5
SOURCE6
SOURCE6
GATE6
OUTPUT3
OUTPUT3
description
1
24
2
23
3
22
4
21
5
20
6
19
OUTPUT1
GATE1
DRAIN1
DRAIN1
DRAIN2
DRAIN2
OUTPUT2
OUTPUT2
GATE2
DRAIN3
DRAIN3
GATE3
The TPIC1301 is a monolithic gate-protected
7
18
power DMOS array that consists of six electrically
8
17
isolated N-channel enhancement-mode DMOS
9
16
transistors configured as three half H-bridges.
10
15
Each transistor features integrated high-current
11
14
zener diodes (ZCXa and ZCXb) to prevent gate
12
13
damage in the event that an overstress condition
occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body
model of a 100-pF capacitor in series with a 1.5-kΩ resistor.
The TPIC1301 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of − 40°C to 125°C.
schematic
OUTPUT2
17, 18
DRAIN1
GATE5
7
21, 22
GATE2 DRAIN2
16
19, 20
Q2
Q1
GATE1
ZC1b
ZC2b
D1
OUTPUT1
SOURCE4
13
ZC3a
11, 12
D4
2
GATE3
ZC3b
D2 D3
1, 24
D5
Q5
Q4
GATE4
Z3
ZC2a
ZC1a
DRAIN3
Q3
Z2
Z1
23
14, 15
OUTPUT3
Q6
Z4
Z5
Z6
10
ZC4b
ZC5b
ZC6b
ZC4a
ZC5a
ZC6a
8, 9
3, 4
GATE6
SOURCE6
5, 6
GND
NOTE: For correct operation, no terminal pin may be taken below GND.
Copyright 1994, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
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2−1
SLIS037 − NOVEMBER 1994
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-GND voltage, VDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
SOURCE4, SOURCE6-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −9 V to 18 V
Continuous drain current, each output, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25 A
Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25 A
Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . 11.25 A
Continuous gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Pulsed gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA
Single-pule avalanche energy, EAS, TC = 25°C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . . 17.2 mJ
Continuous total dissipation, TC = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
2−2
•
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•
SLIS037 − NOVEMBER 1994
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
V(BR)GS
V(BR)SG
Gate-to-source breakdown voltage
ID = 250 µA,
ID = 1 mA,
See Figure 5
VGS = 0
VDS = VGS,
Source-to-gate breakdown voltage
IGS = 250 µA
ISG = 250 µA
V(BR)
Reverse drain-to-GND breakdown voltage
(across D1 −D5)
Drain-to-GND current = 250 µA
VDS(on)
Drain-to-source on-state voltage
ID = 2.25 A,
See Notes 2 and 3
VF(SD)
Forward on-state voltage, source-to-drain
VF
MIN
TYP
MAX
60
1.5
UNIT
V
1.75
2.2
V
18
V
9
V
100
V
VGS = 10 V,
0.52
0.62
V
IS = 2.25 A,
VGS = 0 (Z1 −Z6),
See Notes 2 and 3 and Figure 12
1
1.2
V
Forward on-state voltage, GND-to-drain
ID = 2.25 A (D1 −D5)
See Notes 2 and 3
5
IDSS
Drain current-gate shorted to source
VDS = 48 V,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward-gate current, drain short circuited to
source
VGS = 15 V,
IGSSR
Reverse-gate current, drain short circuited to
source
Ilkg
rDS(on)
V
0.05
1
0.5
10
VDS = 0
20
200
nA
VSG = 5 V,
VDS = 0
10
100
nA
Leakage current, drain-to-GND
Gate shorted to source
TC = 25°C
TC = 125°C
0.05
1
VDGND = 48 V
0.5
10
TC = 25°C
0.23
0.275
Static drain-to-source on-state resistance
VGS = 10 V,
ID = 2.25 A,
See Notes 2 and 3
and Figures 6 and 7
TC = 125°C
0.35
0.4
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse transfer capacitance, common
source
VDS = 25 V,
f = 1 MHz,
µA
A
Ω
VDS = 15 V,
ID = 1.125 A,
See Notes 2 and 3 and Figure 9
gfs
µA
A
1.6
VGS = 0,
See Figure 11
2.21
S
200
250
175
220
40
75
pF
NOTES: 2. Technique should limit TJ − TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER
trr
QRR
Reverse-recovery time
Total diode charge
TEST CONDITIONS
IS = 1.125 A,
VGS = 0,
See Figures 1 and 14
VDS = 48 V,
di/dt = 100 A/µs,
•
MIN
MAX
UNIT
50
ns
65
nC
Z1, Z2, and Z3
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•
TYP
2−3
SLIS037 − NOVEMBER 1994
resistive-load switching characteristics, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
25
50
25
50
15
30
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Qg
Total gate charge
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
5
Internal source inductance
5
Rg
Internal gate resistance
Turn-off delay time
RL = 20 Ω,
See Figure 2
VDD = 25 V,
tdis = 10 ns,
ten = 10 ns,
Fall time
VDS = 48 V,
See Figure 3
ID = 1.125 A,
VGS = 10 V,
7
15
6.2
7.4
0.7
0.8
2.4
2.9
UNIT
ns
nC
nH
Ω
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA
Junction-to-ambient thermal resistance
See Notes 4 and 7
90
°C/W
RθJB
Junction-to-board thermal resistance
See Notes 5 and 7
45
°C/W
RθJP
Junction-to-pin thermal resistance
See Notes 6 and 7
28
°C/W
NOTES: 4.
5.
6.
7.
2−4
Package mounted on an FR4 printed-circuit board with no heatsink.
Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
Package mounted in intimate contact with infinite heatsink.
All outputs with equal power
•
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•
SLIS037 − NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
2.25
I S − Source-to-Drain Diode Current − A
1.5
VDS = 48 V
VGS = 0
TJ = 25°C
Z1, Z2, and Z3
trr (SD)
IS
Reverse di/dt = 100 A/µs
0.75
0
− 0.75
25% of IRM†
− 1.5
Shaded Area = QRR
− 2.25
IRM†
−3
− 3.75
0
50
100
150
200
250
300
350
400
450
500
Time − ns
† IRM = maximum recovery current
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
VDD = 25 V
RL
Pulse Generator
ten
10 V
VDS
VGS
0V
VGS
50 Ω
tr
tf
CL 30 pF
(see Note A)
50 Ω
td(off)
td(on)
DUT
Rgen
tdis
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
•
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•
2−5
SLIS037 − NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
10 V
0.3 µF
Qgs(th)
VDD
VDS
0
VGS
DUT
IG = 100 µA
Qgd
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
VDD = 25 V
tw
160 µH
Pulse Generator
(see Note A)
ID
VDS
15 V
VGS
0V
IAS
(see Note B)
VGS
50 Ω
tav
ID
DUT
0V
Rgen
50 Ω
V(BR)DSX = 60 V Min
VDS
0V
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 11.25 A.
I
V
t av
AS
(BR)DSX
Energy test level is defined as E
+
+ 17.2 mJ.
AS
2
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
2−6
•
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•
SLIS037 − NOVEMBER 1994
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VGS(th) − Gate-to-Source Threshold Voltage − V
2.5
0.6
ID = 2.25 A
r DS(on) − Static Drain-to-Source
2
ID = 1 mA
1.5
ID = 100 µA
1
0.5
0
− 40 − 20
0
20
40
60
On-State Resistance − Ω
VDS = VGS
0.4
VGS = 10 V
VGS = 15 V
0.2
0
− 40 − 20
80 100 120 140 160
0
Figure 5
10
TJ = 25°C
VGS
= 15 V
9
VGS
= 10 V
VGS = 5 V
0.5
0.4
0.3
ÁÁ
ÁÁ
VGS = 10 V
0.2
VGS = 15 V
7
∆VGS = 0.2 V
TJ = 25°C
(unless otherwise
noted)
6
5
VGS = 4 V
4
3
2
VGS = 3 V
1
0.1
0.1
80 100 120 140 160
8
I D − Drain Current − A
On-State Resistance − Ω
rDS(on) − Static Drain-to-Source
60
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
0.6
ÁÁ
ÁÁ
ÁÁ
ÁÁ
40
Figure 6
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
0.9
0.8
0.7
20
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
0
1
10
ID − Drain Current − A
0
100
1
7
8
9
2
3
4
5
6
VDS − Drain-to-Source Voltage − V
Figure 7
10
Figure 8
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•
2−7
SLIS037 − NOVEMBER 1994
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
25
10
Total Number of
Units = 2196
VDS = 15 V
ID = 1.125 A
TJ = 25°C
TJ = 25°C
TJ = 75°C
8
I D − Drain Current − A
Percentage of Units − %
20
TJ = − 40°C
9
15
10
7
TJ = 125°C
6
TJ = 150°C
5
4
3
2
5
0
2.360
2.330
2.300
2.270
2.240
2.210
2.180
2.150
2.120
2.090
2.030
0
2.060
1
0
1
2
3
4
5
6
7
8
9
10
VGS − Gate-to-Source Voltage − V
gfs − Forward Transconductance − S
Figure 9
Figure 10
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
800
10
720
Capacitance − pF
640
560
I SD − Source-to-Drain Diode Current − A
VGS = 0
f = 1 MHz
TJ = 25°C
Ciss(0) = 307 pF
Coss(0) = 437 pF
Crss(0) = 141 pF
480
400
320
Ciss
240
160
Coss
Crss
80
VGS = 0
6
4
2
1
0.6
TJ = 125°C
TJ = 150°C
TJ = 25°C
0.2
TJ = 75°C
0
0.1
0
4
8
12
16
20
24
28
32
36
40
0.1
VDS − Drain-to-Source Voltage − V
1
VSD − Source-to-Drain Voltage − V
Figure 11
2−8
TJ = − 40°C
0.4
Figure 12
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•
10
SLIS037 − NOVEMBER 1994
TYPICAL CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
12
ID = 1.125 A
TJ = 25°C
See Figure 3
50
10
VDD = 20 V
40
8
VDD = 30 V
30
6
20
4
VDD = 48 V
10
2
VGS − Gate-to-Source Voltage − V
VDS − Drain-to-Source Voltage − V
60
VDD = 20 V
0
0
0
1
2
3
4
5
6
7
8
Qg − Gate Charge − nC
Figure 13
REVERSE RECOVERY TIME
vs
REVERSE di/dt
trr − Reverse Recovery Time − ns
50
45
40
Z1, Z2, and Z3
35
VDS = 48 V
VGS = 0
IS = 1.125 A
TJ = 25°C
See Figure 1
30
25
0
100
200
300
400
500
600
Reverse di/dt − A/µs
Figure 14
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•
2−9
SLIS037 − NOVEMBER 1994
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
100
I D − Maximum Drain Current − A
TC = 25°C
ÁÁ
ÁÁ
1 µs†
10
10 ms†
1 ms†
1
500 µs†
θ JA‡
θ JP§
DC Conditions
0.1
0.1
1
10
100
VDS − Drain-to-Source Voltage − V
† Less than 2% duty cycle
‡ Device mounted on FR4 printed-circuit board with no heatsink.
§ Device mounted in intimate contact with infinite heatsink.
Figure 15
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
I AS − Maximum Peak Avalanche Current − A
100
See Figure 4
10
TC = 25°C
TC = 125°C
1
0.01
0.1
1
10
tav − Time Duration of Avalanche − ms
Figure 16
2−10
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•
100
SLIS037 − NOVEMBER 1994
THERMAL INFORMATION
DW PACKAGE†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
RθJB − Junction-to-Board Thermal Resistance −°C/W
DC Conditions
d = 0.5
10
d = 0.2
d = 0.1
d = 0.05
d = 0.02
1
d = 0.01
tc
tw
ID
Single Pulse
0
0.1
0.0001
0.001
0.01
0.1
1
10
100
tw − Pulse Duration − s
† Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink
NOTE A. ZθB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw / tc
Figure 17
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•
2−11
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPIC1301DW
OBSOLETE
SOIC
DW
Pins Package Eco Plan (2)
Qty
24
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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