TI TPIC5322LD

SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
D
D
D
D
D
Low rDS(on) . . . 0.45 Ω Typ
High-Voltage Outputs . . . 60 V
Pulsed Current . . . 3 A Per Channel
Fast Commutation Speed
Direct Logic-Level Interface
D PACKAGE
(TOP VIEW)
GND
SOURCE1
SOURCE1
SOURCE2
SOURCE2
SOURCE3
SOURCE3
GATE3
description
The TPIC5322L is a monolithic logic-level power
DMOS array that consists of three electrically
isolated independent N-channel enhancementmode DMOS transistors.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
DRAIN1
DRAIN1
GATE1
DRAIN2
DRAIN2
GATE2
DRAIN3
DRAIN3
The TPIC5322L is offered in a standard 16-pin
small-outline surface-mount (D) package and is
characterized for operation over the case
temperature range of −40°C to 125°C.
schematic
DRAIN1
GATE2
15, 16
Q1
GATE1
DRAIN2
11
D1
2, 3
SOURCE1
DRAIN3
8
Q2
D2
Z1
14
GATE3
12, 13
9, 10
Q3
Z2
1
GND
4, 5
SOURCE2
D3
Z3
6, 7
SOURCE3
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Gate-to-source voltage, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Continuous drain current, each output, all outputs on, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 3 A
Single-pulse avalanche energy, EAS, TC = 25°C (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40.5 mJ
Continuous total power dissipation at (or below) TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.09 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms and duty cycle = 2%.
Copyright  1994, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
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1
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ID = 250 µA,
ID = 1 mA,
See Figure 5
V(BR)DSX
Drain-to-source breakdown voltage
VGS = 0
VDS = VGS,
VGS(th)
Gate-to-source threshold voltage
V(BR)
Reverse drain-to-GND breakdown voltage (across
D1, D2, and D3)
Drain-to-GND current = 250 µA
VDS(on)
Drain-to-source on-state voltage
ID = 1 A,
See Notes 2 and 3
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1 A,
VGS = 0,
See Notes 2 and 3 and Figure 12
VF
Forward on-state voltage, GND-to-drain
ID = 1 A
MIN
TYP
MAX
60
1.5
V
1.85
2.2
100
VGS = 5 V,
UNIT
V
V
0.45
0.525
V
0.85
1
V
3.7
V
IDSS
Zero-gate-voltage drain current
VDS = 48 V,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short circuited to
source
VGS = 16 V,
VDS = 0
10
100
nA
IGSSR
Reverse gate current, drain short circuited to
source
VSG = 16 V,
VDS = 0
10
100
nA
1
Leakage current, drain-to-GND
VDGND = 48 V
TC = 25°C
TC = 125°C
0.05
Ilkg
0.5
10
TC = 25°C
0.45
0.525
Static drain-to-source on-state resistance
VGS = 5 V,
ID = 1 A,
See Notes 2 and 3
and Figures 6 and 7
TC = 125°C
0.7
0.78
rDS(on)
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse-transfer capacitance,
common source
VDS = 25 V,
f = 1 MHz,
1
0.5
10
µA
A
µA
A
Ω
VDS = 10 V,
ID = 0.5 A,
See Notes 2 and 3 and Figure 9
gfs
0.05
1
VGS = 0,
See Figure 11
1.24
S
135
170
80
100
30
40
pF
NOTES: 2. Technique should limit TJ − TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
2
TEST CONDITIONS
IS = 0.5 A,
VGS = 0,
See Figures 1 and 14
VDS = 48 V,
di/dt = 100 A /µs,
MIN
Z1, Z2, Z3
35
D1, D2, D3
110
Z1, Z2,Z3
D1, D2, D2
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TYP
0.035
0.35
MAX
UNIT
ns
µC
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
resistive-load switching characteristics, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Fall time
13
26
Qg
Total gate charge
3.1
3.8
Qgs(th)
Threshold gate-to-source charge
0.4
0.5
Qgd
Gate-to-drain charge
1.3
1.6
LD
LS
Internal drain inductance
5
Internal source inductance
5
Rg
Internal gate resistance
Turn-off delay time
RL = 50 Ω,
See Figure 2
VDD = 25 V,
tdis = 10 ns,
VDS = 48 V,
See Figure 3
ten = 10 ns,
ID = 0.5 A,
VGS = 5 V,
21
42
20
40
5
10
UNIT
ns
nC
nH
Ω
0.25
thermal resistance
PARAMETER
RθJA
TEST CONDITIONS
Junction-to-ambient thermal resistance
(see Note 4)
MIN
All outputs with equal power
TYP
MAX
UNIT
115
°C/W
32
°C/W
RθJP Junction-to-pin thermal resistance
NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink
PARAMETER MEASUREMENT INFORMATION
1
Reverse di/dt = 100 A/µs
I S − Source-to-Drain Diode Current − A
0.5
0
− 0.5
25% of IRM†
Shaded Area = QRR
−1
− 1.5
IRM†
−2
− 2.5
VDS = 48 V
VGS = 0
TJ = 25°C
Z1, Z2, and Z3
trr(SD)
−3
0
25
50
75
100
125 150 175
t − Time − ns
200
225
250
† IRM = maximum recovery current
NOTE A: The above waveform is representative of D1, D2, and D3 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
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3
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
RL
5V
VGS
Pulse Generator
VGS
0
DUT
Rgen
tdis
ten
VDS
50 Ω
td(on)
CL = 30 pF
(see Note A)
50 Ω
td(off)
tr
tf
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
5V
0.3 µF
Qgs(th)
VDD
VDS
0
VGS
DUT
IG = 1 µA
Qgd
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
4
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SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
tav
tw
5.25 mH
Pulse Generator
(see Note A)
ID
5V
VGS
VDS
0
IAS
(see Note B)
VGS
50 Ω
ID
DUT
0
Rgen
50 Ω
V(BR)DSX = 60 V Min
VDS
0
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 3 A.
I
V
t av
AS
(BR)DSX
Energy test level is defined as E
+
+ 40.5 mJ.
AS
2
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
2.5
1
VDS = VGS
ID = 1 A
2
ID = 1 mA
1.5
ID = 100 µA
1
0.5
0
−40 −20
0.8
On-State Resistance − Ω
r DS(on) − Static Drain-to-Source
VGS(th) − Gate-to-Source Threshold Voltage − V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VGS = 4.5 V
0.6
VGS = 5 V
0.4
0.2
0
−40 −20
20 40 60 80 100 120 140 160
TJ − Junction Temperature − °C
0
Figure 5
0
20 40 60 80 100 120 140 160
TJ − Junction Temperature − °C
Figure 6
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5
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
3
1
VGS = 5 V
TJ = 25°C
VGS = 4 V
2.5
0.8
I D − Drain Current − A
On-State Resistance − Ω
r DS(on) − Static Drain-to-Source
0.9
0.7
0.6
VGS = 4.5 V
nVGS = 0.2 V
TJ = 25°C
2
1.5
1
VGS = 3 V
0.5
0.5
VGS = 5 V
0
0.4
0.01
0.1
1
ID − Drain Current − A
0
10
1
5
6
7
8
2
3
4
VDS − Drain-to-Source Voltage − V
Figure 7
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
3
40
TJ = 25°C
Total Number of Units = 819
VDS = 10 V
ID = 0.5 A
TJ = 25°C
TJ = 125°C
2.5
TJ = 75°C
I D − Drain Current − A
Percentage of Units − %
30
10
Figure 8
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
35
9
25
20
15
2
1.5
1
TJ = 150°C
10
0.5
5
TJ = − 40°C
0
0
1.275
1.265
1.255
1.245
1.235
1.225
1.215
1.205
1.195
1.185
0
1
2
3
4
VGS − Gate-to-Source Voltage − V
gfs − Forward Transconductance − S
Figure 9
6
Figure 10
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5
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
TYPICAL CHARACTERISTICS
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
250
225
200
I SD − Source-to-Drain Diode Current − A
f = 1 MHz
VGS = 0
TJ = 25°C
Capacitance − pF
175
150
Ciss
125
100
Coss
75
50
Crss
25
4
8 12 16 20 24 28 32 36
VDS − Drain-to-Source Voltage − V
1
TJ = 125°C
0.1
40
1
VSD − Source-to-Drain Voltage − V
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
80
60
12
50
10
VDD = 20 V
40
8
VDD = 30 V
30
6
20
4
VDD = 48 V
10
t rr − Reverse-Recovery Time − ns
14
VGS − Gate-to-Source Voltage − V
VDS − Drain-to-Source Voltage − V
150
16
ID = 0.5 A
TJ = 25°C
See Figure 3
VDD = 20 V
1.5
2
2.5
125
100
D1, D2, and D3
75
50
Z1, Z2, and Z3
25
0
0
1
VDS = 48 V
VGS = 0
IS = 0.5 A
TJ = 25°C
See Figure 1
2
0
0.5
10
Figure 12
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
0
TJ = 25°C
TJ = 75°C
Figure 11
70
TJ = − 40°C
TJ = 150°C
0.01
0.1
0
0
VGS = 0
3
0
100
200
300
400
500
600
Reverse di/dt − A/µs
Qg − Gate Charge − nC
Figure 13
Figure 14
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7
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
MAXIMUM PEAK-AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
10
5
See Figure 4
I AS − Maximum Peak-Avalanche Current − A
I D − Maximum Drain Current − A
TC = 25°C
1 µs†
10 ms†
1
1 ms†
500 µs†
DC Conditions
0.1
0.1
10
1
VDS − Drain-to-Source Voltage − V
4
3
TC = 25°C
2
1
0.01
100
TC = 125°C
0.1
1
† Less than 2% duty cycle
Figure 15
8
10
tav − Time Duration of Avalanche − ms
Figure 16
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100
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
THERMAL INFORMATION
D PACKAGE†
NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
R θJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W
10
DC Conditions
1
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
tc
tw
ID
0
0.0001
0.0001
0.001
0.01
0.1
1
10
tw − Pulse Duration − s
† Device mounted on FR4 printed-circuit board with no heat sink
NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 17
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9
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPIC5322LD
OBSOLETE
SOIC
D
Pins Package Eco Plan (2)
Qty
16
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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