TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 HIGH-EFFICIENCY MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD FEATURES 1 • Operation Over 4.5-V to 28-V Input Range • Programmable Fixed-Frequency up to 1-MHz Voltage-Mode Controller • Predictive Gate Drive™ With Anti-Cross Conduction Circuitry • <1% Internal 700-mV Reference • Internal Gate Drive Outputs for High-Side and Synchronous N-Channel MOSFETs • 16-Pin PowerPAD™ Package • Thermal Shutdown Protection • TPS40070: Source Only • TPS40071: Source/Sink • Programmable High-Side Sense Short Circuit Protection 2 APPLICATIONS • • • • • DESCRIPTION The TPS4007x is a mid voltage, wide input (4.5 V to 28 V), synchronous, step-down converter. The TPS4007x offers design flexibility with a variety of user programmable functions, including; soft-start, UVLO, operating frequency, voltage feed-forward and high-side FET sensed short circuit protection. The TPS4007x incorporates MOSFET gate drivers for external N-channel high-side and synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates predictive anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction, while minimizing to eliminating current flow in the body diode of the SR FET. The TPS40071 allows the supply output to sink current at all times. The TPS40070 implements a source-only power supply. Power Modules Networking/Telecom PCI Express Industrial Servers SIMPLIFIED APPLICATION DIAGRAM TPS40070PWP 1 VDD 2 VOUT Powergood KFF RT ILIM 16 VDD VDD 15 3 LVBP BOOST 14 4 PGD HDRV 13 5 SGND SW 12 6 SS DBP 11 7 FB LDRV 10 8 COMP PGND 9 VOUT VDG−03170 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Predictive Gate Drive, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2009, Texas Instruments Incorporated TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com DESCRIPTION (CONTINUED) The TPS4007x uses voltage feed-forward control techniques to provide good line regulation over a wide-input voltage range, and fast response to input line transients with near constant gain with input variation to ease loop compensation. The externally programmable short circuit protection provides fault current limiting, as well as hiccup mode operation for thermal protection in the presence of a shorted output.The TPS4007x is packaged in a 16-pin PowerPAD package for better thermal performance at higher voltages and frequencies. See SLMA002 for information on board layout for the PowerPAD package. The pcb pad that the PowerPAD solders to should be connected to GND. Due to the die attach method, the PowerPAD itself cannot be used as the device ground connection. The two device grounds must be connected as well. ORDERING INFORMATION TA 40°C to 85°C (1) (2) APPLICATION PACKAGE PART NUMBER SOURCE ONLY (1) Plastic HTSSOP (PWP)( (2)) TPS40070PWP SOURCE/SINK (1) Plastic HTSSOP (PWP)( (2)) TPS40071PWP See Application Information section and Table 1. The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40070PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40070 TPS40071 VDD, ILIM VDD Input voltage range VOUT Output voltage range IOUT Output current source IOUT Output current sink 30 COMP, FB, KFF, PGD, LVBP –0.3 to 6 SW –0.3 to 40 SW, transient < 50 ns –2.5 COMP, KFF, RT, SS –0.3 to 6 VBOOST 10.5 6 LDRV, HDRV 1.5 LDRV, HDRV 2.0 KFF 10 RT A 1 LVBP mA 1.5 TJ Operating junction temperature range –40 to 125 Tstg Storage temperature –55 to 150 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) V 50 DBP LVBP Output current UNIT °C 260 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VDD Input voltage 4.5 28 V TA Operating free-air temperature -40 85 °C 2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 A, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VDD Input voltage range, VIN 4.5 28 V 2.5 3.5 mA 3.9 4.2 4.5 V 450 500 550 kHz OPERATING CURRENT IDD Quiescent current Output drivers not switching LVBP VLVBP Output voltage TA = TJ = 25°C OSCILLATOR/RAMP GENERATOR (1) fOSC Accuracy VRAMP PWM ramp voltage (2) VRT RT voltage tON Minimum output pulse time (2) VPEAK-VVAL 2.0 2.23 2.40 CHDRV = 0 nF Maximum duty cycle VKFF Feed-forward voltage IKFF Feed-forward current operating range (2) V 2.58 V 250 ns VFB = 0 V, 100 kHz ≤ fSW ≤ 500 kHz 84% 93% VFB = 0 V, fSW = 1 MHz 76% 93% 0.35 0.40 20 0.45 V 1100 µA 17 µA SOFT START ISS Charge current tDSCH Discharge time CSS = 3.9 nF 7 tSS Soft-start time CSS = 3.9 nF, VSS rising from 0.7 V to 1.6 V Command zero output voltage (1) 12 25 210 75 290 500 300 µs mV DBP VDBP VDD > 10 V Output voltage 7 8 4.0 4.3 TA = TJ = 25°C 0.698 0.700 0.704 0°C ≤ TA≤ 85°C 0.690 0.700 0.707 40°C ≤ TA≤ 85°C 0.690 0.700 0.715 VDD = 4.5 V, IOUT = 25 mA 9 V ERROR AMPLIFIER VFB Feedback regulation voltage total variation Soft-start offset from VSS (2) VSS Offset from VSS to error amplifier (2) 1 GBW Gain bandwidth AVOL Open loop gain 50 ISRC Output source current 2.5 4.5 ISINK Output sink current 2.5 6 IBIAS Input bias current (1) (2) 5 VFB = 0.7 V V –250 10 MHz dB mA 0 nA For zero output voltage only. Does not assure lack of activity on HDRV or LDRV. Ensured by design. Not production tested. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 3 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 A, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 105 125 µA –75 –50 –30 mV 135 225 ns SHORT CIRCUIT CURRENT PROTECTION IILIM Current sink into current limit VILIM(ofst) Current limit offset voltage VILIM = 11.5 V, (VSW - VILIM) VDD = 12 V tHSC Minimum HDRV pulse width During short circuit Propagation delay to output (3) 50 ns tBLANK Blanking time (3) 50 ns tOFF Off time during a fault (SS cycle times) 7 cycles VSW Switching level to end precondition (3) tPC Precondition time (3) VILIM Current limit precondition voltage threshold (3) (VDD - VSW) 2 V 100 6.8 ns V OUTPUT DRIVERS tHFALL High-side driver fall time (3) tHRISE High-side driver rise time (3) tHFALL High-side driver fall time (3) tHRISE High-side driver rise time (3) tLFALL Low-side driver fall time (3) Low-side driver rise time tLFALL Low-side driver fall time (3) tLRISE Low-side driver rise time (3) VOH High-level output voltage, HDRV VOL Low-level output voltage, HDRV VOH High-level output voltage, LDRV VOL Low-level output voltage, LDRV ns 48 72 CHDRV = 2200 pF, (HDRV - SW) VDD = 4.5 V, 0.2 V ≤ VSS≤ 4 V ns 96 24 CLDRV = 2200 pF (3) tLRISE 36 CHDRV = 2200 pF, (HDRV - SW) ns 48 48 CLDRV = 2200 pF, VDD= 4.5 V, 0.2 V ≤ VSS≤ 4 V ns 96 IHDRV = -0.01 A, (VBOOST- VHDRV) 0.7 1.0 IHDRV = -0.1 A, (VBOOST - VHDRV) 0.95 1.30 (VHDRV - VSW), IHDRV = 0.01A 0.06 0.10 (VHDRV - VSW), IHDRV = 0.1 A 0.65 1.0 (VDBP - VLDRV), ILDRV= -0.01A 0.65 1.00 (VDBP - VLDRV), ILDRV = -0.1 A 0.875 1.200 ILDRV = 0.01 A 0.03 0.05 ILDRV = 0.1 A 0.3 0.5 –5 0 5 15.2 17.0 6.2 7.2 8.2 V V V V ZERO CURRENT DETECTION IZERO Zero current threshold, TPS40070 mV BOOST REGULATOR VBOOST Output voltage VDD = 12 V V Programmable UVLO threshold voltage RKFF = 90.9 kΩ, turn-on, VDD rising Programmable UVLO hysteresis RKFF = 90.9 kΩ 1.10 1.55 2.00 Fixed UVLO threshold voltage Turn-on, VDD rising 4.15 4.30 4.45 275 365 UVLO VUVLO Fixed UVLO hysteresis V mV POWER GOOD VPG Powergood voltage VOH High-level output voltage, FB IPG = 1 mA 370 770 VOL Low-level output voltage, FB 630 500 mV THERMAL SHUTDOWN Shutdown temperature threshold (3) 165 Hysteresis (3) (3) 4 15 °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 PWP PACKAGE(1)(2) (TOP VIEW) 1 2 3 4 5 6 7 8 KFF RT LVBP PGD SGND SS FB COMP THERMAL PAD 16 15 14 13 12 11 10 9 ILIM VDD BOOST HDRV SW DBP LDRV PGND (1) For more information on the PWP package, refer to TI Technical Brief (SLMA002). (2) PowerPAD™ heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins. Table 1. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. BOOST 14 I Gate drive voltage for the high-side N-channel MOSFET. The BOOST voltage is 8 V greater than the input voltage. A capacitor should be connected from this pin to the SW pin. COMP 8 O Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the FB pin to compensate the overall loop. The comp pin is internally clamped to 3.4 V. DBP 11 O 8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed to ground with a 1.0-µF ceramic capacitor. FB 7 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V. HDRV 13 O Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off). ILIM 16 I Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage on this pin is compared to the voltage drop (VVDD -VSW) across the high side N-channel MOSFET during conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately VDD/2 and released when SW is within 2 V of VDD or after a timeout (the precondition time) - whichever occurs first. Placing a capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time, effectively programming the ILIM blanking time. See applications information. KFF 1 I A resistor is connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into this pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at this pin is maintained at 400 mV. LDRV 10 O Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFET off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC. LVBP 3 O 4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-µF ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied. PGD 4 O This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a 10% band around VREF. PGND 9 RT 2 SGND 5 Signal ground reference for the device. SS 6 I Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 10 µA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal reference voltage of 1 V plus the internal reference voltage of 0.7 V. If SS is below the 1-V offset voltage to the error amplifier. The resulting output voltage is zero. Also provides timing for fault recovery attempts. Maximum recommended capacitor value is 22nF. SW 12 I This pin is connected to the switched node of the converter. It is used for short circuit sensing, gate drive timing information and is the return for the high side driver. A 1.5-Ω resistor is required in series with this pin for protection against substrate current issues. VDD 15 I Supply voltage for the device. Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s). I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 5 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com FUNCTIONAL BLOCK DIAGRAM 11 DBP VDD VDD 15 Reference Regulator UVLO Controller 16 ILIM UVLO LVBP 3 RT 2 Oscillator Ramp Generator SW CLK Pulse Control 9 SS Active KFF 1 HDRV LDRV PGD 4 Power Good Logic SGND 5 770 mV FB 630 mV SS Active ILIM CLK LVBP Soft Start and Fault Control SS CLK CLK + + 6 COMP 8 Overcurrent Comparator and Control OC OC DBP OC FB 7 IZERO 12 SW RAMP 700 mV IZERO Comparator and Control (TPS40070 only) PGND PWM Predictive Gate Drive Control Logic 14 BOOST 13 HDRV 10 LDRV SW UVLO PGND FAULT IZERO VDG−03171 6 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 APPLICATION INFORMATION The TPS40070 family of parts allows the user to construct synchronous voltage-mode buck converters with inputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays for increased efficiency and improved converter output power capability. Voltage feed-forward is employed to ease loop compensation and provide better line transient response. A converter based on the TPS40070 operates as a single quadrant (source only) converter at all times. When the rectifier FET is on and the controller senses that current is near zero in the inductor, the rectifier FET is turned off, preventing the buildup of negative or reverse current in the inductor. This feature prevents the converter from pulling energy from its output and forcing that energy onto its input. Converters based on the TPS40071 operates as a two quadrant converter all the time (source and sink current). This is the controller of choice for most applications. MINIMUM PULSE WIDTH The TPS4007x devices have limitations on the minimum pulse width that can be used to design a converter. Reliable operation is guaranteed for nominal pulse widths of 250 ns and above. This places some restrictions on the conversion ratio that can be achieved at a given switching frequency. Figure 2 shows minimum output voltage for a given input voltage and frequency. SLEW RATE LIMIT ON VDD The regulator that supplies power for the drivers on the TPS40070/1 requires a limited rising slew rate on VDD for proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shoot and damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than 0.12 V/µs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in normal operation. This places some constraints on↔ the R-C values that can be used. Figure 1 is a schematic fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R and C that limits the slew rate in the worst case condition. TPS40070 R ILIM 16 15 VDD VIN + _ HDRV 13 C SW 12 9 PGND LDRV 10 UDG−05058 Figure 1. Limiting the Slew Rate Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 7 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com V IN * 8 V R SR 0.2 V Rt f SW Q g(TOT) ) I DD Cu (1) (2) where • • • • • VVIN is the final value of the input voltage ramp fSW is the switching frequency Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet) IDD is the TPS4007x input current (3.5 mA maximum) SR is the maximum allowed slew rate [12×104] (V/s) SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS4007x has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching frequency of the clock oscillator. The clock frequency is related to RT by: RT + ǒ f SW(kHz) 1 17.82 10 *6 Ǔ * 23 kW (3) MINIMUM OUTPUT VOLTAGE vs FREQUENCY 5.0 SWITCHING FREQUENCY vs TIMING RESISTANCE 600 VIN = 28 V 4.5 VIN = 24 V 500 VIN = 15 V VIN = 18 V 3.5 3.0 VIN = 12 V VIN = 10 V 2.5 2.0 1.5 VIN = 8 V RT - Timing Resistance - kΩ VOUT - Output Voltage - V 4.0 400 300 200 100 1.0 0.5 100 VIN = 5 V 200 300 400 500 600 700 800 900 1000 0 0 200 400 600 800 fOSC - Oscillator Frequency - kHz fSW - Switching Frequency - kHz Figure 2. Figure 3. 1000 PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 9). The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed to start. The PWM ramp time is programmed via a single resistor (RKFF) connected from KFF VDD. RKFF , VSTART and RT are related by (approximately): 8 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 R KFF + 0.131 RT 10*3 V UVLO(on) * 1.61 2 V UVLO(on) ) 1.886 V UVLO * 1.363 * 0.02 10*5 R T * 4.87 R 2T (4) where • • RT and RKFF are in kΩ VUVLO(on) is in V This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up 15% from this number. Figure 5 through Figure 6 show the typical relationship of VUVLO(on), VUVLO(off) and RKFF at three common frequencies. FREQUENCY vs INPUT VOLTAGE UNDERVOLTAGE LOCKOUT THRESHOLD vs FEEDFORWARD IMPEDANCE 525 20 520 18 VUVLO − Programmable UVLO Threshold − V fSW = 300 kHz fOSC − Frequency − kHz 515 510 505 500 495 490 485 480 5 9 11 13 15 17 19 21 23 25 27 29 UVLOVON 16 14 12 UVLOVOFF 10 8 6 4 2 100 150 200 250 300 350 400 VDD − Input Voltage − V RKFF − Feedforward Impedance − kΩ Figure 4. Figure 5. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 450 9 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com UNDERVOLTAGE LOCKOUT THRESHOLD vs FEEDFORWARD IMPEDANCE UNDERVOLTAGE LOCKOUT THRESHOLD vs FEEDFORWARD IMPEDANCE 20 20 fSW = 750 kHz UVLOVON 18 VUVLO − Programmable UVLO Threshold − V VUVLO − Programmable UVLO Threshold − V fSW = 500 kHz 16 14 12 UVLOVOFF 10 8 6 4 2 UVLOVON 18 16 14 12 UVLOVOFF 10 8 6 4 2 60 90 120 150 180 210 240 RKFF − Feedforward Impedance − kΩ 270 40 60 80 100 120 140 160 RKFF − Feedforward Impedance − kΩ Figure 6. 180 Figure 7. The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice the startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that with this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 8 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages At startup, LDRV may pulse high when VDD is in the range of 1 V to 1.25 V and VDD is rising extremely slowly. To minimize these effects, the ramp rate of VDD at startup should be greater than 1 V/ms. 10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 TYPICAL MAXIMUM DUTY CYCLE vs INPUT VOLTAGE 100 UVLO(on) = 15 V 90 80 Duty Cycle - % UVLO(on) = 8 V UVLO(on) = 12 V 70 60 UVLO(on) = 4.5 V 50 40 30 20 4 8 12 16 20 24 28 VIN - Input Voltage - V Figure 8. VIN VIN SW SW RAMP VPEAK COMP COMP RAMP VVALLEY tON1 t d + ON T T1 tON2 T2 tON1 > tON2 and d1 > d2 VDG−03172 Figure 9. Voltage Feed-Forward and PWM Duty Cycle Waveforms Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 11 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com PROGRAMMING SOFT START TPS4007x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a fixed current, generating a ramp signal. The voltage on SS is level shifted down approximately 1 V and fed into a separate non-inverting input to the error amplifier. The loop is closed on the lower of the level shifted SS voltage or the 700-mV internal reference voltage. Once the level shifted SS voltage rises above the internal reference voltage, output voltage regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-COUT time constant or: t START w 2p ǸL COUT (5) To ensure correct start up of the converter, the soft-start time is limited and can be calculated using Equation 6. DMIN t START v ms f SW 10*7 (6) where • • DMIN is the minimum operating duty cycle fSW is the converter switching frequency Please note: There is a direct correlation between tSTART and the input current required during start-up. The lower tSTART is, the higher the input current required during start-up since the output capacitance must be charged faster. For a desired soft-start time, the soft-start capacitance, CSS, can be found from: *6 A C SS + 12 10 t START (Farads) 0.7 V (7) PROGRAMMING SHORT CIRCUIT PROTECTION The TPS4007x uses a two-tier approach for short circuit protection. The first tier is a pulse-by-pulse protection scheme. Short circuit protection is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across a resistor (RILIM) connected from VDD to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 10. ILIM ILIM Threshold (A) Overcurrent VIN − 2V SW T2 ILIM T1 VIN − 2V ILIM Threshold (B) SW T1 T3 UDG−03173 Figure 10. Switching and Current Limit Waveforms and Timing Relationship 12 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of VDD. The ILIM pin is allowed to return to its nominal value after one of two events occur. If the SW node rises to within approximately 2 V of VDD, the device allows ILIM to go back to its nominal value. This is illustrated in Figure 10(A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes a driver delay of 50 ns typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to its nominal value, typically 20ns. The second event that can cause ILIM to return to its nominal value is for an internal timeout to expire. This is illustrated in Figure 10(B) as T3. Here SW never rises to VDD-2 V, for whatever reason, and the internal timer times out, releasing the ILIM pin. Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, this ensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false trips while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM sets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrent threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate for slower turn-on FETs. Choosing the proper capacitance requires care. If the capacitance is too large, the voltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift in overcurrent threshold as pulse width changes. Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on its SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as 2 V at -40C) below VDD. When ILIM is more than 1.4 V below VDD, the overcurrent circuit is effectively disabled. As a general rule, it is best to make the time constant of the R-C at the ILIM pin 0.2 times or less of the nominal pulse width of the converter as shown in see Equation 13. The second tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a fault condition is declared by the controller. When this happens, the outputs are placed in a state defined in Table 2. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero the PWM is re-enabled and the controller attempts to restart. If the fault has been removed the output starts up normally. If the output is still present the counter counts seven overcurrent pulses and re-enter the second tier fault mode. Refer to Figure 11 for typical fault protection waveforms. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 13 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com The minimum short circuit limit setpoint (ISCP(min)) depends on tSTART, COUT, VOUT, ripple current in inductor (IRIPPLE) and the load current at turn-on (ILOAD). COUT VOUT I I SCP(min) u ) I LOAD ) RIPPLE t START 2 ǒ Ǔ ǒ Ǔ (8) The short circuit limit programming resistor (RILIM) is calculated from: 100 R ILIM + ǒRDS(ON)max Ǔ I SCP ) V ILIM(ofst) ) 9 109 R VDD IR VDD ) 4.5 V I ILIM (W) (9) where • • • • • • IR VDD IILIM is the current into the ILIM pin (110 µA typical) VILIM(ofst) is the offset voltage between SW and ILIM pins (-50 mV typical) ISCP is the short-circuit protection current RDS(ON)max is the drain-to-source resistance of the high-side MOSFET RVDD is the slew rate limit resistor if used IRVDD is the current through RVDD and can be calculated using Equation 10. + f SW Q g(TOT) ) I DD (A) (10) where • • • fSW is the switching frequency Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet) IDD is the TPS4007x input current (3.5 mA maximum) To find the range of the overcurrent values use the following equations. 1.09 I ILIM(max) R ILIM * 0.09 RVDD I R * 0.045 V ) 75 mV VDD I SCP(max) + (A) R DS(ON)min 1.09 I SCP(min) + I ILIM(min) R ILIM * 0.09 RVDD IR VDD * 0.045 V ) 30 mV R DS(ON)max (11) (A) (12) The TPS40070/1 provides short circuit protection only. As such, it is recommended that the minimum short circuit protection level be placed at least 20% above the maximum output current required from the converter. The maximum output of the converter should be the steady state maximum output plus any transient specification that may exist. The ILIM capacitor maximum value can be found from: V OUT 0.2 C ILIM(max) + (Farads) VIN RILIM f SW (13) Note that this is a recommended maximum value. If a smaller value can be used, it should be. For most applications, consider using half the maximum value above. 14 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 HDRV Clock tBLANKING VILIM VVIN − VSW SS 7 Current-Limit Trips (HDRV Cycle Terminated by Current-Limit Trip) 7 Soft-Start Cycles VDG−03174 Figure 11. Typical Fault Protection Waveforms LOOP COMPENSATION Voltage mode buck type converters are typically compensated using Type III networks. Since the TPS4007x uses voltage feedforward control, the gain of the voltage feedforward circuit must be included in the PWM gain. The gain of the voltage feedforward circuit combined with the PWM circuit and power stage for the TPS4007x is: K PWM ^ VUVLO (on) (14) The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltage feedforward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly a function of the programmed startup voltage. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 15 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com BOOST AND DBP BYPASS CAPACITANCE The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOST capacitor should be a good quality, high-frequency capacitor. A capacitor with a minimum value of 100-nF is suggested. The DBP has to provide energy for both the synchronous MOSFET and the high-side MOSFET (via the BOOST capacitor). The suggested value for this capacitor is 1-µF ceramic, minimum. INTERNAL REGULATORS The internal regulators are linear regulators that provide controlled voltages for the drivers and the internal circuitry to operate from. The DBP pin is connected to a nominal 8-V regulator that provides power for the driver circuits to operate from. This regulator has two modes of operation. At VDD voltages below 8.5 V ,the regulator is in a low dropout mode of operation and tries to provide as little impedance as possible from VDD to DBP. Above 10 V at VDD, the regulator regulates DBP to 8 V. Between these two voltages, the regulator remains in the state it was in when VDD entered this region (see Figure 12). Small amounts of current can be drawn from this pin for other circuit functions, as long as power dissipation in the controller device remains at acceptable levels and junction temperature does not exceed 125C. The LVBP pin is connected to another internal regulator that provides 4.2-V (nom) for the operation of low-voltage circuitry in the controller. This pin can be used for other circuit purposes, but extreme care must be taken to ensure that no extra noise is coupled onto this pin, since controller performance suffers. Current draw is not to exceed 1 mA. See Figure 13 for typical output voltage at this pin. INPUT VOLTAGE vs LOW VOLTAGE BYPASS VOLTAGE INPUT VOLTAGE vs DBP VOLTAGE 4.50 10 VDBP - Low Voltage Bypass Voltage - V 4.45 VDBP - Driver Bypass Voltage - V 9 8 7 6 5 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 4 0 5 10 15 VDD - Input Voltage - V 20 25 5 10 15 20 25 30 VDD - Input Voltage - V Figure 12. Figure 13. TPS4007x POWER DISSIPATION The power dissipation in the TPS4007x is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance) can be calculated from: P D + Q g VDR f SW (Wattsńdriver) (15) where • 16 VDR is the driver output voltage Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 And the total power dissipation in the TPS4007x, assuming the same MOSFET is selected for both the high-side and synchronous rectifier is described in Equation 16. 2 PD PT + ) IQ V IN (Watts) V DR ǒ Ǔ (16) or P T + ǒ2 f SW ) I QǓ Qg V IN (Watts) (17) where: • IQ is the quiescent operating current (neglecting drivers) The maximum power capability of the TPS4007x PowerPAD package is dependent on the layout as well as air flow. The thermal impedance from junction to air assuming 2-oz. copper trace and thermal pad with solder and no air flow is see teh application report titledPowerPAD Thermally Enhanced Package (SLMA002) for detailed information on PowerPAD package mounting and usage. q JA + 36.51 CńW (18) O The maximum allowable package power dissipation is related to ambient temperature by Equation 19. T * TA PT + J (Watts) q JA (19) Substituting Equation 19 into Equation 18 and solving for fSW yields the maximum operating frequency for the TPS4007x. The result is described in Equation 20. ǒƪ ǒT J*T AǓ ƫ ǒq JA V DDǓ f SW + ǒ2 * IQ Q gǓ Ǔ (Hz) (20) BOOST DIODE The TPS4007x series has internal diodes to charge the boost capacitor connected from SW to BOOST. The drop across this diode is rather large at 1.4-V nominal at room temperature. If this drop is too large for a particular application, an external diode may be connected from DBP (anode) to BOOST (cathode). This provides significantly improved gate drive for the high side FET, especially at lower input voltages. LOW VOLTAGE OPERATION If the programmable UVLO is set to less than 6.5 V nominal, connect a 330-kΩ resistor across the soft-start capacitor. This eliminates a race condition inside the device that can lead to an output voltage overshoot on power down of the part. If operation is expected below -10°C ambient temperature and at less than 5-V input, it is recommended that a diode be connected from LVBP to DBP. (See Figure 16). GROUNDING AND BOARD LAYOUT The TPS4007x provides separate signal ground (SGND) and power ground (PGND) pins. Care should be given to proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (DBP), and the input capacitor should be connected to PGND plane. Sensitive nodes such as the FB resistor divider and RT should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. It is suggested that the SGND pin be tied to the copper area for the PowerPAD underneath the chip. Tie the PGND to the PowerPAD copper area as well and make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the SGND pin. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 17 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout practices results in sub-optimal operation. More detailed information can be found in the TPS40071EVM User's Guide (SLUU180). Output Ripple Consideration In addition to the typical output ripple associated with switching converters, which can vary from 5 mV to 150 mV, the TPS40070/1 exhibits a low-frequency ripple from 5 mV to 50 mV. The ripple, a consequence of the charge pump in the driver supply regulator, is well bounded under changes in line, load, and temperature. The ripple frequency does vary with the converter switching frequency and can vary from 10 kHz to 60 kHz. 18 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 SYNCHRONOUS RECTIFIER CONTROL Depending on which device is used the synchronous rectifier is controlled in slightly different ways. Table 2 describes the differences. For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC. Table 2. Synchronous Rectifier MOSFET States SYNCHRONOUS RECTIFIER OPERATION DURING DEVICE SOFT-START NORMAL FAULT OVERVOLTAGE TPS40070 Turns OFF when IZERO detected or start of next cycle Turns Off when IZERO detected or start of next cycle OFF Turns OFF when IZERO detected or start of next cycle TPS40071 Turns OFF only at start of next cycle Turns OFF only at start of next cycle ON Turns OFF only at start of next cycle, if duty cycle is > 0 + VDD R6 165 kΩ 12 V − R9 2 kΩ TPS40070PWP TPS40071PWP 1 KFF R2 165 kΩ C7 10 pF ILIM 16 C12 22 µF 2 RT VDD 15 C2 0.1 µF C10 0.1 µF 3 LVBP 4 PG C14 22 µF C8 0.1 µF BOOST 14 L1 COEV Q1 DXM1306−1R6 Si7840DP 1.6 µH HDRV 13 1.5 Ω 5 SGND C3 22 nF 6 SS R5 10 kΩ C5 5.6 nF DBP 11 7 VFB LDRV 10 8 COMP C4 470 pF + SW 12 C9 1 µF Q2 Si7856DP + C13 4.7 nF C15 47 µF + VOUT 1.8 V C16 C17 C18 10 A 470 µF 470 µF 0.1 µF PGND 9 − PWP R7 8.66 kΩ R3 5.49 kΩ C6 4.7 nF R8 226 Ω VDG−03175 Figure 14. 300 kHz, 12 V to 1.8 V Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 19 TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com + VDD 12 V R6 165 kΩ − 1 KFF R2 165 kΩ ILIM 16 2 RT C2 0.1 µF C7 10 pF R9 2 kΩ TPS40070PWP TPS40071PWP C12 22 µF VDD 15 3 LVPB BOOST 14 4 PG 5 SGND C10 0.1 µF D1 BAT54 HDRV 13 C3 22 nF + C9 1 µF DBP 11 C5 5.6 nF 7 VFB Q2 Si7856DP + C13 4.7 nF LDRV 10 8 COMP C4 470 pF Q1 Si7840DP 1.5 Ω L1 COEV DXM1306−1R6 1.6 µH SW 12 6 SS R5 10 kΩ C8 0.1 µF C14 22 µF + C15 C16 47 µF 470 µF PGND 9 VOUT 1.8 V C17 C18 470 µF 0.1 µF 10 A − PWP R7 8.66 kΩ R3 5.49 kΩ C6 4.7 nF R8 226 Ω VDG−03176 Figure 15. 300 kHz, 12 V to 1.8 V with Improved High-Side Gate Drive See Application Information section Boost Diodes. 20 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 TPS40070 TPS40071 www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 + VDD R6 47 kΩ 5V − R9 2 kΩ TPS40070PWP TPS40071PWP R2 90.1 kΩ 1 KFF ILIM 16 2 RT VDD 15 C2 0.1 µF C7 10 pF C10 0.1 µF 3 LVBP C12 22 µF C8 0.1 µF BOOST 14 4 PGD HDRV 13 C14 22 µF D1 BAT54 Q1 Si7860DP L1 COEV DXM1306−1R6 1.6 µH VOUT 1.2 V 10 A 1.5 Ω C3 5 SGND 22 nF R4 330 kΩ R5 10 kΩ C5 5.6 nF C9 1 µF 6 SS DBP 11 7 VFB Q2 Si7860DP C13 4.7 nF LDRV 10 8 COMP C4 470 pF + SW 12 PGND 9 PWP + C15 47 µF + C16 C17 C18 470 µF 470 µF 0.1 µF − D2 BAT54 R7 8.66 kΩ R3 12.1 kΩ C6 4.7 nF R8 226 Ω Note resistor across soft−start capacitor. Diode D2 for operation below −10°C VDG−03177 Figure 16. 500 kHz, 5 V to 1.2 V with Improved High-Side Gate Drive See Application Information section Boost Diodes. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS40070PWP NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40070 TPS40070PWPG4 NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40070 TPS40070PWPR NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40070 TPS40070PWPRG4 NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40070 TPS40071PWP NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40071 TPS40071PWPG4 NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40071 TPS40071PWPR NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40071 TPS40071PWPRG4 NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40071 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS40070PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS40071PWPR HTSSOP PWP 16 2000 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40070PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS40071PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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