Preliminary Datasheet R2A20112ASP Critical Conduction Mode Interleaved PFC Control IC R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Description The R2A20112A controls a boost converter to provide an active power factor correction. The R2A20112A adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Interleaving function improves ripple current on input or output capacitor by 180 degrees phase shift. Soft-star, the feedback loop short detection, two mode over-voltage-protection, over-current-protection, Over current ON/OFF timer protection for boost Diode short and slave ZCD open detection are built in the R2A20112A, and can constitute a power supply system of high reliability with few external parts. Features Absolute Maximum Ratings Supply voltage Vcc: 24 V Operating junction temperature Tjopr: –40 to +150°C Electrical Characteristics VREF output voltage Vref: 5.0 V 1.5% UVLO operation start voltage Vuvlh: 10.5 V 0.7 V UVLO operation shutdown voltage Vuvll: 9.3 V 0.5 V UVLO hysteresis voltage Hysuvl: 1.2 V 0.5 V Functions Boost converter control with critical conduction mode Interleaving control Soft start function for the reference voltage of Error Amp Two mode PFC output Over-voltage-protection Mode1: Dynamic OVP corresponding to a voltage rise by dynamic load change. Mode2: Static OVP corresponding to over-voltage in stable. PFC output Dynamic-under-voltage-protection (DUVP) Feedback loop open/short detection Master and Slave independence over-current-protection 280 s restart timer Slave ZCD signal open detection Over current ON/OFF timer protection for boost Diode short Package Pb-free SOP-16 Ordering Information Part No. R2A20112ASPW0 Package Name FP-16DAV R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Package Code PRSP0016DH-B Package Abbreviation SP Taping Abbreviation (Quantity) W (2,000 pcs/reel) Page 1 of 8 R2A20112ASP Preliminary Pin Arrangement ZCD-M 1 16 VCC ZCD-S 2 15 GD-M TM 3 14 PGND VREF 4 13 GD-S SGND 5 12 OCP-M RAMP 6 11 OCP-S RT 7 10 SS COMP 8 9 FB (Top view) Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name ZCD-M ZCD-S TM VREF SGND RAMP RT COMP FB SS OCP-S OCP-M GD-S PGND GD-M VCC R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Function Master converter zero current detection input terminal Slave converter zero current detection input terminal Over current ON/OFF timer protection terminal Reference voltage output terminal Signal Ground Ramp waveform setting terminal Oscillator frequency setting terminal Error amplifier output terminal Error amplifier input terminal Soft start time setting terminal Slave converter overcurrent detection terminal Master converter overcurrent detection terminal Slave converter Power MOSFET drive terminal Power Ground Master converter Power MOSFET drive terminal Supply voltage terminal Page 2 of 8 R2A20112ASP Preliminary Block Diagram 10μA 10μA Vref VREF: 5V ZCD COMP1 ZCD-M Clamp ON: 10.5V OFF: 9.3V – -0.1V ~ 4.5V VCC UVLO VCC + GD-M Vzcd_lo=1.3V 300mVhys ZCD-S ZCD COMP2 Clamp – -0.1V ~ 4.5V GD-S + Vref Vref 50μA 5μA OCP COMP1 Logic Hi: ON TM – + 5μA Vtm=3.6V – 2.2Vhys OCP COMP2 OCP-S + S-OCP 40μA OCP-M + M-OCP – 5μA VREF 0.3V VREF: 5V Stop GD GD Disable OVP BLOCK SGND SW COMP COMP Discharge FB – + RT Iramp Tstart Error Amp FB – + Vref Iramp Dynamic UVP Vfb=2.49V + – Vref Vfb ×0.93V 10μA SS UVL RAMP FBLOW RAMP Level shift 0.9V (Design SPEC) COMP PGND 4.3V R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Page 3 of 8 R2A20112ASP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Symbol Supply voltage GD terminal peak current VCC Ipk-gd GD terminal DC current Idc-gd ZCD terminal current Izcd RT terminal current Vref terminal current Vref terminal load capacitor Vref terminal voltage OCP terminal voltage Power dissipation Irt Iref Cref min Cref max Icomp Vt-group1 Vt-group2 Vt-ref Vt-ocp Pt Operating junction temperature Storage temperature Tj-opr Tstg COMP terminal current Terminal voltage Ratings –0.3 to +24 Unit V Notes –300 +1200 mA 3 –15 +60 mA +3 –3 –200 –5 1000 1 1 –0.3 to Vcc –0.3 to Vref –0.3 to Vref + 0.3 *–1 to Vref 1 mA –40 to +150 –55 to +150 °C °C A mA pF F mA V V V V W 4 5 6 7 8 Notes: 1. 2. 3. 4. 5. Rated voltages are with reference to the PGND terminal. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. RT terminal's resistor is fixed 33 k to GND. This is the rated voltage for the following pins: Nothing 6. This is the rated voltage for the following pins: FB, SS, RAMP, TM 7. Minus value is peak voltage. Do not impress the DC voltage of the minus. 8. ja = 120°C/W 2 This value is a thing mounting on 40 40 (thickness: 1.6 mm) [mm ], a glass epoxy board of wiring density 10%. R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Page 4 of 8 R2A20112ASP Preliminary Electrical Characteristics (Ta = 25°C, VCC = 12 V, RT = 33 k, RAMP = 820 pF, TM = 2.2 F, SS = 1.0 F, OCP = GND) Item Supply VREF Error amplifier Symbol Min Typ Max Unit Test Conditions UVLO turn-on threshold Vuvlh 9.8 10.5 11.2 V UVLO turn-off threshold Vuvll 8.8 9.3 9.8 V UVLO hysteresis Hysuvl 0.7 1.2 1.7 V Standby current Istby — 85 170 A Operating current Icc — 4.2 6.3 mA Output voltage Vref 4.925 5.00 5.075 V Line regulation Vref-line — 5 20 mV Isource = –1 mA Vcc = 10 V to 24 V Load regulation Vref-load — 5 20 mV Isource = –1 mA to –5 mA Temperature stability dVref — 80 — ppm/°C Feedback voltage Vfb 2.452 2.490 2.528 V FB-COMP short Input bias current Ifb –0.5 –0.3 –0.1 A Measured pin: FB 1 FB = 3 V * Open loop gain Av — 60 — dB * Upper clamp voltage Vclamp-comp 4.2 4.3 4.4 V FB = 2.0 V Low voltage Vl-comp — 0.1 0.3 V FB = 3.0 V Source current Isrc-comp — –120 — A FB = 1.5 V VCC = 8.9 V Isource = –1 mA Ta = –40 to +125°C * 1 1 COMP = 2.5 V * 1 — 330 — A FB = 3.5 V gm 120 200 290 s FB = 2.45V 2.55 V RAMP charge current at DUVP disable condition Ic-ramp1 –60 –50 –40 A FB = 2.4 V RAMP charge current at DUVP enable condition Ic-ramp2 –32 –25 –18 A FB = 2 V RAMP discharge current Id-ramp 7 15 29 mA RAMP = 1 V Low voltage Vl-ramp — 17 200 mV Isink = 100 A Phase delay Phase 160 180 200 deg On time ratio Ton-ratio 0 — 5 % FB = 2.5 V, COMP = 2 V 1, 2 * Sink current Isnk-comp Transconductance COMP = 2.5 V COMP = 2.5 V Ramp Slave control Notes: *1 Design spec *2 Tperiod (100μs) Ton-m (50μs) GD-M Tdelay Ton-s GD-S Tdelay × 360 [deg] Tperiod Ton-s Ton-ratio = 1 – × 100 [%] Ton-m Phase = R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Page 5 of 8 R2A20112ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, VCC = 12 V, RT = 33 k, RAMP = 820 pF, TM = 2.2 F, SS = 1.0 F, OCP = GND) Item Symbol Gate drive rise time Gate drive (GD-M & GD-S) tr-gd Gate drive fall time tf-gd Gate drive low voltage Min Typ Max Unit — 20 100 ns — 5 30 ns Test Conditions 90% FB-COMP short CL = 100 pF 10% tr 90% FB-COMP short CL = 100 pF tf Vol1-gd — 0.02 0.1 V Isink = 2 mA Vol2-gd — 0.01 0.2 V Isink = 1 mA, VCC = 5 V Gate drive high voltage Voh-gd 11.5 11.9 — V Isource = –2 mA * Over current OCP threshold voltage Vocp 0.27 0.30 0.33 V protection OCP source current Iocp –10 –5 –2.5 A 10% 1 OCP = 0 V (OCP-M & OCP-S ON/OFF timer ON/OFF timer threshold voltage Vtm 3.52 3.6 3.68 V protection for ON/OFF timer hysteresis Hys-tm 2.1 2.2 2.3 V Boost diode short Charge current Isrc-tm –54 –45 –36 A TM = 2 V, OCP-M = 1 V Discharge current at TM disable condition Isnk-tm1 36 45 54 A TM = 2 V Discharge current at TM enable condition Isnk-tm2 4.2 5 5.8 A TM = 5 V to 2 V PFC output Dynamic OVP threshold voltage Vdovp Vfb 1.035 Vfb 1.050 Vfb 1.065 V COMP = 2.5 V abnormality protection Static OVP threshold voltage Vsovp Vfb 1.075 Vfb 1.090 Vfb 1.105 V COMP = 2.5 V Static OVP hysteresis Hys-sovp 50 100 150 mV COMP = 2.5 V Dynamic UVP threshold voltage Vduvp — Vfb 0.930 Vfb 0.950 V FB low detect threshold voltage Vfblow 0.45 0.50 0.55 V COMP = 2.5 V FB low detect hysteresis Hysfblow 0.16 0.20 0.24 V COMP = 2.5 V Zero current Upper clamp voltage Vzcdh 4.0 4.5 5.0 V Isource = –3 mA detector Lower clamp voltage Vzcdl –0.5 –0.1 0.4 V Isink = 3 mA (ZCD-M & ZCD-S) ZCD low threshold voltage Vzcd-lo 0.9 1.3 1.6 V * 1 ZCD hysteresis Hyszcd 130 300 410 mV * 1 Input bias current Izcd –14 –10 –6 A 1.2 V < Vzcd < 2.5 V Slave ZCD open detect delay time tzcds — 100 — ms ZCD-S: OPEN 1 Gate drive 10 kHz * ZCD-S open detector COMP = 2.5 V * 1 Soft start Charge current Ic-ss –14 –10 –6 A SS = 3 V, FB = 1 V Restart Restart time delay Tstart 210 280 350 s ZCD-M = 10 k to GND 2 ZCD-S = 10 k to GND * Notes: *1 Design spec *2 ZCD-M Tstart (280μs) [ A period without ZCD-M trigger] Vzcd-lo (1.3V: provide 300mV hysteresis) GD-M Restart pulse width: 1μs (Design spec) R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Page 6 of 8 R2A20112ASP Preliminary System Diagram T1 220μ D1 PFC OUT (390Vdc, 400W) 3M 2μ 470μ (450V) Q1 + VRB1 0.02 From GD-M T2 220μ GND D2 Q2 From GD-S 33k 0.02 AUX 33k VCC ZCD-M 1μ GD-M To Q1 gate GD-S To Q2 gate ZCD-S OCP-M TM 200 1000p 2.2μ OCP-S 200 1000p VREF 0.1μ SGND R2A20112ASP RT FB 33k SS 1.0μ RAMP 470p COMP PGND 1μ 51k 820k 0.1μ R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 Page 7 of 8 R2A20112ASP Preliminary Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV D MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 9 c HE *2 E bp Index mark Terminal cross section Reference Symbol ( Ni/Pd/Au plating ) 1 Z 8 *3 e bp x M A L1 A1 θ S L y S Detail F R03DS0047EJ0100 Rev.1.00 Jul 21, 2011 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.34 0.40 0.20 2.20 0.46 0.15 0.20 0.25 0° 7.50 0.50 7.80 1.27 0.70 1.15 8° 8.00 0.12 0.15 0.80 0.90 Page 8 of 8 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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