Preliminary Datasheet R2A20124AFP/R2A20124ASP Synchronous Phase Shift Full-Bridge Control IC Series REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Description The R2A20124AFP/R2A20124ASP controls a full-bridge phase shift circuit and secondary synchronous rectification. The R2A20124AFP/R2A20124ASP has adjustable delay time functions which make ZVS of primary side and make loss of body diode of primary switching device minimal. The R2A20124AFP/R2A20124ASP is based on HA16163/R2A20121. And RAMP slope compensation circuit is builtin as an additional function. Also its output driver circuits are improved to enlarge gate drive output voltage swing from VREF to VCC. In addition R2A20124AFP has ON/OFF function of synchronous rectification and includes amplifier which detect input current signal. Features Maximum ratings Supply voltage Vcc: 20 V Operating junction temperature Tj-opr: –40 to +125°C Electrical characteristics VFB feedback voltage VFB(–): 1.25 V 2.0% UVLO (Under Voltage Lockout) operation start voltage VH: 8.4 V 0.7 V UVLO operation shutdown voltage VL: 8.0 V 0.6 V UVLO hysteresis voltage dVUVL: 0.4 V 0.1 V Output voltage swing of OUT-A, B, C, D, and E for gate drive: GND to VCC Functions R2A20124AFP/R2A20124ASP Full-bridge phase-shift switching circuit with adjustable delay times Pulse by pulse current limit Synchronization I/O for the oscillator Ramp sloping adjustor Error amplifier built-in Soft start function R2A20124AFP Synchronous rectification on/off control Remote on/off control Amplified output of current sense input voltage: CS Package lineup Pb-free LQFP-40: R2A20124AFP Pb-free SOP-20: R2A20124ASP Ordering Information Part No. R2A20124AFP-W0 R2A20124AFP-W5 R2A20124AFP-U0 R2A20124AFP-U5 R2A20124ASP-W0 R2A20124ASP-W5 R2A20124ASP-U0 R2A20124ASP-U5 REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Package Name FP-40EV Package Code PLQP0040JB-C FP-20DAV PRSP0020DD-B Taping Spec. 2000 pcs./one taping product 2000 pcs./one taping product — — 2000 pcs./one taping product 2000 pcs./one taping product — — Page 1 of 12 R2A20124AFP/R2A20124ASP Preliminary Modified Points from R2A20121SP The swing level of the maximum output voltage is changed from VREF to VCC. Ramp sloping compensation circuit is added. Synchronous rectification control is possible to turned off at light load. (only R2A20124AFP) On/off control terminal for Remote is added. (only R2A20124AFP) Illustrative Circuit VIN DC 12 V DC 12 V DC 12 V DC 12 V DC 12 V Vbias (DC 12 V) VCC OUT OUT -A -B CS RAMP RAMP -SLP OUT OUT -C -D OUT OUT -E -F SEC-CONT(∗1) REMOTE(∗1) COMP R2A20124AFP/ASP FB(–) VREF PGND SGND RT SYNC DELAY CS-1 SS OUT(∗1) DELAY -2 DELAY -3 Note: ∗1. Only R2A20124AFP REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Page 2 of 12 R2A20124AFP/R2A20124ASP Preliminary Pin Arrangement N.C. PGND RT SGND N.C. SYNC N.C. N.C. RAMP-SLP N.C. R2A20124AFP R2A20124ASP 30 29 28 27 26 25 24 23 22 21 31 20 OUT-A N.C. 32 19 OUT-B RAMP 18 OUT-C 34 17 OUT-D N.C. 35 16 N.C. COMP 36 15 N.C. FB(–) 37 14 OUT-E SS 38 13 OUT-F N.C. 39 12 N.C. N.C. 40 1 11 10 N.C. N.C.: Non-connection 8 9 VCC 7 N.C. 6 VREF 5 REMOTE DELAY-3 4 SEC-CONT 3 N.C. DELAY-2 2 N.C. 33 DELAY-1 CS CS-OUT (Top view) Outline: LQFP-40 (PLQP0040JB-C) REJ03D0928-0200 Rev.2.00 Aug 03, 2010 SYNC 1 20 RT RAMP-SLP 2 19 GND RAMP 3 18 OUT-A CS 4 17 OUT-B COMP 5 16 OUT-C FB(–) 6 15 OUT-D SS 7 14 OUT-E DELAY-1 8 13 OUT-F DELAY-2 9 12 VCC DELAY-3 10 11 VREF (Top view) Outline: SOP-20 (PRSP0020DD-B) Page 3 of 12 R2A20124AFP/R2A20124ASP Preliminary Pin Functions LQFP-40 Pin No. SOP-20 Pin No. Pin Name DELAY-1 Input/Output Input/Output Pin Function 1 8 Delay time adjustor for the full-bridge control signal (OUT-A and B) 2 9 DELAY-2 Input/Output Delay time adjustor for the full-bridge control signal (OUT-C and D) 4 10 DELAY-3 Input/Output Delay time adjustor for the secondary control signal (OUT-E and F) 5 — SEC-CONT Input Synchronous rectification on/off control 6 — REMOTE Input Remote on/off control 7 11 VREF Output 5 V/20 mA output 9 12 VCC Input IC power supply input 13 13 OUT-F Output Secondary control signal 14 14 OUT-E Output Secondary control signal 17 15 OUT-D Output Full-bridge control signal 18 16 OUT-C Output Full-bridge control signal 19 17 OUT-B Output Full-bridge control signal 20 18 OUT-A Output Full-bridge control signal 22 — PGND — Ground level for the output signal 23 — SGND — Ground level for the small signal — 19 GND — Ground 24 20 RT Input/Output Timing resistor for the oscillator 27 1 SYNC Input/Output Synchronization I/O for the oscillator 29 2 RAMP-SLP Input/Output Ramp sloping adjustor 31 3 RAMP Input Ramp waveform set 33 4 CS Input Current sense signal input for OCP 34 — CS-OUT Output Current sense information amplifier output 36 5 COMP Output Error amplifier output 37 6 FB(–) Input Error amplifier negative input 38 7 SS Output Timing capacitor for soft start 3, 8, 10 to 12, 15, 16, 21, 25, 26, 28, 30, 32, 35, 39, 40 — N.C. — Open REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Page 4 of 12 R2A20124AFP/R2A20124ASP Preliminary Block Diagram R2A20124AFP VCC H VREF L 5V GENERATOR UVLO VREF VREF H GOOD L 40 μA REMOTE ON: 1.32 V OFF: 1.23 V CIRCUIT BIAS VREF START-UP COUNTER 32 CLOCK RT VREF GOOD VCC OSCILLATOR RES SYNC OUT-A Q SYNC I/O DELAY-1 VREF GOOD FB(–) VCC ERROR VREF AMP 500 μA OUT-B DELAY Control Circuit 1.25 V VCC OUT-C COMPARATOR DELAY-2 COMP VCC 1.135 V RAMP OUT-D RES VREF Phase Shift Control Logic RAMP-SLP Zero Delay CLAMP CIRCUIT VREF DELAY-3 VCC DELAY Control Circuit 4V 10 μA OUT-E Synchronous Rectification Control Logic SS VCC OUT-F VREF GOOD ×3.0 CS-OUT PULSE BY PULSE 1.15 V CS 1.4 V RES heavy load SEC-CONT 2.5 kΩ 185 kΩ 10 μA SGND REJ03D0928-0200 Rev.2.00 Aug 03, 2010 PGND Page 5 of 12 R2A20124AFP/R2A20124ASP Preliminary R2A20124ASP VCC H UVLO L 5V GENERATOR VREF VREF H GOOD L START-UP COUNTER 32 CLOCK VREF CIRCUIT BIAS VREF GOOD RT VCC OUT-A OSCILLATOR RES SYNC Q SYNC I/O DELAY-1 VCC VREF GOOD FB(–) OUT-B ERROR VREF AMP 500 μA DELAY Control Circuit VCC 1.25 V OUT-C DELAY-2 COMPARATOR VCC COMP 1.135 V OUT-D RAMP RES VREF Phase Shift Control Logic RAMP-SLP Zero Delay DELAY-3 CLAMP CIRCUIT VREF VCC DELAY Control Circuit 4V 10 μA OUT-E Synchronous Rectification Control Logic VCC OUT-F SS VREF GOOD PULSE BY PULSE CS 1.4 V RES GND REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Page 6 of 12 R2A20124AFP/R2A20124ASP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power supply voltage Peak output current DC output current VREF output current COMP sink current DELAY set current RT set current RAMP-SLP set current VREF terminal voltage Terminal group 1 voltage Operating junction temperature Storage temperature Symbol Vcc Ipk-out Idc-out Iref-out Isink-comp Iset-delay Iset-rt Iset-ramp-slp Vter-ref Vter-1 Tj-opr Tstg Ratings 20 200 50 –20 2 0.3 0.3 0.3 –0.3 to +6 –0.3 to (Vref + 0.3) –40 to +125 –55 to +150 Unit V mA mA mA mA mA mA mA V V °C °C Note 1 2, 3 3, 4 3 3 3 3 3 1, 5 1, 6 7 Notes: 1. 2. 3. 4. 5. 6. Rated voltages are with reference to the GND or SGND pin. The Rating shows the transient current when driving a capacitive load. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Total current of OUT-A, Out-B, OUT-C, OUT-D, OUT-E, and OUT-F must be not exceed 90 mA. VREF pin voltage must not exceed VCC pin voltage. Terminal group 1 is defined the pins; REMOTE, RAMP-SLP, SEC-CONT, CS, RAMP, COMP, CS-OUT, FB(–), SS, RT, SYNC, and DELAY-1 to 3 7. Theramal resistance ja R2A20124AFP (40-pin); 85.3°C/W Board condition; Glass epoxy 50 mm 50 mm 1.6 mm, 10% wiring density. R2A20124ASP (20-pin); 120°C/W Board condition; Glass epoxy 40 mm 40 mm 1.6 mm, 10% wiring density. REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Page 7 of 12 R2A20124AFP/R2A20124ASP Preliminary Electrical Characteristics (Ta = 25°C, Vcc = 12 V, RT = 180 k, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.) Item Symbol Min Typ Max Unit 7.7 8.4 9.1 V Test Conditions SUPPLY: R2A20124AFP/ASP Start threshold VH Shutdown threshold VL 7.4 8.0 8.6 V UVLO hysteresis dVUVL 0.3 0.4 0.5 V Start-up current Is — 90 150 A Vcc = 7.5 V Operating current Icc — 8 11.5 mA No load on VREF pin Vref 4.9 5.0 5.1 V VREF: R2A20124AFP/ASP Output voltage Line regulation Vref-line — 0 10 mV Vcc= 10 V to 16 V Load regulation Vref-load — 6 20 mV Iref= –1 mA to –20 mA Temperature stability dVref/dTa — 80*1 — ppm/°C Oscillator frequency fosc — 200*1 — kHz Switching frequency fsw Line stability fsw-line Temperature stability RT voltage Ta = –40°C to 105°C OSCILLATOR: R2A20124AFP/ASP 85 100 115 kHz –1.5 0 1.5 % Measured on OUT-A, -B dfsw/dTa — 0.1*1 — %/°C VRT 2.5 2.7 2.9 V Input threshold VTH-SYNC 2.5 2.85 3.2 V Output high VOH-SYNC 3.5 4.0 — V RSYNC = 33 k to GND *2 Output low VOL-SYNC — 0.05 0.15 V RSYNC = 33 k to VREF Minimum input pulse TI-MIN 50 — — ns Output pulse width TO-SYNC — 3.0*1 — s Vcc = 10 V to 16 V Ta = –40°C to 105°C SYNC: R2A20124AFP/ASP REMOTE: R2A20124AFP On threshold voltage VON-REMOTE 1.12 1.32 1.52 V Off threshold voltage VOFF-REMOTE 1.04 1.23 1.42 V REMOTE hysteresis dVREMOTE Input bias current IREMOTE 60 90 120 mV –100 –50 — A REMOTE = 2 V ERROR AMPLIFIER: R2A20124AFP/ASP FB(–) input voltage VFB(–) 1.225 1.250 1.275 V FB(–) and COMP are shorted FB(–) input current IFB(–) –2.0 0 2.0 A FB(–) = 1.25 V Open-loop DC gain Av — 80*1 — dB Unity gain bandwidth BW Output source current ISOURCE Output sink current ISINK 2.0 Output high voltage VOH-EO 3.7 VOL-EO — –0.16 Output low voltage Output clamp voltage * 3 VCLAMP-EO 1 — 2* –650 –500 — MHz –390 A 6.5 — mA FB(–) = 1.75 V, COMP = 2 V 3.9 — V FB(–) = 0.75 V, COMP; open 0.1 0.4 V FB(–) = 1.75 V, COMP; open –0.07 0.0 V FB(–) = 0.75 V, COMP; open, SS = 1 V FB(–) = 0.75 V, COMP = 2 V Notes: 1. Design specification (reference data) 2. R2A20124AFP: SGND and PGND 3. VCLAMP-EO = VCOMP – SS voltage (1 V) REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Page 8 of 12 R2A20124AFP/R2A20124ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 180 k, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.) Item Symbol Min Typ Max Unit Test Conditions VRAMP 1.035 1.135 1.235 V RAMP source current Isource-RAMP –220 –185 –150 A RAMP = 0.15 V, COMP; open RAMP sink current ISINK-RAMP 3 10 — mA RAMP = 0.15 V, COMP = 0 V Minimum phase shift Dmin — 0*1*4 — % PHASE MODULATOR: R2A20124AFP/ASP RAMP offset voltage 1 4 RAMP = 0 V, COMP = 0 V Maximum phase shift Dmax — 97.0* * — % RAMP = 0 V, COMP = 2.1 V Delay to OUT-C, -D *2 Tpd — 100 200 ns COMP = 1.6 V RAMP discharge time *1 Tdis — 80 120 ns FB(–) = 0.75 V, COMP; open RAMP-SLP voltage VRAMP-SLP 2.1 2.3 2.5 V DELAY-1, -2 *3 TD1, 2 70 100 130 ns DELAY-3 *3 TD3 45 65 85 ns Delay set R = 51 k DELAY2-1, -2 *1*3 TD2_1, _2 140 220 300 ns Delay set R = 180 k DELAY2-3 *1*3 TD2_3 110 170 230 ns Delay set R = 180 k Terminal voltage VD1, 2, 3 1.9 2.0 2.1 V Delay set R = 51 k Source current ISS –14 –10 –6 A SS high voltage VOH-SS 3.9 4.0 4.1 V DELAY: R2A20124AFP/ASP Delay set R = 51 k SOFT START: R2A20124AFP/ASP SS = 1 V Notes: 1. Design specification (reference data) 2. Tpd is defined as; 1V RAMP 50% 0V OUT-C/D VCC 0V 50% Tpd 3. TD1, TD2, and TD3 are defined as; TD1 TD1 OUT-A 50% OUT-B For primary control OUT-C TD2 TD2 OUT-D OUT-E For secondary control TD3 OUT-F TD3 4. Maximum/Minimum phase shift is defined as; T2 D= × 2 × 100 (%) T1 OUT-A OUT-B T2 OUT-D T2 OUT-C T1 REJ03D0928-0200 Rev.2.00 Aug 03, 2010 T1 Page 9 of 12 R2A20124AFP/R2A20124ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 180 k, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.) Item Symbol Min Typ Max Unit Test Conditions OVER CURRENT PROTECTION: R2A20124AFP/ASP Pulse-by-pulse current limit threshold VCS-PP 1.26 1.4 1.54 V SEC-CONT = 0.3 V (AFP) Delay to OUT pins *1 Tpd-cs — 100 200 ns CS = 0 V to 1.57 V, SEC-CONT = 0.3 V (AFP) CS sink current ISINK-CS 2 5 — mA CS = 0.15 V, COMP = 0 V High voltage VOH-OUT 11.5 11.9 — V IOUT = –2 mA Low voltage VOL-OUT — 0.05 0.2 V IOUT = 2 mA Rise time tr — 30 100 ns COUT = 100 pF Fall time tf — 30 100 ns COUT = 100 pF Timing offset *2 TD4 — 20 140 ns 15 20 25 s CS = 0.4 V OUTPUT: R2A20124AFP/ASP POWER INFORMATION AMPLIFIER: R2A20124AFP Tranceconductance gm SECONDARY CONTROL: R2A20124AFP Forced synchronous rectification on voltage Von-sec-cont 4.6 — — V CS = 1 V Forced synchronous rectification off voltage Voff-sec-cont — — 0.4 V CS = 0 V Input bias current-1 ISEC-CONT1 5 10 20 A CS = 0 V, SEC-CONT = 2.1 V Input bias current-2 ISEC-CONT2 10 20 40 A CS = 1 V, SEC-CONT = 2.1 V Current hysteresis dISEC-CONT 5 10 20 A Notes: 1. Tpd-cs is defined as; 1.57 V CS 0 50% 50% OUT-C/D Tpd-cs 2. TD4 is defined as; 50% OUT-D OUT-C OUT-E 50% TD4 REJ03D0928-0200 Rev.2.00 Aug 03, 2010 50% OUT-F 50% TD4 Page 10 of 12 R2A20124AFP/R2A20124ASP Preliminary Timing Diagram Note: All voltage, current, time shown in the diagram is typical value. • Full Bridge and Secondary Control: R2A20124AFP/ASP TD1 OUT-A TD1 OUT-B TD2 OUT-C TD2 OUT-D TD3 OUT-E TD3 OUT-F • Full Bridge and Secondary Control: R2A20124AFP (SEC-CONT > 4.6 V) TD1 OUT-A TD1 OUT-B TD2 OUT-C TD2 OUT-D OUT-E Low-fixed OUT-F Low-fixed VIN OUT-A DRIVE MA MC DRIVE OUT-C OUT-B DRIVE MB MD DRIVE OUT-D DRIVE RAMP OUT-E ME MF DRIVE OUT-F External Power Stage REJ03D0928-0200 Rev.2.00 Aug 03, 2010 Page 11 of 12 R2A20124AFP/R2A20124ASP Preliminary Package Dimensions JEITA Package Code P-LQFP40-7x7-0.65 RENESAS Code PLQP0040JB-C Previous Code FP-40EV MASS[Typ.] 0.2g HD *1 D 30 21 31 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 20 c HE *2 E bp ZE Terminal cross section ( Ni/Pd/Au plating ) 11 40 Reference Dimension in Millimeters Symbol Min D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 10 1 Index mark c A F A2 ZD θ A1 L L1 Detail F e *3 bp x M y JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV 0.10 0.15 0.20 0° 8° 0.65 0.13 0.10 0.575 0.575 0.40 0.50 0.60 1.0 MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 Nom Max 7.0 7.0 1.40 8.8 9.0 9.2 8.8 9.0 9.2 1.70 0.08 0.13 0.22 0.17 0.22 0.27 11 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 10 1 Z e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F REJ03D0928-0200 Rev.2.00 Aug 03, 2010 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Page 12 of 12 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. 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