SSM6J412TU TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ) SSM6J412TU ○ Power Management Switch Applications 2.1±0.1 1.5-V drive Low ON-resistance: RDS(ON) = 99.6 mΩ (max) (@VGS = -1.5 V) RDS(ON) = 67.8 mΩ (max) (@VGS = -1.8 V) RDS(ON) = 51.4 mΩ (max) (@VGS = -2.5 V) RDS(ON) = 42.7 mΩ (max) (@VGS = -4.5 V) Symbol Rating Unit Drain-source voltage VDSS -20 V Gate-source voltage VGSS ±8 V DC Drain current Pulse ID -4.0 IDP (Note 1) 5 3 4 +0.1 0.3-0.05 2 A -16.0 PD (Note 2) Power dissipation 6 +0.06 0.16-0.05 Characteristic 1 0.7±0.05 Absolute Maximum Ratings (Ta = 25°C) 0.65 0.65 1.3±0.1 1.7±0.1 2.0±0.1 • • Unit: mm 1 W Channel temperature Tch 150 °C Storage temperature range Tstg −55 to 150 °C UF6 1,2,5,6: Drain 3: Gate 4: Source JEDEC ― Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in JEITA ― temperature, etc.) may cause this product to decrease in the TOSHIBA 2-2T1D reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the Weight : 7.0mg ( typ. ) absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: Pw ≤ 10μs, Duty. ≤ 1% Note 2: Mounted on a FR4 board. (25.4 mm × 25.4 mm × 1.6 mm , Cu Pad: 645 mm2) Marking (Top View) 6 5 Equivalent Circuit 4 6 5 4 3 1 2 3 KPH 1 2 1 2010-12-08 SSM6J412TU Electrical Characteristics (Ta = 25°C) Characteristic Drain-source breakdown voltage Symbol Test Conditions Min Typ. Max Unit -20 ⎯ ⎯ V -15 ⎯ ⎯ V ⎯ ⎯ -1 μA V (BR) DSS ID = -1 mA, VGS = 0 V V (BR) DSX ID = -1 mA, VGS = 5 V (Note 4) Drain cut-off current IDSS Gate leakage current IGSS VGS = ±8 V, VDS = 0 V ⎯ ⎯ ±1 μA Vth VDS = -3 V, ID = -1 mA -0.3 ⎯ -1.0 V S Gate threshold voltage ⏐Yfs⏐ Forward transfer admittance Drain–source ON-resistance RDS (ON) Input capacitance Ciss Output capacitance Coss VDS = -3 V, ID = -1.0 A (Note 3) 4.5 9.1 ⎯ ID = -3.0 A, VGS = -4.5 V (Note 3) ⎯ 36.9 42.7 ID = -2.5 A, VGS = -2.5 V (Note 3) ⎯ 42.8 51.4 ID = -1.5 A, VGS = -1.8 V (Note 3) ⎯ 50.6 67.8 ID = -0.5 A, VGS = -1.5 V (Note 3) ⎯ 58.6 99.6 VDS = -10 V, VGS = 0 V f = 1 MHz ⎯ 840 ⎯ ⎯ 118 ⎯ ⎯ 99 ⎯ Turn-on time ton VDD = -10 V, ID = -2.0 A ⎯ 32 ⎯ Turn-off time toff VGS = 0 to -2.5 V, RG = 4.7 Ω ⎯ 107 ⎯ ⎯ 12.8 ⎯ ⎯ 1.4 ⎯ Reverse transfer capacitance Switching time VDS = -20 V, VGS = 0 V Crss Total gate charge Qg Gate-source charge Qgs1 Gate-drain charge Qgd Drain-source forward voltage VDSF VDD = -10 V, ID = -4.0 A, VGS = -4.5 V ID = 4.0 A, VGS = 0 V (Note 3) ⎯ 3.0 ⎯ ⎯ 0.88 1.2 mΩ pF ns nC V Note 3: Pulse test Note 4: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain-source breakdown voltage is lowered in this mode. Switching Time Test Circuit (a) Test Circuit (b) VIN 0V 90% OUT 0 IN 10% −2.5 V RG −2.5V 10 μs RL (c) VOUT VDS (ON) 90% VDD VDD = -10 V RG = 4.7 Ω Duty ≤ 1% VIN: tr, tf < 5 ns Common Source Ta = 25°C 10% VDD tr ton tf toff Notice on Usage Vth can be expressed as the voltage between gate and source when the low operating current value is ID = -1 mA for this product. For normal switching operation, VGS (on) requires a higher voltage than Vth and VGS (off) requires a lower voltage than Vth. (The relationship can be established as follows: VGS (off) < Vth < VGS (on).) Take this into consideration when using the device. Handling Precaution When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. Thermal resistance Rth (ch-a) and power dissipation PD vary depending on board material, board area, board thickness and pad area. When using this device, please take heat dissipation into consideration 2 2010-12-08 SSM6J412TU ID – VDS -10 VGS =-4.5 V ID – VGS -100 -2.5 V Common Source -1.8 V -1 ID Drain current Drain current -4 -2 Common Source Ta = 25 °C Pulse test 0 -0.2 -0.6 -0.4 -0.8 Drain–source voltage VDS Pulse test (A) (A) ID -1.5 V -6 0 VDS = -3 V -10 -8 -0.1 Ta = 100 °C 25 °C -0.001 -0.0001 0 -1 -0.5 (V) Drain–source ON-resistance RDS (ON) (mΩ) Drain–source ON-resistance RDS (ON) (mΩ) Ta = 100 °C 25 °C 40 20 − 25 °C 0 -4 -2 Gate–source voltage -6 VGS 100 80 60 20 − 25 °C 0 (V) -2 Pulse test Drain–source ON-resistance RDS (ON) (mΩ) Drain–source ON-resistance RDS (ON) (mΩ) 120 VGS = -1.5 V 80 -1.8 V 60 -2.5 V 40 -4.5 V 20 0 0 -2.0 -4.0 -6.0 Drain current ID -6 VGS -8 (V) RDS (ON) – Ta Common Source Ta = 25°C 100 -4 Gate–source voltage 140 120 25 °C 40 0 -8 Ta = 100 °C RDS (ON) – ID 140 (V) ID =-2.5A Common Source Pulse test 120 80 0 VGS -2.0 RDS (ON) – VGS 100 60 -1.5 140 ID =-0.5A Common Source Pulse test 120 -1.0 Gate–source voltage RDS (ON) – VGS 140 −25 °C -0.01 -8.0 100 80 -1.5 A / -1.8 V ID = -0.5 A / VGS = -1.5 V -2.5 A / -2.5 V 60 40 -3.0 A / -4.5 V 20 0 −50 -10.0 Common Source Pulse test 0 50 Ambient temperature (A) 3 100 Ta 150 (°C) 2010-12-08 SSM6J412TU Vth – Ta -0.6 -0.4 -0.2 0 50 100 Ambient temperature VDS = -3 V Ta = 25 °C Ta 150 0.1 -0.01 -0.1 -1 -10 ID -100 (A) Dynamic Input Characteristic (V) Ciss Coss 300 100 50 Common Source 30 Ta = 25 °C f = 1 MHz VGS = 0 V Crss -1 -10 Drain–source voltage -100 VDS VDD = -16 V -4 -2 Common Source ID = -4.0 A Ta = 25 °C 10 (A) 10 IDR t 100 ton 10 tr -0.1 Drain current Qg 30 (nC) Common Source VGS = 0 V Ta = 25 °C D Pulse test IDR G S 1 0.1 25 °C 0.01 100 °C -0.01 20 IDR – VDS 100 Drain reverse current tf 0 Total Gate Charge Common Source VDD = -10 V VGS = 0 to -2.5 V Ta = 25 °C RG = 4.7Ω toff VDD = -10 V (V) t – ID 10000 1 -0.001 -6 0 10 -0.1 1000 0.3 -8 VGS Capacitance 500 1.0 Drain current Gate–source voltage (pF) C 1000 3.0 (°C) 5000 3000 10 C – VDS 10000 (ns) 30 Common Source Pluse test 0 −50 Switching time (S) -0.8 100 Forward transfer admittance Vth (V) Gate threshold voltage Common Source VDS = -3 V ID = -1 mA ⎪Yfs⎪ |Yfs| – ID -1.0 -1 ID 0.001 0 -10 0.2 −25 °C 0.4 0.6 Drain–source voltage (A) 4 0.8 VDS 1.0 1.2 (V) 2010-12-08 SSM6J412TU PD – Ta 1.25 600 Mounted on FR4 board (25.4mm × 25.4mm × 1.6mm , Cu Pad : 645 mm2) DC Power dissipation PD (W) Transient thermal impedance Rth (°C/W) Rth – tw 100 10 1.0 0.75 0.5 0.25 Single pulse Mounted on FR4 board 1 0.001 2 (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm ) 0.01 0.1 1 Pulse Width 10 100 0 -40 1000 tw (s) -20 0 20 40 60 80 Ambient temperature 5 100 120 140 Ta (°C) 160 2010-12-08 SSM6J412TU RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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