SMMS713 − JUNE 1998 D Organization: D D D D SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 (LVTTL) Interface D Read Latencies 2 and 3 Supported D Supports Burst-Interleave and D D D D D D Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Four Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0°C to 70°C Gold-Plated Contacts Pipeline Architecture Serial Presence-Detect (SPD) Using EEPROM REFRESH INTERVAL tREF ’8TU72JPW-8 8 ns 10 ns 6 ns 6 ns 64 ms ’8TU72JPW-8A 8 ns 10 ns 6 ns 7.5 ns 64 ms description The TM8TU72JPW is a 64M-byte, 168-pin registered dual-in-line memory module (DIMM). The registered DIMM is composed of nine TMS664814DGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP); two SN74ALVC162836DGG, 20-bit universal bus drivers, each in a 240-mil, 56-pin thin shrink small-outline package (TSSOP); and one CDC2510 phase-lock loop (PLL) in a 177-mil, 24-pin TSSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695), the SN74ALVC162836 data sheet (literature number SCES129), and the CDC2510 data sheet (literature number SCAS597) for reference. operation The TM8TU72JPW operates as nine TMS664814DGE devices that are connected as shown in the TM8TU72JPW functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated !" #$%" &! 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(& &(! $"%! &!"! #$%" ,&% !* POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1 PRODUCT PREVIEW D D Byte-Read/Write Capability D High-Speed, Low-Noise, Low-Voltage TTL − TM8TU72JPW . . . 8 388 608 × 72 Bits Designed for 100-MHz, 72-Bit 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) With Register for Use With Socket TM8TU72JPW — Uses Nine 64M-Bit (8M × 8-Bit) SDRAMs in Plastic Thin Small-Outline Package (TSOP), Two SN74ALVC162836 20-Bit Universal Bus Drivers in Thin Shrink Small-Outline Package (TSSOP), and One CDC2510 Phase-Lock Loop (PLL) in TSSOP Single 3.3-V Power Supply (±10% Tolerance) Performance Ranges: SMMS713 − JUNE 1998 DUAL-IN-LINE MEMORY MODULE ( TOP VIEW ) TM8TU72JPW ( SIDE VIEW ) PIN NOMENCLATURE A[0:11] A[0:8] A13/BA0 A12/BA1 CAS CB[0:7] CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] 1 10 11 NC RAS REGE S[0:3] SA[0:2] PRODUCT PREVIEW SCL SDA VDD VSS WE WP 40 41 84 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Row-Address Inputs Column-Address Inputs Bank-Select Zero Bank-Select One Column-Address Strobe Check-Bit In/Check-Bit Out Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Register Enable Chip Select Serial Presence-Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable Write Protect SMMS713 − JUNE 1998 Pin Assignments NAME NO. 1 VSS DQ0 43 2 3 DQ1 4 DQ2 5 6 PIN NAME NO. PIN NAME NO. PIN NAME VSS NC 85 VSS DQ32 127 86 45 S2 87 DQ33 129 S3 46 DQMB2 88 DQ34 130 DQMB6 DQ3 47 DQMB3 89 DQ35 131 DQMB7 VDD DQ4 48 NC 90 NC 49 91 133 8 DQ5 50 VDD NC VDD DQ36 132 7 92 DQ37 134 VDD NC 44 128 VSS CKE0 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 54 97 VSS DQ41 138 55 VSS DQ16 96 13 VSS DQ9 139 VSS DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 101 DQ45 143 18 60 102 VDD DQ52 61 NC 103 VDD DQ46 144 19 VDD DQ14 VDD DQ20 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 CB0 63 CKE1 105 CB4 147 REGE 22 CB1 64 106 CB5 148 23 65 107 VSS DQ53 66 DQ22 108 VSS NC 149 24 VSS NC VSS DQ21 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 68 111 VDD CAS 152 69 VSS DQ24 110 27 VDD WE 153 VSS DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 S0 72 DQ27 114 S1 156 DQ59 31 NC 73 115 RAS 157 32 74 116 158 75 DQ29 117 VSS A1 VDD DQ60 33 VSS A0 VDD DQ28 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 120 A7 162 37 A8 79 VSS CK2 121 A9 163 VSS CK3 38 A10 80 NC 122 A13/BA0 164 NC 39 A12/BA1 81 WP 123 A11 165 SA0 40 82 SDA 124 SA1 83 SCL 125 VDD CK1 166 41 VDD VDD 167 SA2 42 CK0 84 VDD 126 NC 168 VDD POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PRODUCT PREVIEW PIN NO. 3 SMMS713 − JUNE 1998 dual-in-line memory module and components The dual-in-line memory module and components include: PRODUCT PREVIEW D PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage D Bypass capacitors: Multilayer ceramic D Contact area: Nickel plate and gold plate over copper 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMMS713 − JUNE 1998 functional block diagram for the TM8TU72JPW RS0 R CS RDQMB0 DQM R 8 DQ[0:7] CK1 CS U0 RDQMB4 DQM R DQ[0:7] DQ[32:39] 8 C U5 R DQ[0:7] CK2 C CS DQM R 8 U1 RDQMB5 DQM R DQ[0:7] DQ[40:47] 8 R U6 DQM R 8 CB[0:7] R = 10 Ω C = 10 pF U2 DQ[0:7] RS2 VDD CS RDQMB2 DQM R 8 DQ[16:23] U3 RDQMB6 DQM R DQ[0:7] DQ[48:55] 8 RDQMB3 DQM R 8 DQ[24:31] S0/S2 DQMB[0:7] BA[0:1] A[0:11] RAS CAS CKE0 WE 10 kΩ VSS U[0:8] CS U4 RDQMB7 DQM R DQ[0:7] Register U7 DQ[0:7] U[0:8] One 0.0022 µF and one 0.22 µF per SDRAM CS CS VDD C DQ[0:7] CS RDQMB1 CK3 PRODUCT PREVIEW RDQMB1 DQ[8:15] CS DQ[56:63] 8 U8 DQ[0:7] SPD EEPROM SCL RS0/RS2 SDA WP RDQMB[0:7] A0 A1 A2 RBA[0:1] → BA[0:1]: SDRAMs U[0:8] RA[0:11] → A[0:11]: SDRAMs U[0:8] SA0 SA1 SA2 47 kΩ RRAS → RAS: SDRAMs U[0:8] RCAS → CAS: SDRAMs U[0:8] RCKE0 → CKE: SDRAMs U[0:8] VDD RWE → WE: SDRAMs U[0:8] PCK1: U0, U1, U5 10 kΩ PCK2: U2, U6, U7 PLL PCK3: U3, U4, U8 CK0 PCK4 PCK4: Register REGE LEGEND: CS = Chip Select SPD = Serial Presence Detect PLL = Phase-Lock Loop POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 SMMS713 − JUNE 1998 absolute maximum ratings over ambient temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. PRODUCT PREVIEW recommended operating conditions MIN NOM MAX UNIT 3 3.3 3.6 V VDD VSS Supply voltage VIH VIH-SPD High-level input voltage 2 High-level input voltage for SPD device 2 VIL TA Low-level input voltage Supply voltage 0 Ambient temperature V VDD + 0.3 5.5 V V −0.3 0.8 V 0 70 °C capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER MIN MAX UNIT Ci(CK) Input capacitance, CK input 38 pF Ci(AC) Input capacitance, address and control inputs: A0 −A13, RAS, CAS, WE 10 pF Ci(CKE) Input capacitance, CKE input 10 pF Co Output capacitance 15 pF Ci(DQMBx) Input capacitance, DQMBx input 10 pF Ci(Sx) Input capacitance, Sx input 9 pF Ci/o(SDA) SDA Input/output capacitance 12 pF Ci(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs 10 pF NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMMS713 − JUNE 1998 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3) ’8TU72JPW-8 VOH VOL High-level output voltage Low-level output voltage TEST CONDITIONS IOH = − 2 mA IOL = 2 mA MIN MAX 2.4 ’8TU72JPW-8A MIN MAX 2.4 V 0.4 0.4 V "10 "10 µA µA II Input current (leakage) 0 V ≤ VI ≤ VDD + 0.3 V, All other pins = 0 V to VDD IO Output current (leakage) 0 V ≤ VO ≤ VDD + 0.3 V, Output disabled "10 "10 CAS latency = 2 TBD TBD Operating current Burst length = 1, tRC ≥ tRC MIN, IOH/IOL = 0 mA (see Notes 4, 5, and 6) CAS latency = 3 TBD TBD ICC1 UNIT mA ICC2P Precharge standby current in power-down mode CKE ≤ VIL MAX, tCK = 15 ns (see Note 7) TBD TBD mA ICC2N Active standby current in non-power-down mode CKE ≥ VIH MIN, tCK = 15 ns (see Note 7) TBD TBD mA ICC3P Active standby current in power-down mode CKE ≤ VIL MAX, tCK = 15 ns (see Notes 4 and 7) TBD TBD mA ICC3N Precharge standby current in non-power-down mode CKE ≥ VIH MIN, tCK = 15 ns (see Notes 4 and 7) TBD TBD mA CAS latency = 2 TBD TBD Burst current Page burst, IOH/IOL = 0 mA All banks activated, nCCD = one cycle (see Notes 9 and 10) CAS latency = 3 TBD TBD CAS latency = 2 TBD TBD mA CAS latency = 3 TBD TBD mA ICC4 ICC5 Auto-refresh current tRC ≤ tRC MIN (see Notes 5 and 8) PRODUCT PREVIEW PARAMETER mA ICC6 Self-refresh current CKE ≤ VIL MAX TBD TBD mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC ≥ tRCMIN 6. Control and address inputs change state twice during tRC. 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change state once every cycle. 10. Continuous burst access, nCCD = 1 cycle POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 7 SMMS713 − JUNE 1998 ac timing requirements†‡ ’8TU72JPW-8 PRODUCT PREVIEW MIN ’8TU72JPW-8A MAX MAX Cycle time, CK CAS latency = 2 Cycle time, CK CAS latency = 3 tCH tCL Pulse duration, CK high (input clock duty cycle) 60 % tAC2 tAC3 Access time, CK high to data out (see Note 11) CAS latency = 2 6 7.5 ns Access time, CK high to data out (see Note 11) CAS latency = 3 6 6 ns tOH tLZ Hold time, CK high to data out with 50-pF load 3 3 ns Delay time, CK high to DQ in low-impedance state (see Note 12) 1 1 ns tHZ tIS Delay time, CK high to DQ in high-impedance state (see Note 13) tIH tRAS Hold time, address, control, and data input Setup time, address, control, and data input 15 UNIT tCK2 tCK3 Pulse duraction, CK low (input clock duty cycle) 10 MIN 8 ns 8 40 60 40 40 60 40 8 2 1 ns 60 8 % ns 2 ns 1 ns 48 ns 68 68 ns Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 14) 20 20 ns Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 20 20 ns tRRD tRSA Delay time, ACTV command in one bank to ACTV command in the other bank 16 16 ns 16 ns tAPR tAPW Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command tT Transition time tREF Refresh interval nCCD Delay time, READ or WRT command to an interrupting command 1 nCDD nCESP Delay time, CS low or high to input enabled or inhibited 0 Power down/self-refresh exit time 1 nCLE nCWL Delay time, CKE high or low to CLK enabled or disabled 1 Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P 1 nDID nDOD Delay time, ENBL or MASK command to enabled or masked data in 0 0 0 0 cycles Delay time, ENBL or MASK command to enabled or masked data out 2 2 2 2 cycles Delay time, ACTV command to DEAC or DCAB command 48 tRC Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command tRCD tRP Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command 100 000 16 tRP −(CL−1)*tCK tRP + 1 tCK 1 5 tRP − (CL−1)* tCK tRP + 1 tCK 1 64 0 5 ms ms cycles 0 1 1 1 ns 64 1 0 ns cycles cycles 1 1 cycles cycles nHZP2 Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 2 2 2 cycles nHZP3 Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 3 3 3 cycles nWCD Delay time, WRT command to first data in 0 cycles 0 0 0 nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 1 cycles † All references are made to the rising transition of CK unless otherwise noted. ‡ Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMMS713 − JUNE 1998 serial presence detect The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 1 − TM8TU72JPW Table 1. Serial Presence-Detect Data for the TM8TU72JPW DESCRIPTION OF FUNCTION TM8TU72JPW-8A ITEM DATA ITEM DATA 0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM, . . .) SDRAM 04h SDRAM 04h 3 Number of row addresses on this assembly 12 0Ch 12 0Ch 4 Number of column addresses on this assembly 9 09h 9 09h 5 Number of module rows on this assembly 1 bank 01h 1 bank 01h 6 Data width of this assembly 72 bits 48h 72 bits 48h 7 Data width continuation 8 Voltage interface standard of this assembly 9 SDRAM cycle time at maximum supported CAS latency (CL), CL = X 10 SDRAM access from clock at CL = X 11 DIMM configuration type (non-parity, parity, error-correcting code [ECC]) 12 Refresh rate / type 13 14 15 Minimum clock delay, back-to-back random column addresses 16 17 18 CAS latencies supported 19 CS latency 20 Write latency 21 00h 00h LVTTL 01h LVTTL 01h tCK = 8 ns tAC = 6 ns 80h 80h 60h tCK = 8 ns tAC = 6 ns ECC 02h ECC 02h 15.6 µs/ self-refresh 80h 15.6 µs/ self-refresh 80h SDRAM width, primary DRAM x8 08h x8 08h Error-checking SDRAM data width x8 08h x8 08h 1 CK cycle 01h 1 CK cycle 01h Burst lengths supported 1, 2, 4, 8 0Fh 1, 2, 4, 8 0Fh Number of banks on each SDRAM device 4 banks 04h 4 banks 04h 2, 3 06h 2, 3 06h 0 01h 0 01h 0 01h 0 01h SDRAM module attributes Registered, PLL 16h Registered, PLL 16h 22 SDRAM device attributes: general VDD tolerance = (±10%), Burst read / write, precharge all, auto precharge 0Eh VDD tolerance = (±10%), Burst read / write, precharge all, auto precharge 0Eh 23 Minimum clock cycle time at CL = X − 1 24 Maximum data-access time from clock at CL = X − 1 25 26 tCK = 10 ns tAC = 6 ns A0h Minimum clock cycle time at CL = X − 2 N/A Maximum data-access time from clock at CL = X − 2 N/A POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 60h F0h 00h tCK = 15 ns tAC = 7.5 ns N/A 00h N/A 00h 60h PRODUCT PREVIEW TM8TU72JPW-8 BYTE NO. 75h 00h 9 SMMS713 − JUNE 1998 serial presence detect (continued) Table 1. Serial Presence-Detect Data for the TM8TU72JPW (Continued) TM8TU72JPW-8 BYTE NO. TM8TU72JPW-8A ITEM DATA ITEM DATA tRP = 20 ns tRRD = 16 ns 14h tRP = 20 ns tRRD = 16 ns 14h tRCD = 20 ns tRAS = 48 ns 14h 14h 27 Minimum row precharge time 28 Minimum row-active to row-active delay 29 Minimum RAS-to-CAS delay 30 Minimum RAS pulse width 30h tRCD = 20 ns tRAS = 48 ns 31 Density of each bank on module 64M Bytes 10h 64M Bytes 10h 32 Command and address signal input setup time 20h Command and address signal input hold time tIS = 2 ns tIH = 1 ns 20h 33 tIS = 2 ns tIH = 1 ns 34 Data signal input setup time 20h Data signal input hold time 10h tIS = 2 ns tIH = 1 ns 20h 35 tIS = 2 ns tIH = 1 ns Rev. 1.2 12h Rev. 1.2 12h 135 87h 236 ECh Manufacturer’s JEDEC ID code per JEP −106E 97h 9700... 00h 97h 9700... 00h 72 Manufacturing location† TBD 73 Manufacturer’s part number T 54h T 54h 74 Manufacturer’s part number M 4Dh M 4Dh 75 Manufacturer’s part number 8 38h 8 38h 76 Manufacturer’s part number T 54h T 54h 77 Manufacturer’s part number U 55h U 55h 78 Manufacturer’s part number 7 37h 7 37h 79 Manufacturer’s part number 2 32h 2 32h 80 Manufacturer’s part number J 4Ah J 4Ah 81 Manufacturer’s part number P 50h P 50h 82 Manufacturer’s part number W 57h W 57h 83 Manufacturer’s part number − 2Dh − 2Dh 84 Manufacturer’s part number 8 38h 8 38h 85 Manufacturer’s part number SPACE 20h A 41h 86 −90 Manufacturer’s part number Die revision code† SPACE 20h SPACE 20h 36 −61 PRODUCT PREVIEW DESCRIPTION OF FUNCTION SPD revision 63 Checksum for byte 0 −62 91 10h TBD TBD TBD 93 −94 PCB revision code† Manufacturing date† TBD TBD 95 −98 Assembly serial number† TBD TBD 99 −125 Manufacturer-specific data† TBD 126 Clock Frequency 127 128−166 SDRAM component and clock interconnection details System-integrator-specific data‡ 167−255 Open 10h 10h POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TBD 100 MHz 64h 100 MHz 64h 199 C7h 199 C7h TBD † TBD indicates values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional). 10 30h TBD TBD 92 10h Superset features (may be used in the future) 62 64 −71 10h TBD SMMS713 − JUNE 1998 device symbolization TM8TU72JPW -SS Unbuffered Key Position YYMMT 3.3-V Voltage Key Position YY MM T -SS = = = = Year Code Month Code Assembly Site Code Speed Code PRODUCT PREVIEW NOTE A: Location of symbolization may vary. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11 SMMS713 − JUNE 1998 BVC (R-PDIM-N168) DUAL-IN-LINE MEMORY MODULE 5.255 (133,48) 5.245 (133,22) (Note D) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places 0.050 (1,27) PRODUCT PREVIEW 0.039 (1,00) TYP 0.125 (3,18) 0.054 (1,37) 0.046 (1,17) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.014 (0,35) MAX 0.118 (3,00) TYP 0.125 (3,18) 0.700 (17,78) TYP 0.118 (3,00) DIA 2 Places 1.550 (39,37) 1.450 (36,83) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double-Sided DIMM Only) 4088193/A 05/98 NOTES: A. B. C. D. E. 12 All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes depanelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Device Number: TM8TU72JPW Job Number: Literature Number: SMMS713 Location: Title: TM8TU72JPW Synchronous Dynamic RAM Module File Name: 78040 SCHEDULE Final Review To Print Coordinator Signoff 4/20/98 4/23/98 PS for Customers Draft Copy Internet 4/27/98 Hibbert In Stock 4/27/98 4/30/98 DOCUMENT TYPE Pgs 14 Pgs Pgs Data Sheet User’s Guide Data Manual Data Book Handbook Itek Copies Application Report Reference Guide Rel/Qual Report Other PRODUCT STAGE: x Product Preview Advance Information Production Data Product Contact: B.J. Jackson Phone: 5909 MSG: BJ72 Marcom Contact: Marilyn Sparks Phone: 3725 MSG: MHOW Writer: Jim Williams Phone: 4286 MSG: JIMW Editor: Sylvia Lee Phone: 2798 MSG: 1JAA FUNCTION DATE IN DATE OUT HOURS INITIALS RDM Card 4/13/98 ME To Writer 4/13/98 4/13/98 Fmt 4/13/98 4/15 Art 4/15 4/15 Lbe 4/16 Wrt 4/17 4/17 JW Fmt 4/17 4/22 BT Wrt 4/22 4/22 JW Fmt 4/22 4/24 BT Wrt 4/24 4/24 JW LBE 4/24 4/28 Wrt 4/28 4/29 JW Fmt 4/29 5/4 BT Art 5/4 5/5 LC Wrt 5/5 5/5 JW .5 COMMENTS NOTE: Update traveler using 78040online_traveler JW 1st review POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1 Device Number: TM8TU72JPW Job Number: Literature Number: SMMS713 Location: Title: TM8TU72JPW Synchronous Dynamic RAM Module File Name: 78040 SCHEDULE Final Review To Print Coordinator Signoff 4/20/98 4/23/98 PS for Customers Draft Copy Internet 4/27/98 Hibbert In Stock 4/27/98 4/30/98 DOCUMENT TYPE Pgs Pgs 14 Pgs Data Sheet User’s Guide Data Manual Data Book Handbook Itek Copies Application Report Reference Guide Rel/Qual Report Other PRODUCT STAGE: Product Preview Advance Information Production Data Product Contact: B.J. Jackson Phone: 5909 MSG: BJ72 Marcom Contact: Marilyn Sparks Phone: 3725 MSG: MHOW Writer: Jim Williams Phone: 4286 MSG: JIMW Editor: Sylvia Lee Phone: 2798 MSG: 1JAA FUNCTION HOURS INITIALS DATE IN DATE OUT LBE 5/5 5/8 Wrt 5/8 5/8 LBE 5/8 5/9 Wrt 5/9 5/13 JW Fmt 5/13 5/13 BT LBE 5/13 5/13 FMT 5/13 5/13 BT FMT 5/14 5/14 BT Wrt 5/14 5/14 Edit 5/14 5/14 COMMENTS JW 4 Signed Off JW Signed off SL −proofed against source and R/Led copies A−G −edited −to writer for questions −then will neeed to send to FMT/ART for changes −asked Michelle to update Channel Media Jim 5/14 5/18 FMT 5/18 6/1 BT Wrt 6/1 6/3 JW 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Device Number: TM8TU72JPW Job Number: Literature Number: SMMS713 Location: Title: TM8TU72JPW Synchronous Dynamic RAM Module File Name: 78040 SCHEDULE Final Review To Print Coordinator Signoff 4/20/98 4/23/98 PS for Customers Draft Copy Internet 4/27/98 Hibbert In Stock 4/27/98 4/30/98 DOCUMENT TYPE Pgs Pgs 14 Pgs Data Sheet User’s Guide Data Manual Data Book Handbook Itek Copies Application Report Reference Guide Rel/Qual Report Other PRODUCT STAGE: Product Preview Advance Information Production Data Product Contact: B.J. Jackson Phone: 5909 MSG: BJ72 Marcom Contact: Marilyn Sparks Phone: 3725 MSG: MHOW Writer: Jim Williams Phone: 4286 MSG: JIMW Editor: Sylvia Lee Phone: 2798 MSG: 1JAA FUNCTION Prt Chk DATE IN DATE OUT 6/8 6/8 HOURS 1 INITIALS SL COMMENTS −proofed against 6/3/98 preliminary print check −checked out RDM Edit copy to add a hyphen in the 2nd Features bullet −printed entire data sheet −did final print check on newly printed data sheet −signed off −checked RDM Edit copy back into RDM −to writer for other signatures Jim 6/8/98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 3 Device Number: TM8TU72JPW Job Number: Literature Number: SMMS713 Location: Title: TM8TU72JPW Synchronous Dynamic RAM Module File Name: 78040 SCHEDULE Final Review To Print Coordinator Signoff 4/20/98 4/23/98 PS for Customers Draft Copy Internet 4/27/98 Hibbert In Stock 4/27/98 4/30/98 DOCUMENT TYPE Pgs Pgs 14 Pgs Data Sheet User’s Guide Data Manual Data Book Handbook Itek Copies Application Report Reference Guide Rel/Qual Report Other PRODUCT STAGE: Product Preview Advance Information Production Data Product Contact: B.J. Jackson Phone: 5909 MSG: BJ72 Marcom Contact: Marilyn Sparks Phone: 3725 MSG: MHOW Writer: Jim Williams Phone: 4286 MSG: JIMW Editor: Sylvia Lee Phone: 2798 MSG: 1JAA FUNCTION 4 DATE IN DATE OUT HOURS INITIALS POST OFFICE BOX 1443 COMMENTS • HOUSTON, TEXAS 77251−1443 SMMS713 Jim Williams 78040 TM8TU72JPW SMMS713 Jim Williams Jim Williams 78040 Jim Williams 78040 Jim Williams 78040 Jim Williams 78040 Jim Williams 78040 Jim Williams 78040 Jim Williams 78040 Jim Williams 78040 Jim Williams 78040 Jim Williams Jim Williams 78040 SMMS713 Jim Williams 78040 SMMS713 Jim Williams 78040 SMMS713 Jim Williams 78040 SMMS713 Jim Williams 78040 SMMS713 Jim Williams 78040 SMMS713 Jim Williams 78040 TM8TU72JPW 78040 TM8TU72JPW SMMS713 SMMS713 TM8TU72JPW TM8TU72JPW SMMS713 78040 TM8TU72JPW TM8TU72JPW SMMS713 Jim Williams TM8TU72JPW TM8TU72JPW SMMS713 SMMS713 TM8TU72JPW TM8TU72JPW SMMS713 78040 TM8TU72JPW TM8TU72JPW SMMS713 Jim Williams TM8TU72JPW TM8TU72JPW SMMS713 SMMS713 TM8TU72JPW TM8TU72JPW SMMS713 78040 TM8TU72JPW TM8TU72JPW SMMS713 Jim Williams TM8TU72JPW TM8TU72JPW SMMS713 SMMS713 SMMS713 Jim Williams 78040 TM8TU72JPW 78040 TM8TU72JPW SMMS713 Jim Williams 78040 TM8TU72JPW POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 SMMS713 Jim Williams 78040 TM8TU72JPW SMMS713 Jim Williams Jim Williams 78040 78040 SMMS713 Jim Williams 78040 TM8TU72JPW 78040 TM8TU72JPW 6 Jim Williams TM8TU72JPW TM8TU72JPW SMMS713 SMMS713 SMMS713 Jim Williams TM8TU72JPW POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 78040 TECHNICAL DOCUMENTATION SERVICES First Review: TM8TU72JPW Synchronous Dynamic RAM Module Literature Number: SMMS713 TDS Job #: 78040 Device Number(s): TM8TU72JPW Scheduled printing date: 4/27/98 Distributed: Return by: From: Jim Williams Engineering Reviewers: 4286 JIMW M/S: 640 B.J. Jackson The purpose of this review is to identify technical inaccuracies, missing information, and organizational problems. As you review this datasheet, please: Verify technical accuracy. Provide detailed redlines and any additional source as needed. In order to meet the scheduled to-print date, please make every effort to complete this review and return to TDS before 4:00 p.m. on . Thank you for your cooperation. Jim Williams POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 7 TECHNICAL DOCUMENTATION SERVICES Review: TM8TU72JPW Synchronous Dynamic RAM Module Literature Number: SMMS713 TDS Job #: 78040 Device Number(s): TM8TU72JPW Scheduled printing date: 4/27/98 Distributed: Return by: From: Jim Williams Engineering Reviewers: 4286 JIMW M/S: 640 B.J. Jackson Revisions to this datasheet were based on the previous review and recent updates. Please verify and send any additional corrections or changes to TDS before 4:00 p.m. on . Thank you for your cooperation. Jim Williams 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TECHNICAL DOCUMENTATION SERVICES Final Review: TM8TU72JPW Synchronous Dynamic RAM Module Literature Number: SMMS713 TDS Job #: 78040 Device Number(s): TM8TU72JPW Scheduled printing date: 4/27/98 Distributed: Return by: From: Jim Williams 4286 JIMW M/S: 640 The attached datasheet is ready for final approval, signoff, and printing. Please sign and date this form and return to TDS before 4:00 on . Any major changes at this time will affect the printing schedule. Sign Off for Print Engineering Reviewers: Date B.J. Jackson Marketing: Writer: Jim Williams Editor: Sylvia Lee Illustrator: Format: L. Coleman or B. Herke M. Pope or B. Tucker MarCom: Please indicate the print quantity and fullfillment channels, and sign below. Please send the distribution to the print coordinator as soon as possible. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 9 Print Quantity: Marcom Manager: Marilyn Sparks ÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Channel Yes No Channel Yes No Channel Internet Field Sales Office CD ROM Hibbert Fax Servers Product Specific CD ROM Print on Demand 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Yes No Collation List Literature Number: Lit # TDS Job #: 78040 TM8TU72JPW Synchronous Dynamic RAM Module Collation List file name 78040a.ps Item # of Pages File Name Page Numbers Cover (see note 1) 0 or 4 78040b.ps − Title Page 1 78040c.ps i (Implied) Important Notice 1 78040d.ps ii (implied) (Note: This MUST be a separate file!) S Preface 78040e.ps TOC 78040f.ps Chapter 1 (sse note 2) 78040g.ps 1 −1 to 1 −? Chapter 2 (If a section has more than 1 file, create the entry this way.) 78040h.ps 78040i.ps 2 −1 to 2 − ? 2 − ? to 2 − ? Chapter 3 78040j.ps 3 −1 to 3 − ? Chapter 4 78040k.ps 4 −1 to 4 − ? Chapter 5 78040l.ps 5 −1 to 5 − ? Chapter 6 78040m.ps 6 −1 to ? Appendix A 78040n.ps A −1 to ? Index 78040o.ps Index−1 to Index− iii to ? Notes (see note 3) 1 or pad to total FSO 1 Business Reply Card (see note 1.) − − Reference Card (see note 1.) − ? pages Total Pages (see note 4) ? (multiple of 4) UG_NOTES_LEFT.ps UG_NOTES_RIGHT.ps sszza01k.ps NEW FSO file date code:A032597 Notes 1. Cover: • If your book has a blue and yellow cover, enter 0 (do not count the covers, reference cards, etc.) • If your book has a self-cover, enter 4 (front and back cover as 4 pages). 2. Add as many rows as necessary for chapters, filenames, etc. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11 3. 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