SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Packaged in Plastic Thin Shrink Small-Outline Package Y1 Y2 GND Y3 Y4 VDDQ Y5 Y6 GND Y7 Y8 VDDQ Y9 Y10 GND OE VREF GND Y11 Y12 VDDQ Y13 Y14 GND Y15 Y16 VDDQ Y17 Y18 GND Y19 Y20 description This 20-bit buffer is designed for 3-V to 3.6-V VCC operation and SSTL_3 input levels. Data flow from A to Y is controlled by the output-enable (OE). When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74SSTL16847 is characterized operation from 0°C to 70°C. for 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 A1 A2 GND A3 A4 VCC A5 A6 GND A7 A8 VCC A9 A10 GND NC NC GND A11 A12 VCC A13 A14 GND A15 A16 VCC A17 A18 GND A19 A20 NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 FUNCTION TABLE INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) OE A1 16 1 64 Y1 To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through each VCC, VDDQ or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Package thermal impedance, qJA (see Note 3): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current will flow only when the output is in the high state and VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 recommended operating conditions (see Note 4) MIN VCC VDDQ Supply voltage VREF VTT Reference voltage (VREF = 0.45 × VDDQ) VI VIH Input voltage AC high-level input voltage All inputs VIL VIH AC low-level input voltage All inputs DC high-level input voltage All inputs VIL IOH DC low-level input voltage All inputs IOL TA Low-level output current NOM MAX VDDQ 3 Output supply voltage 1.3 Termination voltage VREF–50mV 0 1.5 VREF UNIT 3.6 V 3.6 V 1.7 V VREF+50mV VCC VREF+400mV V V VREF–400mV VREF+200mV V V VREF–200mV – 20 High-level output current 20 Operating free-air temperature V 0 V mA _C 70 NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS II = –18 mA IOH = –100 µA VOH IOH = –16 mA IOH = –20 mA VOL Data inputs, OE VREF IOZ ICC Ci A port VCC–0.2 2.2 VI = 2.1 V or 0.9 V, VREF = 1.3 V or 1.7 V VREF = 1.3 V or 1.7 V 0.5 Co Y port VO = 2.1 V or 0.9 V † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 3.3 V • DALLAS, TEXAS 75265 V 0.55 36V 3.6 33V 3.3 V 0.2 3.6 V VI = 2 2.1 1 V or 0 0.9 9V UNIT –1.2 V 3.6 V IO = 0 MAX 2.1 3V VO = 0.9 V or 2.1 V VI = 2.1 V or 0.9 V, Control inputs 3 V to 3.6 V 3 V to 3.6 V IOL = 20 mA II MIN 3V IOL = 100 µA IOL = 16 mA TYP† VCC 3V 2 2.5 3.5 ±5 µA ±150 µA ±10 µA 90 mA pF pF 3 SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 switching characteristics over recommended operating free-air temperature range, Class I, VREF = VTT = VDDQ X 0.45 and CL = 10 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX tpd UNIT A Y 1.5 3 ns ten OE Y 1.5 4 ns tdis OE Y 1.6 4.9 ns switching characteristics over recommended operating free-air temperature range, Class II, VREF = VTT = VDDQ X 0.45 and CL = 30 pF (unless otherwise noted) (see Figure 1) 4 PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX tpd A Y 1.5 3 ns ten OE Y 1.5 4.1 ns tdis OE Y 1.5 4.8 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VTT Test Point 25 Ω = SSTL_3 Class II 50 Ω = SSTL_3 Class I 25 Ω CL = 10 pF or 30 pF (see Note A) LOAD CIRCUIT Timing Input VIH‡ VREF† tsu tw VIL§ VIH‡ VREF† VREF† Input th VIL§ VIH‡ Data Input VREF† VREF† VOLTAGE WAVEFORMS PULSE DURATION VIL§ VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control VREF† Input VIL§ tPLH Output VOH VREF† VOL VIL§ tPLZ Output Waveform 1 (see Note B) VIL§ Output Waveform 2 (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VIL§ VTT VOL tPHL VREF† VIH‡ VREF† tPZL VIH‡ VREF† VREF† tPHZ tPZH VIH‡ VIH‡ VOH VTT VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING † VREF = 0.45 VDDQ ‡ VIH = VREF+400mV (AC voltage levels) § VIL = VREF–400mV (AC voltage levels) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1.25 ns/V, tf ≤ 1.25 ns/V. D. The outputs are measured one at a time with one transition per measurement. E. VTT = VREF = VDDQ X 0.45 F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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