MOTOROLA MC14501BCL

SEMICONDUCTOR TECHNICAL DATA
Dual 4–Input “NAND” Gate
2–Input “NOR/OR” Gate
8–Input “AND/NAND” Gate
L SUFFIX
CERAMIC
CASE 620
The MC14501UB is constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. Additional characteristics
can be found on the Family Data Sheet.
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT SCHEMATIC
VDD
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
LOGIC DIAGRAM
(POSITIVE LOGIC)
1
2
13
3
4
11
14 AND
12
5
6
7
9
15 NAND
10
VDD = PIN 16
VSS = PIN 8
Use Dotted Connection Externally to
Obtain 8–Input AND/NAND
16
VDD
NOTE: Pin 14 must not be used as an input
NOTE: to the inverter.
11
13 (10)
12
(6) 1
14
(7) 2
15
VSS
(9) 3
(5) 4
VSS
8
VSS
Numbers in parenthesis are for second 4–input gate.
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14501UB
1
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
3.75
—
—
—
2.25
4.50
6.75
1.5
3.0
3.75
—
—
—
1.4
2.9
3.6
5.0
10
15
3.6
7.1
11.4
—
—
—
3.5
7.0
11.25
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 3.6 or 1.4 Vdc)
(VO = 7.2 or 2.8 Vdc)
(VO = 11.5 or 3.5 Vdc)
VIL
(VO = 1.4 or 3.6 Vdc) “1” Level
(VO = 2.8 or 7.2 Vdc)
(VO = 3.5 or 11.5 Vdc)
VIH
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
– 55_C
VDD
Vdc
Vdc
IOH
Source
NAND*
Vdc
mAdc
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc
(VOH = 13.5 Vdc)
NOR
5.0
5.0
10
15
– 2.1
– 0.42
– 1.06
– 3.1
—
—
—
—
– 1.75
– 0.35
– 0.88
– 2.63
– 3.0
– 0.63
– 1.58
– 6.12
—
—
—
—
– 1.22
– 0.24
– 0.62
– 1.84
—
—
—
—
mAdc
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
NOR–
5.0
5.0
10
15
– 3.6
– 0.72
– 1.8
– 5.4
—
—
—
—
– 3.0
– 0.6
– 1.5
– 4.5
– 5.1
– 1.08
– 2.7
– 10.5
—
—
—
—
– 2.1
– 0.42
– 1.05
– 3.15
—
—
—
—
mAdc
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
NAND*
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
NOR
5.0
10
15
0.92
2.34
6.12
—
—
—
0.77
1.95
5.1
1.32
3.37
13.2
—
—
—
0.54
1.36
3.57
—
—
—
mAdc
NOR–
Inverter
5.0
10
15
1.54
3.90
10.2
—
—
—
1.28
3.25
8.5
2.2
5.63
22
—
—
—
0.90
2.27
5.95
—
—
—
mAdc
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
IT
5.0
10
15
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Inverter
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IOL
IT = (1.2 µA/kHz) f + IDD
IT = (2.4 µA/kHz) f + IDD
IT = (3.6 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
MC14501UB
2
MOTOROLA CMOS LOGIC DATA
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS** (CL = 50 pF, TA = 25_C)
Characteristic
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
NAND, NOR
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
NAND, NOR
Output Rise Time
tTLH = (1.35 ns/pF) CL + 32.5 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/pF) CL + 17 ns
NOR–Inverter
Output Fall Time
tTHL = (0.67 ns/pF) CL + 26.5 ns
tTHL = (0.45 ns/pF) CL + 17.5 ns
tTHL = (0.37 ns/pF) CL + 11.5 ns
NOR–Inverter
Figure
Symbol
2, 3
tTLH
2, 3
3
3
VDD
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
60
40
30
120
80
60
50
10
15
130
70
50
260
140
100
Unit
ns
tTHL
ns
tTLH
ns
tTHL
ns
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 45 ns
tPLH, tPHL = (0.66 ns/pF) CL + 37 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
NAND
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns
tPLH, tPHL = (0.66 ns/pF) CL + 32 ns
tPLH, tPHL = (0.5 ns/pF) CL + 20 ns
NOR
3
tPLH
tPHL
5.0
10
15
115
65
45
230
130
90
ns
tPLH, tPHL = (1.7 ns/pF) CL + 45 ns
tPLH, tPHL = (0.66 ns/pF) CL + 37 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
NOR–Inverter
3
tPLH,
tPHL
5.0
10
15
130
70
50
260
140
100
ns
2
tPLH,
tPHL
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA
MC14501UB
3
0.01 µF
VDD
CERAMIC
16
PIN ASSIGNMENT
CL
Vin
CL
CL
CL
8
500 µF
IDD
50% DUTY CYCLE
20 ns
90%
Vin
10%
VDD
90%
10%
20 ns
IN 1A
1
16
VDD
IN 2A
2
15
OUTB
IN 3A
3
14
OUTB
IN 4A
4
13
OUTA
IN 1C
5
12
IN 2B
IN 2C
6
11
IN 1B
IN 3C
7
10
OUTC
VSS
8
9
IN 4C
VSS
Figure 1. Power Dissipation Test Circuit
and Waveform
VDD
20 ns
16
PULSE
GENERATOR
INPUT (A)
OUTPUT
(B)
INPUT
(A) 8
VDD
90%
50%
10%
tPHL
CL
VSS
20 ns
90%
50%
10%
tPLH
90%
50%
10%
OUTPUT (B)
VSS
VOH
90%
50%
10%
tTHL
VOL
tTLH
Figure 2. Input “NAND” Gate Switching Time Test Circuit and Waveforms
20 ns
INPUT (A)
OUTPUT (B)
PULSE
GENERATOR
INPUT (A)
OUTPUT (C)
CL
Output (B) = “NOR”
Output (C) = “NOR–Inverter”
CL
All unused inputs
connected to ground.
VDD
90%
50%
10%
tPLH
tPHL
90%
50%
10%
OUTPUT (B)
tTHL
tPLH
OUTPUT (C)
tTLH
tTLH
90%
50%
10%
tTHL
VSS
VOH
VOL
tPHL
VOH
VOL
Figure 3. “NOR” Gate and “NOR–Inverter” Switching Time Test Circuit and Waveforms
MC14501UB
4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14501UB
5
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
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MC14501UB
6
◊
*MC14501UB/D*
MOTOROLA CMOSMC14501UB/D
LOGIC DATA