× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
D Independent Asynchronous Inputs and
D
D
D
D
D
D
D
D
D
D
D
Outputs
Low-Power Advanced CMOS Technology
Bidirectional
1024 Words by 9 Bits Each
Programmable Almost-Full/Almost-Empty
Flag
Empty, Full, and Half-Full Flags
Access Times of 25 ns With a 50-pF Load
Data Rates From 0 to 50 MHz
Fall-Through Times of 23 ns Max
High Output Drive for Direct Bus Interface
3-State Outputs
Available in 44-Pin PLCC (FN) Package
A2
A1
A0
GND
DIR
SBA
SAB
OE
GND
B0
B1
FN PACKAGE
(TOP VIEW)
A3
A4
7
6 5 4
3
2 1 44 43 42 41 40
39
8
38
VCC
A5
A6
A7
A8
GND
AF/AEA
HFA
LDCKA
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
FULLA
UNCKB
EMPTYB
DAF
RSTA
RSTB
DBF
EMPTYA
UNCKA
FULLB
LDCKB
30
17
29
18 19 20 21 22 23 24 25 26 27 28
B2
B3
B4
VCC
B5
B6
B7
B8
GND
AF/AEB
HFB
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2236 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times.
It processes data at rates from 0 to 50 MHz with access times of 25 ns in a bit-parallel format.
The SN74ACT2236 consists of bus-transceiver circuits, two 1024 × 9 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable OE and
DIR inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 1 shows the five fundamental bus-management functions that can be performed with the SN74ACT2236.
The SN74ACT2236 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the application report 1K 9 2 Asynchronous FIFOs
SN74ACT2235 and SN74ACT2236 in the 1996 High-Performance FIFO Memories Designer’s Handbook,
literature number SCAA012A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
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1
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
logic symbol†
Φ
FIFO
1024 × 9 × 2
SN74ACT2236
SAB
SBA
OE
DIR
RSTA
DAF
LDCKA
UNCKA
FILLA
EMPTYA
AF/AEA
HFA
A0
A1
A2
A3
A4
A5
A6
A7
A8
44
1
43
2
22
21
1
MODE
0
3EN1 [BA]
3EN2 [AB]
G3
RESET B
RESET A
DEF B FLAG
DEF A FLAG
18
25
15
16
4
LDCKA
LDCKB
UNCKA
UNCKB
19
FULL B
FULLA
EMPTYB
EMPTYA
ALMOST-FULL/
ALMOST-FULL/
ALMOST-EMPTY A ALMOST-EMPTY B
HALF-FULL A
HALF-FULL B
0
1
2
0
27
20
30
29
41
5
40
6
39
7
38
A Data
8
B Data
37
10
35
11
34
12
33
13
8
8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
24
28
17
26
23
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•
32
RSTB
DBF
LDCKB
UNCKB
FULLB
EMPTYB
AF/AEB
HFB
B0
B1
B2
B3
B4
B5
B6
B7
B8
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
logic diagram (positive logic)
SAB
SBA
Φ
FIFO B
1024 × 9
HFB
AF/AEB
RSTB
DBF
EMPTYB
FULLB
UNCKB
LDCKB
Q
D
B0
One of Nine Channels
To Other Channels
DIR
OE
Φ
FIFO A
1024 × 9
RSTA
DAF
HFA
AF/AEA
FULLA
EMPTYA
LDCKA
UNCKA
A0
D
Q
One of Nine Channels
To Other Channels
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3
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AF/AEA,
AF/AEB
15, 30
O
Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the
almost-full/almost-empty offset value for FIFO A (X). AF/AEA is high when FIFO A contains X or less
words or 1024 −X words. AF/AEA is low when FIFO A contains between X + 1 or 1023 − X words.
The operation of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for FIFO B.
A0 −A8
4 −8, 10 −13
I/O
A data inputs and outputs
B0 −B8
32 −35,
37 −41
I/O
B data inputs and outputs
DAF, DBF
21, 24
I
Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0 −A8 as the
almost-full/almost-empty offset value for FIFO A (X). The high-to-low transition of DBF stores the
binary value of B0−B8 as the almost-full/almost-empty offset value for FIFO B (Y).
EMPTYA,
EMPTYB
20, 25
O
Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high
when they are not empty.
FULLA,
FULLB
18, 27
O
Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they
are not full.
HFA, HFB
16, 29
O
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more
words, and low when they contain 511 or less words.
LDCKA,
LDCKB
17, 28
I
Load clocks. Data on A0−A8 is written into FIFO A on a low-to-high transition of LDCKA. Data on
B0 −B8 is written into FIFO B on a low-to-high transition of LDCKB. When the FIFOs are full, LDCKA
and LDCKB have no effect on the data residing in memory.
DIR, OE
2, 43
I
Enable inputs. DIR and OE control the transceiver functions. When OE is high, both A0 −A8 and
B0 −B8 are in the high-impedance state and can be used as inputs. With OE low and DIR high, the
A bus is in the high-impedance state and B bus is active. When both OE and DIR are low, the A bus
is active and the B bus is in the high-impedance state.
RSTA, RSTB
22, 23
I
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
SAB, SBA
1, 44
I
Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level
selects real-time data, and a high level selects stored data. Eight fundamental bus-management
functions can be performed as shown in Figure 1.
UNCKA,
UNCKB
19, 26
I
Unload clocks. Data in FIFO A is read to B0 −B8 on a low-to-high transition of UNCKB. Data in FIFO
B is read to A0 −A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and
UNCKB have no effect on data residing in memory.
programming procedure for AF/AEA
The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
almost-full/almost-empty offset value FIFO A (X) and for FIFO B (Y) are either a user-defined value or the default
values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB is
programmed in the same manner for FIFO B.
user-defined X
Take DAF from high to low. This stores A0 thru A8 as X.
If RSTA is not already low, take RSTA high.
With DAF held low, take RSTA high. This defines the AF/AEA flag using X.
To retain the current offset for the next reset, keep DAF low.
default X
To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle.
4
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†
LDCKA
DAF
RSTA
timing diagram for FIFO A
Don’t Care
Word
1
Word
2
Word
257
Word
512
Word
768
Word
1024
Don’t Care
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
X
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•
•
Empty + 256
Half Full
Full − 256
† Operation of FIFO B is identical to that of FIFO A.
‡ Last valid data stays on outputs when FIFO goes empty due to a read.
Set Flag to Empty + 256/
Full − 256 (default)
AF/AEA
HFA
FULLA
EMPTYA
Word 1
Full
Word
514
Half Full
Word Word
258
513
Full − 256
Word Word
257
2
Word
769
Empty + 256
Word
768
Invalid
Set Flag to
Empty + X/Full − X
Load X into
Flag Register
(0 ≤ X ≤ 511)
Word ‡
1024
Empty
Word
1024
ÎÎ
ÎÎ
ÎÎ
Q0 − Q8
UNCKA
Invalid
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÉÉÉ
ÎÎÎ
A0 − A8
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
5
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
In
FIFO A
Out
In
Bus A
Bus B
Bus A
Bus B
FIFO B
Out
In
SAB SBA
L
X
In
DIR
H
FIFO B
Out
In
SAB SBA
X
X
OE
L
FIFO A
Out
In
Bus A
Bus B
In
DIR
L
SAB SBA
H
X
OE
L
Bus B
FIFO B
Out
In
OE
L
Figure 1. Bus-Management Functions
6
FIFO A
Out
FIFO B
Out
In
Bus A
DIR
L
OE
H
Bus B
FIFO A
Out
SAB SBA
X
H
DIR
X
Bus A
FIFO B
Out
In
SAB SBA
X
L
FIFO A
Out
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•
DIR
H
OE
L
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
SELECT-MODE CONTROL TABLE
OPERATION
CONTROL
SAB
SBA
A BUS
B BUS
L
L
Real-time B to A bus
Real-time A to B bus
L
H
FIFO B to A bus
Real-time A to B bus
H
L
Real-time B to A bus
FIFO A to B bus
H
H
FIFO B to A bus
FIFO A to B bus
OUTPUT-ENABLE CONTROL TABLE
OPERATION
CONTROL
DIR
OE
A BUS
B BUS
X
H
Input
Input
L
L
Output
Input
H
L
Input
Output
Figure 1. Bus-Management Functions (Continued)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
recommended operating conditions
′ACT2236-20
VCC
VIH
Supply voltage
VIL
Low-level input voltage
High-level output current
IOL
Low-level output current
fclock
Clock frequency
Pulse duration
MIN
MAX
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
th
TA
8
Hold time
2
2
0.8
0.8
0.8
−8
−8
−8
−8
Status flags
−8
−8
−8
−8
A or B ports
16
16
16
16
Status flags
8
8
8
8
LDCKA or LDCKB
50
33
25
16.7
UNCKA or UNCKB
50
33
25
16.7
20
20
25
25
LDCKA or LDCKB low
8
10
14
20
LDCKA or LDCKB high
8
10
14
20
UNCKA or UNCKB low
8
10
14
20
8
10
14
20
10
10
10
10
Data before LDCKA or
LDCKB↑
4
4
5
5
Define AF/AE: D0 −D8
before DAF or DBF↓
5
5
5
5
Define AF/AE: DAF or
DBF↓ before RSTA or
RSTB↑
7
7
7
7
Define AF/AE (default):
DAF or DBF high before
RSTA or RSTB↑
5
5
5
5
RSTA or RSTB inactive
(high) before LDCKA or
LDCKB↑
5
5
5
5
Data after LDCKA or
LDCKB↑
1
1
2
2
Define AF/AE: D0 −D8
after DAF or DBF↓
0
0
0
0
Define AF/AE: DAF or
DBF low after RSTA or
RSTB↑
0
0
0
0
Define AF/AE (default):
DAF or DBF high after
RSTA or RSTB↑
0
0
0
0
UNIT
V
V
0.8
DAF or DBF high
Setup time
2
A or B ports
UNCKA or UNCKB high
tsu
′ACT2236-60
MAX
2
RSTA or RSTB low
tw
′ACT2236-40
MIN
High-level input voltage
IOH
′ACT2236-30
V
mA
mA
MHz
ns
ns
Operating free-air temperature
0
•
70
0
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70
0
70
0
ns
70
°C
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
Flags
VOL
I/O ports
II
IOZ
IOH = − 8 mA
IOL = 8 mA
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 16 mA
VI = VCC or 0
TYP†
DIR, OE
Other inputs
VCC = 5.5 V,
MAX
2.4
UNIT
V
0.5
0.5
VCC = 5.5 V,
VO = VCC or 0
VI = VCC − 0.2 V or 0
ICC‡
∆ICC§
VCC = 4.5 V,
VCC = 4.5 V,
MIN
10
One input at 3.4 V,
±5
µA
±5
µA
400
µA
2
Other inputs at VCC or GND
1
Ci
VI = 0,
f = 1 MHz
Co
VO = 0,
f = 1 MHz
† All typical values are at VCC = 5 V, TA = 25°C.
‡ ICC tested with outputs open.
§ This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.
V
mA
4
pF
8
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 4 and 5)
PARAMETER
fmax
FROM
(INPUT)
TO
(OUTPUT)
′ACT2236-20
TYP†
MAX
′ACT2236-30
LDCK
50
33
25
16.7
UNCK
50
33
25
16.7
LDCK↑, LDCKB↑
B or A
8
tpd
UNCKA↑,
UNCKB↑
B or A
10
tPLH
LDCK↑, LDCKB↑
EMPTYA,
EMPTYB
tPHL
UNCKA↑,
UNCKB↑
tPHL
MIN
′ACT2236-60
MIN
tpd
MAX
′ACT2236-40
MIN
MAX
MIN
MAX
UNIT
MHz
23
8
23
8
25
8
27
ns
25
10
25
10
35
10
45
ns
4
15
4
15
4
17
4
19
ns
EMPTYA,
EMPTYB
2
17
2
17
2
19
2
21
ns
RSTA↓, RSTB↓
EMPTYA,
EMPTYB
2
18
2
18
2
20
2
22
ns
tPHL
LDCK↑, LDCKB↑
FULLA, FULLB
4
15
4
15
4
17
4
19
ns
tPLH
UNCKA↑,
UNCKB↑
FULLA, FULLB
4
15
4
15
4
17
4
19
ns
tPLH
tPLH
RSTA↓, RSTB↓
FULLA, FULLB
2
15
2
15
2
17
2
19
ns
RSTA↓, RSTB↓
AF/AEA, AF/AEB
2
15
2
15
2
17
2
19
ns
tPLH
LDCK↑, LDCKB↑
HFA, HFB
2
15
2
15
2
17
2
19
ns
tPHL
UNCKA↑,
UNCKB↑
HFA, HFB
4
19
4
19
4
21
4
23
ns
tPHL
tpd
RSTA↓, RSTB↓
SAB or SBA¶
HFA, HFB
1
15
1
15
1
17
1
19
ns
17
B or A
1
11
1
11
1
13
1
15
ns
tpd
tpd
A or B
B or A
1
11
1
11
1
13
1
15
ns
LDCK↑, LDCKB↑
AF/AEA, AF/AEB
2
19
2
19
2
21
2
23
ns
tpd
UNCKA↑,
UNCKB↑
AF/AEA, AF/AEB
2
19
2
19
2
23
2
23
ns
DIR, OE
A or B
2
12
2
12
2
14
2
16
ns
DIR, OE
A or B
1
10
1
10
1
12
1
14
ns
ten
tdis
† All typical values are at VCC = 5 V, TA = 25°C.
¶ These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
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9
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per 1K bits
TYP
CL = 50 pF, f = 5 MHz
Outputs disabled
UNIT
71
pF
57
TYPICAL CHARACTERISTICS
POWER DISSIPATION CAPACITANCE
vs
SUPPLY VOLTAGE
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
typ + 2
VCC = 5 V
TA = 25°C
RL = 500 Ω
typ + 6
Cpd − Power Dissipation Capacitance − pF
t pd − Propagation Delay Time − ns
typ + 8
typ + 4
typ + 2
typ
typ − 2
0
50
100
150
200
250
VCC = 5 V
fi = 5 MHz
TA = 25°C
typ + 1
typ
typ − 1
typ − 2
typ − 3
4.5
300
4.6
CL − Load Capacitance − pF
4.7 4.8 4.9
Figure 2
Figure 3
calculating power dissipation
The maximum power dissipation (PT) can be calculated by:
PT = VCC × [ICC + (N × ∆ICC × dc)] + Σ(Cpd × VCC2 × fi) + Σ(CL × VCC2 × fo)
where:
ICC
N
∆ICC
dc
Cpd
CL
fi
fo
10
=
=
=
=
=
=
=
=
5
5.1 5.2
VCC − Supply Voltage − V
power-down ICC maximum
number of inputs driven by a TTL device
increase in supply current
duty cycle of inputs at a TTL high level of 3.4 V
power dissipation capacitance
output capacitive load
data input frequency
data output frequency
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5.3
5.4 5.5
× × SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
3V
Input
From Output
Under Test
1.5 V
GND
RL = 500 Ω
tpd
CL = 50 pF
tpd
3V
Output
1.5 V
0V
LOAD CIRCUIT
TOTEM-POLE OUTPUTS
Figure 4. Standard CMOS Outputs (All Flags)
3V
1.5 V
Input
1.5 V
0V
VCC
tPZL
≈ VCC
S1
From Output
Under Test
tPLZ
Output
RL
0.3 V
1.5 V
VOL
tPHZ
tPZH
CL
S2
VOH
1.5 V
Output
0.3 V
≈0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
PARAMETER
ten
tPZH
tPZL
tdis
tPHZ
tPLZ
RL
CL†
500 Ω
50 pF
500 Ω
50 pF
S1
S2
Open
Closed
Closed
Open
Open
Closed
Closed
Open
tpd or tt
−
50 pF
Open
† Includes probe and test-fixture capacitance
Open
Figure 5. 3-State Outputs (A0ā −ā A8, B0ā −ā B8)
•
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11
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ACT2236-20FN
OBSOLETE
PLCC
FN
44
TBD
Call TI
Call TI
SN74ACT2236-30FN
OBSOLETE
PLCC
FN
44
TBD
Call TI
Call TI
SN74ACT2236-40FN
OBSOLETE
PLCC
FN
44
TBD
Call TI
Call TI
SN74ACT2236-60FN
OBSOLETE
PLCC
FN
44
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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