ONSEMI 2V7002WT1G

2N7002W, 2V7002W
Small Signal MOSFET
60 V, 340 mA, Single, N−Channel, SC−70
Features
•
•
•
•
•
ESD Protected
Low RDS(on)
Small Footprint Surface Mount Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
2V Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
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V(BR)DSS
RDS(on) MAX
ID MAX
(Note 1)
60 V
1.6 W @ 10 V
340 mA
2.5 W @ 4.5 V
Applications
•
•
•
•
Low Side Load Switch
Level Shift Circuits
DC−DC Converter
Portable Applications i.e. DSC, PDA, Cell Phone, etc.
SIMPLIFIED SCHEMATIC
Gate
1
3
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
±20
V
Drain Current (Note 1)
Steady State
t<5s
TA = 25°C
TA = 85°C
ID
TA = 25°C
TA = 85°C
Power Dissipation (Note 1)
Steady State
t<5s
(Top View)
MARKING DIAGRAM
& PIN ASSIGNMENT
Drain
340
240
PD
3
mW
280
330
IDM
1.4
A
Operating Junction and Storage
Temperature Range
TJ, TSTG
−55 to
+150
°C
Source Current (Body Diode)
IS
250
mA
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
ESD
900
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Symbol
Max
Unit
Junction−to−Ambient − Steady State
(Note 1)
RqJA
450
°C/W
Junction−to−Ambient − t ≤ 5 s (Note 1)
RqJA
375
1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in
sq [1 oz] including traces)
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 5
1
71 MG
G
SC−70/SOT−323
CASE 419
STYLE 8
1
2
Gate
Source
71 = Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Package
Shipping†
2N7002WT1G
SC−70
(Pb−Free)
3000/Tape & Reel
2V7002WT1G
SC−70
(Pb−Free)
3000/Tape & Reel
Device
THERMAL CHARACTERISTICS
Characteristic
2
mA
310
220
Pulsed Drain Current (tp = 10 ms)
Gate−Source ESD Rating
(HBM, Method 3015)
Source
Drain
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
2N7002W/D
2N7002W, 2V7002W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Parameter
Typ
Max
Units
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
IGSS
V
71
mV/°C
VGS = 0 V,
VDS = 60 V
TJ = 25°C
1.0
mA
TJ = 150°C
15
mA
VGS = 0 V,
VDS = 50 V
TJ = 25°C
100
nA
TJ = 150°C
10
mA
VDS = 0 V, VGS = ±20 V
±10
mA
VDS = 0 V, VGS = ±10 V
450
nA
VDS = 0 V, VGS = ±5.0 V
150
nA
2.5
V
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
VGS(TH)
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
gFS
VGS = VDS, ID = 250 mA
1.0
4.0
mV/°C
VGS = 10 V, ID = 500 mA
1.19
1.6
VGS = 4.5 V, ID = 200 mA
1.33
2.5
VDS = 5 V, ID = 200 mA
530
mS
24.5
pF
W
CHARGES AND CAPACITANCES
CISS
Input Capacitance
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
VGS = 0 V, f = 1 MHz,
VDS = 20 V
4.2
2.2
nC
0.7
VGS = 4.5 V, VDS = 10 V;
ID = 200 mA
0.1
0.3
0.1
SWITCHING CHARACTERISTICS, VGS = V (Note 3)
Turn−On Delay Time
td(ON)
Rise Time
Turn−Off Delay Time
tr
td(OFF)
Fall Time
ns
12.2
VGS = 10 V, VDD = 25 V,
ID = 500 mA, RG = 25 W
tf
9.0
55.8
29
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
VGS = 0 V,
IS = 200 mA
2. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%
3. Switching characteristics are independent of operating junction temperatures
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2
TJ = 25°C
0.8
TJ = 85°C
0.7
1.2
V
2N7002W, 2V7002W
TYPICAL CHARACTERISTICS
9.0 V
8.0 V
7.0 V
6.0 V
1.2
1.2
5.0 V
4.5 V
VGS = 10 V
4.0 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
1.6
3.5 V
0.8
3.0 V
0.4
0.8
TJ = 25°C
0.4
2.5 V
0
2
4
0
6
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
TJ = 125°C
TJ = 85°C
TJ = 25°C
2.0
1.6
TJ = −55°C
1.2
0.8
0.4
0.2
0.4
0.6
0.8
1.0
1.2
6
3.2
VGS = 10 V
2.8
2.4
TJ = 125°C
2.0
TJ = 85°C
1.6
TJ = 25°C
1.2
TJ = −55°C
0.8
0.4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Drain Current and
Temperature
Figure 4. On−Resistance vs. Drain Current and
Temperature
2.4
2.2
2.0
ID = 500 mA
1.6
ID = 200 mA
1.2
0.8
0.4
4
Figure 2. Transfer Characteristics
VGS = 4.5 V
0
2
Figure 1. On−Region Characteristics
2.4
0
0
TJ = −55°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
3.2
2.8
TJ = 125°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
2
4
6
8
ID = 0.2 A
1.8
VGS = 10 V
1.4
1.0
0.6
−50
10
VGS = 4.5 V
−25
0
25
50
75
100
125
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance vs. Gate−to−Source
Voltage
Figure 6. On−Resistance Variation with
Temperature
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3
150
2N7002W, 2V7002W
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
30
C, CAPACITANCE (pF)
Ciss
20
TJ = 25°C
VGS = 0 V
Coss
10
0
Crss
0
4
8
12
16
20
5
TJ = 25°C
ID = 0.2 A
4
3
2
1
0
0
0.4
0.6
0.8
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1.0E−6
10
VGS = 0 V
IDSS, LEAKAGE (A)
VGS = 0 V
IS, SOURCE CURRENT (A)
0.2
1
TJ = 85°C
TJ = 25°C
0.1
TJ = 150°C
1.0E−7
TJ = 125°C
1.0E−8
TJ = 85°C
1.0E−9
TJ = 25°C
0.01
0.4
0.6
0.8
1.0
1.0E−10
1.2
5
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
10
15
20
25
30
35
40
45
50
55
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 9. Diode Forward Voltage vs. Current
Figure 10. Drain−to−Source Leakage Current
vs. Voltage
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4
60
2N7002W, 2V7002W
PACKAGE DIMENSIONS
SC−70 (SOT−323)
CASE 419−04
ISSUE M
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
e1
3
E
HE
1
2
b
e
A
0.05 (0.002)
c
A2
L
A1
DIM
A
A1
A2
b
c
D
E
e
e1
L
HE
MIN
0.80
0.00
0.30
0.10
1.80
1.15
1.20
2.00
MILLIMETERS
NOM
MAX
0.90
1.00
0.05
0.10
0.7 REF
0.35
0.40
0.18
0.25
2.10
2.20
1.24
1.35
1.30
1.40
0.65 BSC
0.425 REF
2.10
2.40
MIN
0.032
0.000
0.012
0.004
0.071
0.045
0.047
0.079
INCHES
NOM
0.035
0.002
0.028 REF
0.014
0.007
0.083
0.049
0.051
0.026 BSC
0.017 REF
0.083
MAX
0.040
0.004
0.016
0.010
0.087
0.053
0.055
0.095
STYLE 8:
PIN 1. GATE
2. SOURCE
3. DRAIN
SOLDERING FOOTPRINT*
0.65
0.025
0.65
0.025
1.9
0.075
0.9
0.035
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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5
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For additional information, please contact your local
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2N7002W/D