SCH5017 Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic PRODUCT FEATURES General Features — — — — — — — — — — — Data Brief 3.3 Volt Operation (SIO Block is 5 Volt Tolerant) LPC Interface Programmable Wake-up Event Interface PC99, PC2001 Compliant ACPI 2.0 Compliant Multiplexed Command, Address and Data Bus Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems PME Interface ISA Plug-and-Play Compatible Register Set 25 General Purpose Input/Output Pins System Management Interrupt AC Power Failure Recovery Watchdog Timer 2.88MB Super I/O Floppy Disk Controller — Licensed CMOS 765B Floppy Disk Controller — Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core — Supports One Floppy Drive — Configurable Open Drain/Push-Pull Output Drivers — Supports Vertical Recording Format — 16-Byte Data FIFO — 100% IBM® Compatibility — Detects All Overrun and Underrun Conditions — Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption — DMA Enable Logic — Data Rate and Drive Control Registers — 480 Address, Up to Eight IRQ and Three DMA Options — Support 3 Mode FDD Enhanced Digital Data Separator — 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates — Programmable Precompensation Modes Serial Ports — Two Full Function Serial Ports — High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs — Supports 230k and 460k Baud — Programmable Baud Rate Generator — Modem Control Circuitry — 480 Address and 15 IRQ Options SMSC SCH5017 Infrared Port — — — — Multiprotocol Infrared Interface IrDA 1.0 Compliant SHARP ASK IR 480 Addresses, Up to 15 IRQ Multi-Mode™ Parallel Port with ChiProtect™ — Standard Mode IBM PC/XT®, PC/AT®, and PS/2™ Compatible Bi-directional Parallel Port — Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) — IEEE 1284 Compliant Enhanced Capabilities Port (ECP) — ChiProtect Circuitry for Protection — 960 Address, Up to 15 IRQ and Three DMA Options Keyboard Controller — — — — — — — — — — 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer Port 92 Support Fast Gate A20 and KRESET Outputs Motherboard GLUE Logic — IDE Reset Output — (4) Buffered PCI Reset Outputs with software controlled reset capability - default transparent — 3VSB Gate and 3V Gate signal generation — Front Panel Reset Debouncing and Power Good Signal Generation — Power Supply Turn On Circuitry with Support for power button on PS/2 Keyboard — Resume Reset Signal Generation — SMBus Isolation Circuitry (2 sets external and 1 set internal for Hardware Monitoring Block) — SMBus 2.0 compliant interface for Hardware Monitoring — LED Control (2) PRODUCT PREVIEW Revision 0.5 (05-24-07) Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic Fan Control — — — — — 5 PWM (Pulse width Modulation) Outputs Two and three piece linear fan function options. Low frequency and high frequency PWM support 6 Fan Tachometer Inputs Programmable automatic fan control based on temperature — Interrupt Pin for out-of-limit Fantach Events — Fantach events generate PME’s and/or Speaker warning Voltage Monitor — Monitor Power supplies (5V, +5VTR, +12V, Vccp, Vbat, VTR, and VCC) — Limit Comparison of all Monitored Values — Interrupt Pin for out-of-limit Voltage Indication — Voltage events generate PME’s and/or Speaker warning Security Features — Security Key Register (32 byte) for Device Authentication Temperature Monitor — — — — — Monitoring of Two Remote Thermal Diodes Internal Ambient Temperature Measurement Limit Comparison of all Monitored Values Interrupt Pin for out-of-limit Temperature Indication Thermal events generate PME’s and/or Speaker warning — Configurable offset for internal or external temperature channels. 6 VID (Voltage Identification) Inputs Phoenix Keyboard BIOS ROM 128-Pin, QFP Lead-Free RoHS Compliant Package ORDER NUMBER: SCH5017-NW FOR 128-PIN, QFP LEAD-FREE ROHS COMPLIANT PACKAGE 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. 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Revision 0.5 (05-24-07) 2 PRODUCT PREVIEW SMSC SCH5017 Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic General Description The SCH5017 is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC interface. SCH5017 also includes Hardware Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic. The SCH5017's hardware monitoring capability includes temperature, voltage and fan speed monitoring. It has the ability to alert the system to out-of-limit conditions and automatically control the speeds of multiple fans. There are four analog inputs for monitoring external voltages of +5V, +5VTR, +12V and Vccp (core processor voltage), as well as internal monitoring of the SIO's VCC, VTR, and Vbat power supplies. The SCH5017 includes support for monitoring two external temperatures via thermal diode inputs and an internal sensor for measuring ambient temperature. The nHWM_INT pin is implemented to indicate out-of-limit temperature, voltage, and FANTACH conditions. The hardware monitoring block of the SCH5017 is accessible via the System Management Bus (SMBus). The same interrupt event reported on the nHWM_INT pin also creates PME wakeup events and speaker alarm annunciation. The SCH5017 also allows for a two or three piece linear fan function. The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST, SMBus buffers, and buffered PCI reset outputs. The SCH5017 incorporates complete legacy Super I/O functionality including an 8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, one serial port that is 16C550A UART compatible, one IrDA 1.0 infrared ports, and a floppy disk controller with SMSC's true CMOS 765B core and enhanced digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with SMSC's proprietary 82077AA core. System related functionality, which offers flexibility to the system designer, General Purpose I/O control functions, control of two LED's, and fan control using fan tachometer inputs and pulse width modulator (PWM) outputs The SCH5017 is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard and mouse wake-up events. The SCH5017 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH5017 may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ interface, and Three DMA channels. SMSC SCH5017 3 PRODUCT PREVIEW Revision 0.5 (05-24-07) Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic CLK32 CLOCKI SERIAL IRQ LAD[3:0] LPC Bus Interface Internal Bus (Data, Address, and Control lines) PCI_RESET# High-Speed 16550A UART PORT 2 SMbus Isolation Switch SDA SCLK SDA1 SCLK1 SDA2 SCLK2 S M b u s PCI_RESET# 96 Mhz PCI Reset Outputs 14.318Mhz HWN_INT SLP_S5# nRDATA, nWDATA SLP_S3# nDSKCHG, nDS0, Vbat nDIR, nSTEP VTR DRVDEN0*, nWRTPRT SMSC Proprietary 82077 Compatible Floppydisk Controller with Digital Data Separator & Write Precompensation PD[7,0] BUSY, SLCT, PE, nERROR, nACK nSTROBE, nINIT, nSLCTIN, nALF TXD1*, RXD1 nCTS1, nRTS1* nDSR1, nDTR1 nDCD1, nRI1 TXD2 (IRTX)*, RXD2 (IRRX)* CTS2*, RTS2 * DSR2*, DTR2* DCD2*, RI2* 32 byte Security Key Register VCC nWGATE, nHDSEL General Purpose I/O Keyboard/Mouse 8042 controller Power Control and Recovery Hardware Monitor Intruder Detection nHWM_INT VID0 VID1 VID2 VID3 VID4 VID5 / FANTACH3 +5V_IN +5VTR_IN VCCP_IN +12V_IN Remote1Remote1+ Remote2Remote2+ PWM1/xTest Out PWM2 PWM3/ ADDR_EN# FANTACH1 FANTACH2 FANTACH4/ ADDR_SEL PWMA*, PWMB* FANTACHA* FANTACHB* nMTR0, nTRK0, InNDEX Multi-Mode Parallel Port with ChiProtectTM/ FDC MUX (see LPC47B27x) Power Mgmt GP1[0:4]*, GP21*,GP22* GP27*, GP32*,GP33* GP36*, GP37* , GP4[0,2,3]* GP5[0:1]*, GP6[0:1]* LEDs High-Speed 16550A UART PORT 1 LDRQ# IO_PME_S3* IO_PME_S5* IO_SMI* LED2* WDT* WDT Speaker CLOCK GEN SER_IRQ PCI_CLK LFrame# LED1* SPEAKER Block Diagram nIDE_RSTDRV* nPCIRST_OUT[1:4]* MCLK*, MDAT* A20M* nKBDRST* KCLK*, KDAT* nFPRST, PB_IN# PWRGD_PS SLP_S3#, SLP_S5# ` PWRGD_CPU , PWRGD_3V n3VSB_GAT E n3V_GATE nRSMRST nINTRD_IN Note 1: This diagram does not show power and ground connections. Note 2: Signal names followed by an asterisk (*) are located on multifunction pins. This diagram is designed to show the various functions available on the chip and should not be used as a pin layout. Figure 1 SCH5017 Block Diagram Revision 0.5 (05-24-07) 4 PRODUCT PREVIEW SMSC SCH5017 Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic Package Outline Figure 2 128-Pin QFP Package Outline, 14X20X2.7 Body, 3.2 mm Footprint. Table 1 128-Pin QFP Package Parameters MIN ~ 0.05 2.55 23.00 19.90 17.00 13.90 0.09 0.73 ~ A A1 A2 D D1 E E1 H L L1 e q W R1 R2 ccc 0o 0.10 0.08 0.08 ~ NOMINAL ~ ~ ~ 23.20 20.00 17.20 14.00 ~ 0.88 1.60 0.50 Basic ~ ~ ~ ~ ~ MAX 3.4 0.5 3.05 23.40 20.10 17.40 14.10 0.20 1.03 ~ REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity 7o 0.30 ~ 0.30 0.08 Notes: 1. Controlling Unit: millimeter. 2. Controlling Unit: millimeter. 3. Tolerance on the position of the leads is ± 0.04 mm maximum. 4. Package body dimensions D1 and E1 do not include the mold protrusion. 5. Maximum mold protrusion is 0.25 mm. 6. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 7. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC SCH5017 5 PRODUCT PREVIEW Revision 0.5 (05-24-07)