APW8816 Single Buck PWM Controller With Linear Regulator Features General Description PWM Controller The APW8816 is a single-phase, constant on-time, • synchronous PWM controller with linear regulator, which drives N-channel MOSFETs. The APW8816 steps down Adjustable Output Voltage from +0.75V to +3.3V - 0.75V Reference Voltage high voltage to generate low-voltage chipset or RAM supplies in notebook computers. - ±1% Accuracy Over-Temperature • Operates from An Input Battery Voltage Range of The APW8816 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. +3V to +28V • Power-On-Reset Monitoring on VCC Pin and PVCC In Pulse Frequency Mode (PFM), the APW8816 provides very high efficiency over light to heavy loads with loading- Pin to Avoid Wrong Sequence • Excellent Line and Load Transient Responses • PFM Mode for Increased Light Load Efficiency • Programmable PWM Frequency from 100kHz to modulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise requirements. The APW8816 is equipped with accurate positive current 500kHz • Integrated MOSFET Drivers • Integrated Bootstrap Forward P-CH MOSFET • Integrated Soft-Start • Selectable Forced PWM or Automatic PFM/PWM limit, output under-voltage, and output over-voltage protections, perfect for various applications. The PowerOn-Reset function monitors the voltage on VCC and PVCC to prevent wrong operation during power-on. The APW8816 has a 1.5ms digital soft start and built-in an integrated output discharge device for soft stop. An internal Mode • Power Good Monitoring • 70% Under-Voltage Protection • 125% Over-Voltage Protection • Adjustable Current-Limit Protection • Over-Temperature Protection soft-start ramps up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop function actively discharges the output capacitors. The integrated linear regulator could drive an external NChannel MOSFET and provides an adjustable output by using an external resistive divider. It is easy to be used - Using Sense Low-Side MOSFET’s RDS(ON) because there is independent enable function and power OK indicator at linear regulator part. Moreover, linear LDO Controller • 0.75V Reference Voltage with 1.5% Accuracy Over regulator has soft start, under-voltage and overtemperature protection to become the great second Temperature • Independent Enable and Power OK Function • • 50% Under-Voltage Protection output voltage of the APW8816. The APW8816 is available in 16pin TQFN packages Integrated Soft-Start Function • • respectively. TQFN-16 3x3 package Applications Lead Free and Green Device Available (RoHS Compliant) • Notebook • Table PC • Hand-Held Portable • AIO PC ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 1 www.anpec.com.tw APW8816 Simplified Application Circuit LDO VIN VCC PVCC VIN LEN EN Q3 APW8816 UGATE VOUT2 Q1 VOUT1 L PHASE LFB Q2 LGATE LPOK POK Ordering and Marking Information APW8816 Package Code QB : TQFN3x3-16 Temperature Range I : -40 to 85 oC Handling Code Assembly Meterial Handling Code . Temperature Range TR : Tape & Reel Assembly Meterial G : Halogen and Lead Free Device Package Code APW8816 QB : APW 8816 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). LEN 14 16 EN 15 TON BOOT 13 Pin Configuration VOUT 1 12 UGATE VCC 2 11 PHASE FB 3 10 OCSET POK 4 9 5 6 7 8 LPOK LFB LDRV LGATE TQFN3x3-16 (TOP VIEW) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 2 PVCC = GND and Thermal Pad (connected to GND plane for better heat dissipation) www.anpec.com.tw APW8816 Absolute Maximum Ratings (Note 1) Symbol VCC VPVCC VBOOT-GND VBOOT Parameter VCC Supply Voltage (VCC to GND) Rating Unit -0.3 ~ 7 V PVCC Supply Voltage (PVCC to GND) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to GND or PGND) -0.3 ~ 37 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V -0.3 ~ VCC+0.3 V <20ns Pulse Width >20ns Pulse Width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V <20ns Pulse Width >20ns Pulse Width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V <20ns Pulse Width >20ns Pulse Width -5 ~ 35 -1 ~ 30 V V All Other Pins (VOUT, OCSET, TON, EN, LEN, LFB and FB to GND) UGATE Voltage (UGATE to PHASE) LGATE Voltage (LGATE to GND) PHASE Voltage (PHASE to GND) VPHASE VPOK POK Supply Voltage (POK to GND) -0.3 ~ 7 VLPOK LPOK to GND Voltage -0.3 ~ 7 TJ TSTG TSDR Maximum Junction Temperature Storage Temperature Maximum Soldering Temperature, 10 Seconds V 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Thermal Resistance-Junction to Ambient (Note2) TQFN3x3-16 Unit °C/W 40 Note 2: θJA are measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Recommended Operating Conditions (Note 3) Symbol VIN Parameter Converter Input Voltage Range Unit 3 ~ 28 V VCC, VPVCC VCC, PVCC Supply Voltage 4.5 ~ 5.5 V VOUT(PWM) PWM Converter Output Voltage 0.75 ~ 3.3 V VOUT(LDO) Linear Regulator Output Voltage (Note 4) 0.75~VIN(LDO) - VDROP V TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o C C Note 3: Refer to the typical application circuit. Note 4: VDROP defined as the VIN -VOUT voltage at VOUT = 98% normal VOUT. The linear regulator must provide the output MOSFET with sufficient Gate-to-Source voltage (VGS = VCC - VOUT) to regulate the output voltage. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 3 www.anpec.com.tw APW8816 Electrical Characteristics These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V, VPVCC=5V. Symbol Parameter Test Conditions APW8816 Unit Typ. Max. 0.75 - 3.3 V - 0.75 - V -0.5 - +0.5 % Min. VOUT AND VFB VOLTAGE VOUT Output Voltage VREF Reference Voltage Regulation Accuracy Adjustable output range TA = 25 oC o o TA = -40 C ~ 85 C IFB RDIS -1.0 - +1.0 % FB Input Bias Current FB = 0.75V - 0.02 0.1 µA VOUT Discharge Resistance EN = 0V, VOUT = 0.5V - 20 32 Ω SUPPLY CURRENT ICC 5V Input Bias Current VCC Plus PVCC Current, EN=Float, LEN=5V, VFB=0.8V, PHASE= -0.1V - - 900 µA ICC_SHDN 5V Shutdown Current EN=LEN=GND, VCC=PVCC=5V, VCC Plus PVCC Current - 4.5 8.5 µA 267 334 401 ns - 110 - ns 250 400 550 ns 1.5 - ms ON-TIME TIMER AND INTERNAL SOFT-START TON Nominal on time VIN=15V, VOUT=1.25V, RTON=1MΩ TON(MIN) TOFF(MIN) TSS Minimum off time VFB=0.7V, VPHASE=-0.1V, OCSET=OPEN Internal Soft Start Time EN High to VOUT Regulation 95% - UG Pull-Up Resistance BOOT-UG = 0.5V - 2 4 Ω UG Sink Resistance UG-PHASE = 0.5V - 1.5 3 Ω LG Pull-Up Resistance PVCC-LG = 0.5V - 1.5 3 Ω LG Sink Resistance LG-PGND = 0.5V - 0.7 1.4 Ω UG to LG Dead Time UG falling to LG rising, no load - 30 - ns LG to UG Dead Time LG falling to UG rising, no load - 30 - ns Bootstrap Forward Voltage VPVCC - VBOOT-GND, IF = 10mA - 0.5 0.8 V Reverse Leakage VBOOT-GND = 30V, VPHASE = 25V, VPVCC = 5V - - 0.5 µA 4.25 4.35 4.45 V - 100 - mV 4.25 4.35 4.45 V - 100 - mV GATE DRIVER BOOTSTRAP SWITCH VF IR VCC POR THRESHOLD VVCC_THR Rising VCC POR Threshold Voltage VCC POR Hysteresis VPVCC_TH R Rising PVCC POR Threshold Voltage PVCC POR Hysteresis Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 4 www.anpec.com.tw APW8816 Electrical Characteristics (Cont.) These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V, VPVCC=5V. Symbol Parameter APW8816 Test Conditions Unit Min. Typ. Max. EN High-Level Input Voltage 2.9 - - EN Float Voltage 1.61 1.9 2.19 V - - 0.8 V 350 400 450 mV - 0.1 1.0 µA 87 90 93 % 120 125 130 % - 0.1 1.0 µA 1.25 7.5 - mA CONTROL INPUTS EN Low-Level Input Voltage Hysteresis EN Leakage EN=5V V POWER-OK INDICATOR VPOK IPOK POK in from Lower (POK Goes High) POK out from Normal high threshold (POK Goes Low) POK Threshold POK Leakage Current VPOK=5V POK Sink Current VPOK=0.5V POK Out Debounce Time1 When enter high threshold - 3 - µs POK Out Debounce Time2 When run away 90% - 20 - µs POK Enable Delay Time From EN High to POK High - 4.5 - ms 18 20 22 µA - 4700 - ppm/ C CURRENT SENSE IOCSET IOCSET OCP Threshold IOCSET Sourcing TIOCSET IOCSET Temperature Coefficient On The Basis of 25°C VROCSET Current Limit Threshold Setting Range VOCSET-GND Voltage, Over All Temperature 60 - 650 mV Over current Limit Comparator Offset (VOCSET-PHASE-VGND-PHASE) Voltage, VOCSET-PHASE=200mV -10 0 10 mV Zero Crossing Comparator Offset VGND-PHASE Voltage, EN=3.3V -5 0 5 mV 60 70 80 % - 20 - µs o PROTECTION VUV UVP Threshold UVP Debounce Interval UVP Enable Delay VOVR EN high to UVP workable OVP Rising Threshold OVP Propagation Delay TOTR OTP Rising Threshold OTP Hysteresis VFB Rising, Over voltage=10mV (Note 5) (Note 5) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 5 - 4.5 - ms 120 125 130 % - 3 - µs - 155 - o C - 10 - o C www.anpec.com.tw APW8816 Electrical Characteristics (Cont.) These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V, VPVCC=5V. Symbol Parameter APW8816 Test Conditions Unit Min. Typ. Max. - - 350 LDO Controller IQ_LDO LDO Quiescent Current 1.2 - - V LEN Low-Level Input Voltage - - 0.8 V - 0.1 1.0 µA LEN=5V LDO Reference Voltage ILFB FB Input Bias Current IOUT_LDRV LDRV Output Current VLUV ILPOK TLOTR µA LEN High-Level Input Voltage LEN Leakage VLREF PWM Off, LDO On, no load 0.739 Sourcing, LFB=0.72V - 0.75 0.761 V 0.02 1 µA - 12 mA Sinking, LFB=0.75V - - 4 mA LDO Internal Soft Start Time LDO Out ramp up to LDO Out=95% - 2 - ms LDO Enable Delay LEN High to LDO Out ramp up - 1 - ms LDO UVP Threshold Measured LFB Pin 40 50 60 % LDO UVP Enable Delay LDO ramp up to UVP workable - 4 - ms LPOK in from Lower (POK Goes High) 87 90 93 % LPOK Debounce Time When run away 90% LPOK Sink Current VLPOK=0.5V LPOK Leakage Current VLPOK=5V LDO OTP Rising Threshold (Note 5) OTP Hysteresis (Note 5) - 20 - µs 1.25 7.5 - mA - 0.1 1.0 µA - 155 - o C - o C - 10 Note 5: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 6 www.anpec.com.tw APW8816 Typical Operating Characteristics Switch Frequecy vs. Input Voltage 300 Output Voltage vs. Input Voltage 1.54 Output Voltage(V) Switch Frequecy(kHz) 1.53 200 100 1.52 1.51 1.5 Force 1.49 Auto 1.48 0 0 5 10 15 20 25 1 30 3 5 7 9 11 13 15 17 19 21 23 25 27 Input Voltage(V) Input Voltage(V) Switch Frequency vs. Output Current Output Voltage vs Output Current 300 1.530 Auto Force Output Voltage(V) Switch Frequency(kHz) 250 200 150 100 1.520 Vin=8V 1.510 1.500 50 Auto Force 0 1490 0 4 8 12 16 20 0 5 Outpue Current(A) 10 15 20 Output Current(A) Output Voltage vs Output Current Reference Voltage vs Junction Temperature 0.7495 1.530 0.749 Auto Force Reference Voltage(V) 0.7485 Output Voltage(V) 1.520 Vin=19V 1.510 1.500 0.748 0.7475 0.747 0.7465 0.746 0.7455 0.745 1.490 0.7445 0 5 10 15 20 0 20 40 60 80 100 120 Junction Temperature (oC) Output Current(A) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 -20 7 www.anpec.com.tw APW8816 Typical Operating Characteristics Iocset vs Junction Temperature 35 30 Iocset (uA) 25 20 15 10 5 0 -20 0 20 40 60 80 100 120 Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 8 www.anpec.com.tw APW8816 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Enable(Auto) Enable(Forced PWM ) 1 VEN VPHASE VPHASE 2 2 3 VEN 1 VOUT VOUT 3 VPOK VPOK 4 4 CH1:VEN , 2V/Div CH2:VPHASE , 10V/Div CH3:VOUT , 1V/Div CH4:VPOK , 5V/Div TIME: 1ms/Div CH1:VEN , 2V/Div CH2:VPHASE , 10V/Div CH3:VOUT , 1V/Div CH4:VPOK , 5V/Div TIME: 1ms/Div Load Transient Disable(15A) VOUT 1 VEN 1 VUGATE 2 2 VLGATE VPHASE IL 3 3 V OUT 4 4 CH1: VOUT , 100mV/Div CH2:VPHASE , 10V/Div CH3: I L,10A/Div CH4: IOUT ,10A/Div TIME: 20us/Div CH1: VEN, 5V/Div CH2: VUGATE , 20V/Div CH3: VLGATE , 5V/Div CH4: VOUT , 1V/Div TIME: 10us/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 IOUT 9 www.anpec.com.tw APW8816 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Over-Voltage-Protection Pre-short-protection V FB 1 VCC 1 2 V OUT V OUT 2 V LGATE V UGATE 3 3 4 4 IL IL CH1: VFB , 1V/Div CH2: VOUT, 1V/Div CH3: VLGATE , 5V/Div CH4: IL, 10A/Div TIME: 100us/Div CH1: VCC, 2V/Div CH2: VOUT, 500mV/Div CH3: VUGATE , 5V/Div CH4: IL, 10A/Div TIME: 5ms/Div LDO On by LEN Under-Voltage-Protection VFB VLEN 1 1 VOUT VLGATE 2 2 V POK 3 V UGATE VLDRV 3 4 CH1: VLEN, 5V/Div CH2: VOUT , 500mV/Div CH3: VPOK , 5V/Div CH4: VLDRV, 2V/Div TIME: 2ms/Div CH1: VFB, 1V/Div CH2: V LGATE, 5V/Div CH3: VUGATE , 10V/Div TIME: 20us/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 10 www.anpec.com.tw APW8816 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. LDO Short Circuit LDO load Transient VOUT 1 1 VPOK 2 2 VLDRV 3 3 V LDRV IL CH1: VOUT, 100mV/Div CH2: VLDRV, 2V/Div CH3: IL, 2A/Div TIME: 100us/Div CH1: VOUT, 500mV/Div CH2: VPOK, 5V/Div CH3: VLDRV , 2V/Div TIME: 20us/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 V OUT 11 www.anpec.com.tw APW8816 Pin Description Pin PIN FUNCTION NO. NAME 1 VOUT 2 VCC 3 FB 4 POK Power Good Output. POK is an open drain output used to indicate the status of the output voltage. Connect the POK in to +5V through a pull-high resistor. 5 LPOK LDO Power Good Output. LPOK is an open drain output used to indicate the status of the output voltage. Connect the LPOK in to +5V through a pull-high resistor. 6 LFB 7 LDRV This pin drives the gate of an external N-channel MOSFET for linear regulator. 8 LGATE Output of The Low-side MOSFET Driver. Connect this pin to Gate of the low-side MOSFET. Swings from GND to PVCC. 9 PVCC Supply Voltage Input Pin for The LG Low-side MOSFET Gate Driver. Connect +5V from the PVCC pin to the GND pin. Decoupling at least 1µF of a MLCC capacitor from the PVCC pin to the GND pin. 10 OCSET Current Limit Threshold Setting Pin. There is an internal source current 20µA through a resistor from OCSET pin to GND. This pin is used to monitor the voltage drop across the Drain and Source of the low-side MOSFET for current limit. 11 PHASE Junction Point of The High-side MOSFET Source, Output Filter Inductor And The Low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UG high-side gate driver. 12 UGATE Output of The High-side MOSFET Driver. Connect this pin to Gate of the high-side MOSFET. 13 BOOT Supply Input for The UG Gate Driver And An Internal Level-shift Circuit. Connect to an external capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. 14 LEN Enable Pin of The Linear Regulator. When the LEN is above high logic level, the LDO is enabled. When the LEN is below low logic level, the LDO is disabled. 15 EN Enable Pin of The PWM Controller. When the EN is above high logic level, the device is in automatic PFM/PWM Mode. When the EN is floating, the device is in force PWM mode. When the EN is below low logic level, the device is in shutdown. 16 TON This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON from TON pin to VIN. Exposed pad GND Signal Ground for The IC The VOUT Pin Makes A Direct Measurement of The Converter Output Voltage. The VOUT pin should be connected to the top feedback resistor at the converter output. Supply Voltage Input Pin for Control Circuitry. Connect +5V from the VCC pin to the GND pin. Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the GND pin. Output Voltage Feedback Pin. This pin is connected to the resistive divider that set the desired output voltage. The POK, UVP, and OVP circuits detect this signal to report output voltage status. LDO Output Voltage Feedback Pin. This pin is connected to the resistive divider that set the desired output voltage. The LPOK and UVP circuits detect this signal to report output voltage status. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 12 www.anpec.com.tw APW8816 Block Diagram PWM Controller POK VOUT GND 125% VREF Current Limit Delay OCSET EN 20uA POR 90% VREF 125% VREF Frequency Adjustable OV Fault Latch Logic 70% VREF BOOT Thermal Shutdown FB On-Time Generator ZC Error Comparator Digital Soft Start/Soft Sop VCC UG PWM Signal Controller UV TON PHASE PVCC PHASE LG VREF Force PWM or Automatic PFM/PWM Selection VCC POR VPVCC EN Linear Regulator SoftStart LDRV VREF 0.75V Error Amplifier UVP Comparator LEN Enable LFB Control Logic UV 50%VREF 1.2V LPOK Enable_EA PWOK Power-OK Comparator Delay GND 90%VREF Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 13 www.anpec.com.tw APW8816 Typical Application Circuit APW8816 VLPOK LPOK VPOK POK RTON 1MΩ Q1 APM4350 UG RPOK 100kΩ RLPOK 100kΩ VIN(PWM) 19V TON CIN 10µF BOOT PHASE +5V CBOOT 0.1µF LOUT 1.0µH 1.5V/20A V OUT( PWM) ROCSET PVCC COUT 330µF OCSET RVCC 2.2Ω 6.8kΩ,5% CPVCC 1µF LG VCC Q2 APM4354 RTOP 10kΩ,1% CVCC 1µF GND VOUT VIN( LDO) 3.3V Q3 APM4354 1.8V VOUT(LDO) FB LDRV EN LDO COUT1 22µF LDO COUT2 10µF RLTOP 14kΩ,1% RLGND 10kΩ,1% R1 C2 LFB LEN RGND 10kΩ,1% C1 Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 14 www.anpec.com.tw APW8816 Function Description Constant-On-Time PWM Controller with Input Feed-Forward Where FSW is the nominal switching frequency of the converter in PWM mode. The load current at handoff from PFM to PWM mode is given by: The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This architec- 1 VIN − VOUT × × TON-PFM 2 L V − VOUT 1 V = IN × x OUT 2L FSW VIN ture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, so ILOAD(PFM to PWM) = the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled Forced-PWM Mode by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input volt- The Forced-PWM mode disables the zero-crossing age and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by comparator, which truncates the low-side switch on-time at the inductor current zero crossing. This causes the a switching frequency control circuit in the on-time generator block. low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. This in turn causes The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat- the inductor current to reverse at light loads while UGATE maintains a duty factor of VOUT/VIN. The benefit of Forced- ing it at a constant frequency in PWM mode. The design improves the frequency variation and is more outstand- PWM mode is to keep the switching frequency fairly constant. The Forced-PWM mode is most useful for re- ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, ducing audio frequency noise, improving load-transient response, and providing sink-current capability for dy- output current, and temperature. Both in PFM and PWM, the on-time generator, which senses input voltage on namic output voltage adjustment. Power-On-Reset TON pin, provides very fast on-time response to input line transients. A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the PVCC or VCC voltage is Another one-shot sets a minimum off-time (typical: 400ns). The on-time one-shot is triggered if the error com- low. The POR function continually monitors the bias supply voltage on the PVCC and VCC pins if at least one of parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time oneshot has timed out. the enable pins is set high. When the rising PVCC voltage reaches the rising PVCC POR voltage threshold Pulse-Frequency Modulation (PFM) (4.35V, typical) and the rising VCC voltage reaches the rising VCC POR Threshold (4.35V, typical), the POR sig- In PFM mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This nal goes high and the chip initiates soft-start operations. There is almost no hysteresis to POR voltage threshold switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero (about 100mV typical). When PVCC voltage drops lower than 4.25V (typical) or VCC voltage drops lower than crossing. This mechanism causes the threshold between PFM and PWM operation to coincide with the boundary 4.25V (typical), the POR disables the chip. EN Pin Control between continuous and discontinuous inductor-current operation (also known as the critical conduction point). When V EN is above the EN high threshold (2.9V, Minimum), the converter is enabled in automatic PFM/ The on-time of PFM is given by: TON-PFM = PWM operation mode. When EN pin is floating, APW8816 internal circuit will pull V EN up to 1.9V (Typical). V 1 × OUT FSW VIN Furthermore, APW8816 is in Forced-PWM operation mode. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 15 www.anpec.com.tw APW8816 Function Description (Cont.) During soft-start stage before the POK pin is ready, the under-voltage protection is prohibited. The over-voltage EN Pin Control (Cont.) When VEN is below the EN low threshold (0.8V, Maximum), and current-limit protection functions are enabled. If the output capacitor has residue voltage before start-up, both the chip is in the shutdown and only low leakage current is taken from VCC. low-side and high-side MOSFETs are in off-state until the internal digital soft-start voltage equals to the VFB voltage. The linear regulator controller has a dedicated enable pin (LEN). A logic low signal applied to this pin shuts This will ensure that the output voltage starts from its existing voltage level. down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft- In the event of under-voltage, over-voltage, overtemperature, or shutdown, the chip enables the soft-stop start cycle. It’s not necessary to use an external transistor to save cost. function. The soft-stop function discharges the output voltages to the PGND through an internal 20Ω switch. Digital Soft-Start The linear regulator controller provides an internal softstart circuitry to control rise rate of the output voltage and The APW8816 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. The slew limit the current surge during start-up. Typical soft-start interval is about 2ms. rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- Power OK Indicator start process. The figure 1 shows soft-start sequence. When the EN pin is pulled above the rising EN threshold The APW8816 features an open-drain POK pin to indicate output regulation status. In normal operation, when voltage, the device initiates a soft-start process to ramp up the output voltage. The soft-start interval is 1.5ms the output voltage rises 90% of its target value, the POK goes high. When the output voltage outruns 90% or 125% (typical) and independent of the UGATE switching frequency. of the target voltage, POK signal will be pulled low after internal delay. Since the FB pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled 4.5ms directly to the FB pin by the capacitor in parallel with the voltage divider as shown in the typical applications. In VCC and VPVCC 1.5ms order to prevent false POK from dropping, capacitors need to parallel at the output to confine the voltage deviation VOUT with severe load step transient. The linear regulator controller indicates the status of the EN output voltage by monitoring the feedback voltage (VLFB) on LFB pin. As the VLFB rises and reaches the rising PowerOK voltage threshold (VPOKTH), the IC turns off the internal NMOS of the LPOK to indicate that the output is ok. As the V LFB falls and reaches the falling Power-OK voltage threshold, the IC turns on the NMOS of the LPOK (after a VPOK debounce time of 20µs typical). Figure 1. Soft-Start Sequence Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 16 www.anpec.com.tw APW8816 Function Description (Cont.) Current-Limit Under-Voltage Protection (UVP) The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 2). The APW8816 uses the In the operational process, if a short-circuit occurs, the output voltage will drop quickly. When load current is big- low-side MOSFET’s RDS(ON) of the synchronous rectifier as a current-sensing element. If the magnitude of the ger than current-limit threshold value, the output voltage will fall out of the required regulation range. The under- current-sense signal at PHASE pin is above the currentlimit threshold, the PWM is not allowed to initiate a new voltage protection circuit continually monitors the FB voltage after soft-start is completed. If a load step is strong cycle. The actual peak current is greater than the currentlimit threshold by an amount equals to the inductor ripple enough to pull the output voltage lower than the undervoltage threshold, the under-voltage threshold is 70% of current. Therefore, the exact current-limit characteristic and maximum load capability are the functions of the the nominal output voltage, the internal UVP delay counter starts to count. After 20µs debounce time, the device turns sense resistance, inductor value, and input voltage. IPEAK INDUCTOR CURRENT, IL off both high-side and low-side MOSEFET with latched and starts a soft-stop process to shut down the output gradually. Toggling enable pin to low or recycling PVCC or VCC, will clear the latch and bring the chip back to operation. The linear regulator controller monitors the voltage on LFB. When the voltage on LFB falls below the undervoltage threshold, the UVP circuit shuts off the output voltage immediately by pulling down LDRV to 0V and latches controller off, requiring either a VCC POR or EN re-en- IOUT ∆I ILIMIT 0 Time able again to restart. Figure 2. Current-Limit Algorithm Over-Voltage Protection (OVP) The PWM controller uses the low-side MOSFETs on-re- The over-voltage function monitors the output voltage by sistance R DS(ON) to monitor the current for protection against shortened outputs. The MOSFET’s RDS(ON) is var- FB pin. When the FB voltage increases over 125% of the reference voltage due to the high-side MOSFET failure or ied by temperature and gate to source voltage, the user should determine the maximum RDS(ON) in manufacture’s for other reasons, the over-voltage protection comparator designed with a 3µs noise filter will force the low-side datasheet. The OCSET pin can source 20µA through an external MOSFET gate driver fully turn on and latch high. This action actively pulls down the output voltage. In the meantime, resistor for adjusting current-limit threshold. The voltage at OCSET pin is equal to 20µA x ROCSET. The relationship the output voltage is also pulled low by internal discharge transistor. between the sampled voltage VOCSET and the current-limit threshold ILIMIT is given by: This OVP scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise acti- 20µA x ROCSET = ILIMIT x RDS(ON) Where R OCSET is the resistor of current-limit setting vated with a continuously high output from low-side MOSFET driver. It’s a common problem for OVP schemes threshold. RDS(ON) is the low side MOSFETs conducive resistance. ILIMIT is the setting current-limit threshold. ILIMIT with a latch. Once an over-voltage fault condition is set, it can only be reset by toggling EN, PVCC or VCC power on can be expressed as IOUT minus half of peak-to-peak inductor current. reset signal. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 17 www.anpec.com.tw APW8816 Function Description (Cont.) Current-Limit (cont.) Where: The PCB layout guidelines should ensure that noise and FSW is the PWM switching frequency. APW8816 doesn’t have VIN pin to calculate on-time pulse DC errors do not corrupt the current-sense signals at PHASE. Place the hottest power MOSEFTs as close to width. Therefore, monitoring VTON voltage as input voltage to calculate on-time. And then, use the relationship be- the IC as possible for best thermal coupling. When combined with the under-voltage protection circuit, this cur- tween ontime and duty cycle to obtain the switching frequency. rent-limit method is effective in almost every circumstance. Over-Temperature Protection (OTP) When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the overtemperature protection state that suspends the PWM, which forces the UGATE and LGATE gate drivers output low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 10oC. The OTP is designed with a 10oC hysteresis to lower the average TJ during continuous thermal overload conditions, which increases lifetime of the APW8816. Programming the On-Time Control and PWM Switching Frequency The APW8816 does not use a clock signal to produce PWM. The device uses the constant-on-time control architecture to produce pseudo-fixed frequency with input voltage feed-forward. The on-time pulse width is proportional to output voltage VOUT and inverses proportional to input voltage VIN. In PWM, the on-time calculation is written as below : VOUT TON = 3.85 × 10 -12 × RTON (VIN - 0.5 ) Where: RTON is the resistor connected from TON pin to VIN. Furthermore, the approximate PWM switching frequency is written as : TON = D ⇒ FSW = FSW VOUT VIN TON Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 18 www.anpec.com.tw APW8816 Application Information Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased Output Voltage Setting The output voltage is adjustable from 0.75V to 3.3V with a and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regu- resistor-divider connected with FB, GND, and converter’s output. Using 1% or better resistors for the resistor-di- lator load transient response time. A smaller inductor will give the regulator a faster load vider is recommended. The output voltage is determined by: R TOP V OUT = 0.75 × 1 + R GND transient response at the expense of higher ripple current. Increasing the switching frequency (F SW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipa- Where 0.75 is the reference voltage, RTOP is the resistor connected from converter’s output to FB, and RGND is the tion of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to resistor connected from FB to GND. Suggested RGND is in the range from 1k to 20kΩ. To prevent stray pickup, locate resistors RTOP and RGND close to APW8816. choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has The linear regulator controller,an external N-channel MOSFET should be connected to LDRV as the pass been chosen, selecting an inductor which is capable of carrying the required peak current without going into element. The output voltage set by the resistor divider is determined by: saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase R VOUT(LDO) = 0.75 × 1 + LTOP RLGND abruptly when it saturates. This results in a larger output ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. Output Capacitor Selection Where RLTOP is connected from VOUT to LFB and RLGND is Output voltage ripple and the transient voltage deviation are factors which have to be taken into consider- connected from LFB to GND. ation when selecting an output capacitor. Higher capacitor value and lower ESR reduce the output ripple and Output Inductor Selection The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage the load transient drop. Therefore, selecting high performance low ESR capacitors is recommended for is fixed, it can be written as: D= switching regulator applications. In addition to high frequency noise related to MOSFET turn-on and turn- VOUT VIN off, the output voltage ripple includes the capacitance voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused The inductor value (L) determines the inductor ripple by the AC peak-to-peak inductor’s current. These two voltages can be represented by: current, IRIPPLE, and affects the load transient reponse. Higher inductor value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: ∆VESR IRIPPLE IRIPPLE 8COUTFSW = IRIPPLE × RESR ∆VCOUT = VIN - VOUT VOUT = × FSW × L VIN Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 19 www.anpec.com.tw APW8816 Application Information (Cont.) • In the turning off process of the low-side MOSFET, the Output Capacitor Selection (cont.) These two components constitute a large portion of the total output voltage ripple. In some applications, multiple load current will shift to the body diode first. The high dv/ dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support path. This results in much less switching loss of the lowside MOSFETs. The duty cycle is often very small in high another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR battery voltage applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, when and suppress the voltage ripple to a tolerable level. A small decoupling capacitor (1µF) in parallel for bypass- using smaller RDS(ON) of the low-side MOSFET, the converter can reduce power loss. The gate charge for this ing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing MOSFET is usually the secondary consideration. The high-side MOSFET does not have this zero voltage switching condition; in addition, because it conducts for less time compared to the low-side MOSFET, the switching the voltage excursion during load step change. Another aspect of the capacitor selection is that the total AC cur- loss tends to be dominant. Priority should be given to the MOSFETs with less gate charge, so that both the gate rent going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to driver loss and switching loss will be minimized. prevent the capacitor from over-heating. The selection of the N-channel power MOSFETs are Input Capacitor Selection determined by the R DS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement. The input capacitor is chosen based on the voltage rating The losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, and low-side MOSFETs, the losses are approximately given by the following equations: 2 Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current. 2 Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be- Where I is the load current OUT TC is the temperature dependency of RDS(ON) tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout. MOSFET Selection FSW is the switching frequency tSW is the switching interval The application for a notebook battery with a maximum D is the duty cycle voltage of 28V, at least a minimum 30V MOSFETs should be used. The design has to trade off the gate charge with Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, tSW , is the function of the reverse the RDS(ON) of the MOSFET: • For the low-side MOSFET, before it is turned on, the transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be body diode has been conducting. The low-side MOSFET driver will not charge the miller capacitor of this MOSFET. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. 20 www.anpec.com.tw APW8816 Application Information (Cont.) • The PGND is the current sensing circuit reference Layout Consideration ground and also the power ground of the LGATE low- In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. side MOSFET. On the hand, the PGND trace should be a separate trace and independently go to the source of the With power devices switching at higher frequency, the resulting current transient will cause voltage spike across low-side MOSFET. Besides, the current sense resistor should be close to OCSET pin to avoid parasitic capaci- the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition tor effect and noise coupling. • Decoupling capacitors, the resistor-divider, and boot of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic high-side MOSFET as close as possible.) • The input bulk capacitors should be close to the drain inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’s ground wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. should be close to the grounds of the output capacitors and low-side MOSFET. Besides, signal and power grounds are to be kept separating and finally combined using ground plane construc- • Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega- can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE). tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout: • Keep the switching nodes (UGATE, LGATE, BOOT, and Recommended Minimum Footprint PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. TQFN3x3-16 3mm Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. • The signals going through theses traces have both MOSFETs (UGATE and LGATE) should be short and wide. • Place the source of the high-side MOSFET and the drain 0.24mm 1.66 mm high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers to the 0.5mm * 3mm 0.5mm of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the 0.508mm 1.66mm 0.162mm two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can get better heat sinking. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 * Just Recommend 21 www.anpec.com.tw APW8816 Package Information TQFN3x3-16 D b E A Pin 1 D2 A1 A3 L K E2 Pin 1 Corner e S Y M B O L TQFN3x3-16 INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.012 0.50 0.020 0.008 Note : Follow JEDEC MO-220 WEED-4. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 22 www.anpec.com.tw APW8816 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN3x3-16 A H T1 C d D 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 W E1 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type TQFN3x3-16 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 Quantity 3000 23 www.anpec.com.tw APW8816 Taping Direction Information TQFN3x3-16 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 24 www.anpec.com.tw APW8816 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 25 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8816 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2013 26 www.anpec.com.tw