GA03IDDJT30-FR4 Isolated Gate Driver Gate Driver for SiC SJT with Output and Signal Isolation Features VISOLATION PDRIVE fmax = = = 3000 V 5W 350 kHz Product Image Requires single 12 V voltage supply Pin Out compatible with MOSFET driver boards Multiple Internal level topology for low drive losses High-side drive capable with 3000 V isolation 5000 V Signal Isolation (up to 10 s) Capable of high gate currents with 3 W maximum power RoHS Compliant Section I: Introduction The GA03IDDJT30-FR4 provides an optimized gate drive solution for SiC Junction Transistors (SJT). The board utilizes DC/DC converters and FOD3182 opto-isolators making it capable of driving high and low-side devices in a half-bridge configuration as well as IXDN609 gate driver ICs providing fast switching and customizable continuous gate currents necessary for SJT devices. Its footprint and 12 V supply voltage make it a plug-in replacement for existing SiC MOSFET gate drive solutions. Figure 1: Simplified GA03IDDJT30-FR4 Gate Drive Board Block Diagram Section II: Compatibility with SiC SJTs The GA03IDDJT30-FR4 has an installed RG of 3.75 Ω on-board which may need to be modified by the user for safe operation of certain SJT parts. Please see the table below and Section VII for more information. Table 1: GA03IDDJT30-FR4 – SiC SJT Compatibility Information Table SJT Part Number GA03JT12-247 GA05JT12-247/263 GA06JT12-247 GA10JT12-247/263 GA20JT12-247/263 GA50JT12-247 GA04JT17-247 GA16JT17-247 GA50JT17-247 Nov. 2014 Compatible Yes Requires RG Modification Not Required Not Required Not Required Recommended (see Section VII) Required (see Section VII) Required (see Section VII) Not Required Required (see Section VII) Required (see Section VII) http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 9 GA03IDDJT30-FR4 Isolated Gate Driver Section III: Operational Characteristics Parameter Symbol Input Supply Voltage Input Signal Voltage, Off Input Signal Voltage, On Input Signal Current, On Propagation Delay, Signal Turn On Propagation Delay, Signal Turn Off Output Gate Current, Peak Output Gate Current, Continuous Output Gate Voltage Rise Time Output Gate Voltage Fall Time Operating Frequency Power Dissipation SJT Drain – Source Voltage Isolation Voltage, Signal Isolation Voltage, Voltage Supply Storage Temperature Product Weight VCC Vsig, OFF Vsig, ON Isig, ON td,ON td,OFF IG,ON IG,steady tr tf fsw Ptot VDS VISO-SIG VISO-DC T Conditions Min. 10.8 -5 3.2 20 VCC High, VCC Low D = 0.3, f < 350 kHz Cload = 10 nF Cload = 10 nF Value Typical 12 0 5.0 36 160 187 4 0.35 21 14 Dependant on device driven and CG 3.0 W (VGL) + 2.0 W (VGH + VEE) On driven power transistor -55 Max. 13.2 0.8 6.4 50 270 270 9.0 1.8 35 25 350 5.0 1700 ±5000 ±3000 100 19 Unit Notes V V V mA ns ns A A ns ns kHz W V V V °C g Section IV: Pin Out Description VCC Low RTN VCC Low Signal RTN Signal VCC High RTN VCC High Source Source Source Gate Gate Gate Figure 2: Gate Drive Board Top View Header JP1 JP1 JP1 JP1 JP1 JP1 Gate Gate Gate Source Source Source Nov. 2014 Table 2: GA03IDDJT30-FR4 Pin Out Connections Pin Label Suggested Connection VCC High VCC High RTN Signal Signal RTN VCC Low VCC Low RTN Gate Gate Gate Source Source Source + 12 V, > 6 W Supply Analog Ground Gate Drive Control Signal Analog Ground + 12 V, > 6 W Supply Analog Ground SJT Gate Pin SJT Gate Pin SJT Gate Pin SJT Source Pin SJT Source Pin SJT Source Pin http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 9 Isolated Gate Driver GA03IDDJT30-FR4 Section V: SJT Gate Driving Theory of Operation The SJT transistor is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 3. This is similar to what the GA03IDDJT30-FR4 provides. An SJT is rapidly switched on when the necessary gate charge, QG, for turn-on is supplied by a burst of high gate current, IG,on, until the gatesource capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. , The IG,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the VGS,ON level to counter these effects. After the SJT is turned on, IG may be lowered to IG,steady for reducing unnecessary gate drive power losses. The minimum IG,steady is determined by noting the DC current gain, hFE, of the device from its datasheet. The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain hFE, and a 50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation: , , 1.5 For SJT turn -off, a high negative peak current, -IG,off at the start of the turn-off transition rapidly sweeps out charge from the gate. While satisfactory turn off can be achieved with VGS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. The GA03IDDJT30-FR4 provides a negative bias of -5 V during off state. Figure 3: Idealized SJT Gate Current Waveform Nov. 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 3 of 9 GA03IDDJT30-FR4 Isolated Gate Driver Section VI: Gate Driver Implementation The GA03IDDJT30-FR4 is a gate driver circuit which can be used to drive an SJT transistor by supplying the required gate drive current IG in a low-power gate drive solution. This configuration features a gate capacitor CG (CG1 and CG2 in parallel) which creates a brief current peak IG,ON during device turn-on and IG,OFF during turn-off for fast switching and a gate resistor RG (RG1 and RG2 in parallel) to set the continuous gate current IG,steady required for an SJT to operate. This configuration is shown in the Figure 7 circuit diagram as well as in Figure 4 below with further details provided below. This section provides detail on selecting optimal CG and RG values based on the SJT, drain current, and temperature. Figure 4: Primary gate drive circuit passive components with series gate resistance Schottky rectifier. Symbol RG CG R4 D1 Table 3: Passive Output Component List Values Parameter Range Default Gate Resistor, On Board 0 – 20 3.75 Gate Capacitor, On Board 5 – 20 10 Charging Resistor 500 – 10k 1k Schottky Diode of Gate Resistor --- Units Ω nF Ω A: Gate Resistor RG Modification The GA03IDDJT30-FR4 on board gate resistor RG controls the continuous current IG,steady during steady on-state. The gate current is determined according to: , , 0.6Ω 4.7 , , 0.6Ω Where VGL is the internal, low-level drive voltage (5 V), VGS,sat is the driven SJT saturated gate-source voltage obtained from the individual device datasheets, VD is the Schottky diode voltage drop (approximately 0.3 V), and 0.6 Ω is added from internal GA03IDDJT30-FR4 drive components. It is necessary for the user to reduce RG from its pre-install value of 3.75 Ω for several SiC SJTs for safe operation with the GA03IDDJT30FR4 under high drain current conditions. The location of RG on the circuit board is shown in Figure 5. The maximum allowable value of RG for each device across all rated drain currents can be found in the Gate Drive section of each individual device datasheets. RG may also be calculated from the following equation, where hFE is the SJT DC current gain and VGS,sat is the gate-source saturation voltage. Both of these values may be taken from individual device datasheets. 4.7 , , , 1.5 0.6 For some devices and drain currents it may be desired for the user to install a very low value of RG or to short RG (RG = 0 Ω) to increase the gate current output. This is acceptable, but may limit the duty cycle D during operation. Please see section VII:B for more information. B: Duty Cycle Limitation The duty cycle D of the GA03IDDJT30-FR4 output may be limited by the 3 W power capability of the internal 5 V supply in some applications. If RG remains un-changed by the user IG,steady will remain sufficiently low to allow 100 % duty cycle operation with an SJT. However, if RG is shorted or reduced such that RG ≤ 2.8 Ω in order to drive higher current devices, the duty cycle will be limited by the following equation: 3 5 Nov. 2014 0.9 , http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 4 of 9 GA03IDDJT30-FR4 Isolated Gate Driver Figure 5: Location of RG (RG1 and RG2 in parallel) on GA03IDDJT30-FR4 driver for substitution C: Gate Capacitor CG Modification An external gate capacitor CG connected directly to the device gate pin delivers the positive current peak IG,ON during device turn-on and the negative current peak IG,OFF during turn-off. A high value resistor R4 in parallel with CG sets the SJT gate pin to a defined potential (-VEE) during steady off-state. At device turn-on, CG is pulled to the GA03IDDJT30-FR4 internal voltage level VGH which produces a transient peak of gate voltage and current. This current peak rapidly charges the internal SJT CGS and CGD capacitances. A Schottky diode, D1, in series with RG blocks any CG induced current from draining out through RG and ensures that all of the charge within CG flows only into the device gate, allowing for an ultrafast device turn-on. During steady on-state, a potential of VGH - VGS = VGH – 3 V is across CG. When the device is turned off, CG is pulled to negative VEE and VGS is pulled to a transient peak of VGS,turn-off = VEE – (VGH – 3 V), this induces the negative current peak IG,off out of the gate which discharges the SJT internal capacitances. D: Voltage Supply Selection The GA03IDDJT30-FR4 gate drive design features three internal supply voltages VGH, VGL, and VEE (listed in Table 4) supplied through two DC/DC converters. During device turn-on, VGH charges the capacitor CG thereby delivering the narrow width, high current pulse IG,ON to the SJT gate and charges the SJT’s internal terminal capacitances CGD and CGS. For a given level of parasitic inductance in the gate circuit and SJT package, the rise time of IG,ON is controlled by the value of VGH and CG. During the steady on-state, VGL in combination with the internal and external gate resistances provides a continuous gate current for the SJT to remain on. The VEE supply controls the gate negative voltage during turn-off and steady off-state for faster switching and to avoid spurious turn-on which may be caused by external circuit noise. The power rating of the provided voltage supplies are adequate to meet the gate drive power requirements as determined by , , 1 2 1 2 , , Table 4: GA03IDDJT30-FR4 Gate Drive Voltage Supply Component List Values Symbol Parameter Range Default VGH Supply Voltage, Gate Capacitor 15 – 20 + 20.0 VGL Supply Voltage, Gate Resistor 5.0 – 7.0 + 5.0 VEE Negative Supply Voltage -10 – GND - 5.0 E: Voltage Supply Isolation The DC/DC supply voltage converters are suggested to provide isolation at a minimum of twice the working VDS on the SJT transistor during off-state to provide adequate protection to circuitry external to the gate drive circuit. The installed DC/DC converters have an isolation of 3.0 kV and greater. Alternatively, DC/DC converter galvanic isolation may be bypassed and direct connection of variable voltage supplies may Nov. 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 5 of 9 Isolated Gate Driver GA03IDDJT30-FR4 be done in a laboratory environment, this may be convenient during testing and prototyping but carries risk and is not suggested for extended usage. Figure 6: Typical DC/DC converter configuration F: Signal Isolation The gate supply signal is suggested to be isolated to twice the working VDS on the SJT during off-state to provide adequate protection to circuitry external to the gate drive circuit. This may be done using opto or galvanic isolation techniques. Nov. 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 6 of 9 GA03IDDJT30-FR4 Isolated Gate Driver Section VII: Detailed Schematic and Bill of Materials C2 +12 V GA03IDDJT30-FR4 Gate Driver Board VGL VCC High U3 C5 VCC High RTN CG1 VGL VGH Signal R1 R2 U1 CG2 U5 R4 C9 VEE C6 Gate Signal VEE C10 VGL R3 U2 RG1 U6 D1 Signal RTN VEE VEE G SiC SJT RG2 S C8 VGH VCC Low +12 V D IG Gate VGL C1 U4 VCC Low RTN C3 C4 Source VEE Voltage Isolation Barrier Figure 7: Gate Drive Board Detailed Block Diagram #ITEM Designator 1 C1, C2, C3, C4, C5 2 CG1, CG2 3 C6, C7, C9 4 C10 5 C8 6 R2, R3 7 R1 8 R4 9 RG1, RG2 10 D1 11 U1, U2 12 GATE, SOURCE 13 JP1 14 U3 15 U4 16 U5, U6 17 -- Nov. 2014 Table 5: Gate Drive Board Bill of Materials Package Manufacturer (Metric) Capacitor, Ceramic, 1µF, 50V, 3216 TDK 10%, X7R, 1206 Corporation Capacitor, Ceramic, 4700pF, 4532 Murata 250VAC, X7R, 1812 Electronics NA Capacitor, Ceramic, 0.1µF, 3216 Yageo 50V, 10%, X7R, 1206 Capacitor, Ceramic, 22µF, 35V, 3216 TDK 20%, X5R, 1206 Corporation Capacitor, Ceramic, 100µF, 3225 Taiyo Yuden 16V, 20%, X5R, 1210 Resistor, 10 Ω, 1/4W, 1%, 3216 Rohm 1206, SMD Semiconductor Resistor, 100 Ω, 1/4W, 1%, 3216 Yageo 1206, SMD Resistor, 1 KΩ, 1/4W, 1%, 3216 Yageo 1206, SMD Resistor, 7.50 Ω, 1W, 1%, 6332 Vishay Dale 2512, SMD Schottky Diode, 60V, 2A, SMB SMB Fairchild Semiconductor Optocoupler, 3A, 8-SMD 8-SMD Fairchild Semiconductor Connector Breakaway, Header 3POS HEADER TE Connectivity 0.100IN, 3POS, Vertical Connector Breakaway, Header 6POS HEADER TE Connectivity 0.100IN, 6POS, Vertical 7-SIP Module Murata Power DC/DC Converter, 3W, VIN = 12V, VO = 5V, 7-SIP 7-SIP Module Murata Power DC/DC Converter, 2W, VIN = 12V, VO = 20/- 5V Dual, 7-SIP Gate Driver IC, 9A, Non8-SOIC IXYS IC Inverting, 8-SOIC Gate Driver Circuit Board, PCB GeneSiC 0.062” Thickness, 4oz Cu Semiconductor Description Manufacturer Part Quantity Number / Board C3216X7R1H105K160AB 5 GA343DR7GD472KW01L 2 CC1206KRX7R9BB104 3 C3216X5R1V226M160AC 1 EMK325ABJ107MM-T 1 MCR18ERTF10R0 2 RC1206FR-07100RL 1 RC1206FR-071KL 1 CRCW25127R50FKEG 2 SS26 1 FOD3182S 2 5-146274-3 2 3-644456-6 1 MEV3S1205SC 1 MGJ2D122005SC 1 IXDN609SI 2 GA03IDDJT30-FR4 1 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 9 Isolated Gate Driver GA03IDDJT30-FR4 Section VIII: Mechanical Drawing Figure 8: Gate Drive Board Mechanical Drawing Nov. 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 8 of 9 Isolated Gate Driver GA03IDDJT30-FR4 Revision History Date Revision Comments 2014/11/14 1 Updated Characteristics 2014/08/29 0 Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Nov. 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 9 of 9