Data Sheet

[AK7736B]
AK7736B
Audio/HF DSP with 2Ch SRC
1. General Description
The AK7736B is a highly integrated audio digital signal processor with integrated 2ch SRC. It includes
internal memories for digital audio processing, that allows surround effect process, time alignment and
parametric equalizing. Moreover, the AK7736B can process both data and filter coefficients as floating point
data so that high accuracy IIR/FIR filter performance can be achieved easily. The AK7736B can operate a
hands-free software by AKM as well as sound processing, by programs downloaded via the microprocessor
interface.
2. Features
□ DSP Block
- Word length: 24-bit
- Machine Cycle: 8.1 ns (2560step/fs; fs = 48kHz)
- Step
fs=48kHz: Maximum 2560 step
fs=8kHz: Maximum 15360step
fs=16kHz: Maximum 7680step
- Multiplication: 20 x 24 → 44-bit (Double precision arithmetic available)
- Divider 20 / 20 → 20-bit (floating point normalization function)
- ALU: 48-bit arithmetic and logic operation (overflow margin 4-bit)
- Shift: Multiple DBUS ±15bit Shift with indirect shifting function
- Program RAM (PRAM): 6144word x 36-bit
- Coefficient RAM (CRAM): 4096word x 24-bit
- Data RAM (DRAM): 4096 x 24-bit (Variable Bank Size)
- Offset Register (OFREG): 32word x 15-bit
- Delay RAM (DLRAM): 16384word x 24-bit (Variable Bank Size)
- Register:
48-bit × 4 (ACC) [ALU]
24-bit × 12 (TMP) [DBUS connection]
24-bit × 6 level stack (PTMP) [DBUS connection]
□ Stereo 24-bit SRC
-SRC: FSI=8kHz to 96kHz / FSO=8kHz to 96kHz (FSO/FSI = 0.167 to 6.0)
□ Mono 24-bit Simple SRC
-FSCONV: FSI=44.1kHz to 48kHz / FSO=8kHz to 16kHz
□ Digital Interface Input/Output
- 8ch Serial Data Inputs
- 8ch Serial Data Outputs
- Sampling Frequency: 8kHz to 96kHZ
□ Microcontroller Interface: SPI, I2CBUS (400kHz Fast-Mode)
□ PLL
□ Power Supply
-VDD: 3.0 to 3.6V typ 3.3V (Internal Regulator)
-TVDD: 1.7 to 3.6V (1~8pin)
□ Operating Temperature Range: -40°C to 85°C
□ Package: 48-pin LQFP
MS1562-E-00-PB
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[AK7736B]
3. Table of Contents
1. General Description ....................................................................................................................................... 1
2. Features.......................................................................................................................................................... 1
3. Table of Contents ........................................................................................................................................... 2
4. Block Diagram and Functions ....................................................................................................................... 3
5. Pin Configurations and Functions ................................................................................................................. 5
■ Ordering Guide ......................................................................................................................................... 5
■ Pin Layout ................................................................................................................................................ 5
■ Pin Functions ............................................................................................................................................ 6
■ Handling of Unused Pin ........................................................................................................................... 7
■ Output pin Status in Power-down Mode (PDN pin = “L”) ...................................................................... 8
■ Relationship between the I2CSEL Pin and the SDA Pin ......................................................................... 8
6. Absolute Maximum Ratings .......................................................................................................................... 8
7. Recommended Operating Conditions ............................................................................................................ 8
8. Electrical Characteristics ............................................................................................................................... 9
■ SRC Characteristics .................................................................................................................................. 9
■ DC Characteristics .................................................................................................................................. 10
■ Current Consumption ............................................................................................................................. 10
9. Digital Filter Characteristics ......................................................................................................................... 11
■ SRC Block .............................................................................................................................................. 11
■ FSCONV Block ...................................................................................................................................... 11
10. Switching Characteristics .......................................................................................................................... 12
■ System Clock .......................................................................................................................................... 12
■ Power Down ........................................................................................................................................... 12
■ Serial Data Interface ............................................................................................................................... 13
■ Microprocessor Interface ........................................................................................................................ 14
■ I2C-BUS Interface................................................................................................................................... 14
■ Timing Diagram ..................................................................................................................................... 15
11. Package ...................................................................................................................................................... 20
■ Outline Dimensions ................................................................................................................................ 20
■ Materials and Lead Specification ........................................................................................................... 20
■ Marking .................................................................................................................................................. 21
Revision History .............................................................................................................................................. 21
IMPORTANT NOTICE ................................................................................................................................... 22
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[AK7736B]
4. Block Diagram and Functions
Figure 1. Block Diagram
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[AK7736B]
Pointer
CP0, CP1
DP0, DP1
Coefficient RAM
DLP0, DLP1
Data RAM
4096w x 24-Bit
4096w x 24-Bit
OFREG
32w x 15-Bit
Delay RAM
16384w x 24-Bit(20.4f)
CBUS(24-Bit)
DBUS(24-Bit)
MPX24
Micon I/F
MPX20
X
Control
DEC
Y
Serial I/F
PRAM
6144w x 36-Bit
Multiply
24 x 20  44-Bit
PC
Stack: 5level(max)
24-Bit
44-Bit
TMP 12 x 24-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
2 x 16/20/24-Bit DIN4
SHIFT
48-Bit
2 x 16/20/24-Bit DIN3
44-Bit
A
2 x 16/20/24-Bit DIN2
2 x 16/20/24-Bit DIN1
B
ALU
2 x 16/20/24-Bit DOUT4
48-Bit
2 x 16/20/24-Bit DOUT3
Overflow Margin: 4-Bit
2 x 16/20/24-Bit DOUT2
48-Bit
2 x 16/20/24-Bit DOUT1
DR0  3
48-Bit
Accelerator
Over Flow Data
Generator
Division 202020
Peak Detector
Figure 2. AK7736B Main DSP Block Diagram
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[AK7736B]
5. Pin Configurations and Functions
■ Ordering Guide
AK7736BVQ -40 to +85C
48-pin LQFP (0.5mm pitch)
AKD7736B
Evaluation Board for AK7736B
■ Pin Layout
SDA
SI/CAD0
CSN/CAD1
SDIN4
BITCLKI2/JX1
LRCLKI2/JX2
SO
STO
32
31
29
28
27
25
26
SCLK/SCL
33
30
VSS
VDD
35
34
AVDRV
36
AK7736BLQFP
BITCLKI3
40
21
SDIN2A
LRCLKI3
41
48pin LQFP
20
PDN
SDIN2C
42
(TOP VIEW)
19
I2CSEL
JX0
43
18
VDD
EXPDN
44
17
VSS
VDD
45
16
RDY
TESTI2
46
15
SDOUT2A
VSS
47
14
SDOUT3
LFLT
48
13
SDOUT4
MS1562-E-00-PB
XTO
XTI
VSS
TVDD
LRCLK1
BITCLK1
TESTI3
SDIN2B
SDIN1
SDOUT1
SDOUT2B
TESTI1
Note) **** is an Internal pull-down pin.
12
LRCLKO
11
22
10
39
9
VDD
8
BITCLKO
7
23
6
38
5
VSS
4
CLKO
3
24
2
37
1
SDIN3
PIN
Input
Output
I/O
Power
***: Pin Name
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[AK7736B]
■ Pin Functions
No
Name
1 TESTI1
I/O
I
2
3
4
5
6
SDOUT2B
SDOUT1
SDIN1
SDIN2B
TESTI3
O
O
I
I
I
7
8
9
10
11
BITCLK1
LRCLK1
TVDD
VSS
XTI
I/O
I/O
I
12 XTO
O
13
14
15
16
17
18
19
O
O
O
O
I
SDOUT4
SDOUT3
SDOUT2A
RDY
VSS
VDD
I2CSEL
20 PDN
I
21
22
23
24
25
26
SDIN2A
LRCLKO
BITCLKO
CLKO
STO
SO
I
O
O
O
O
O
27 LRCLKI2
JX2
28 BITCLKI2
JX1
29 SDIN4
I
I
I
I
Function
Classification
Test Pin (Internal pull-down)
Test
This pin must be connected to VSS.
Serial Data2 B Output Pin
Serial Data
Serial Data1 Output Pin
Serial Data1 Input Pin
Serial Data
Serial Data2 B Input Pin
Test Pin (Internal pull-down)
Test
This pin must be connected to VSS
Serial Bit Clock Pin 1 (Internal pull-down)
System Clock
LR Channel Select Clock Pin 1 (Internal pull-down)
Power Supply Pin for 1pin-8pin I/O 1.7 to 3.6V
Power Supply
Ground Pin 0V
Crystal Oscillator Input Pin
System Clock
Connect a crystal oscillator between this pin and the XTO pin,
or input an external clock to the XTI pin.
Crystal Oscillator Output Pin
When a crystal oscillator is used, connect it between XTI and
XTO. When an external clock is used, leave this pin open.
Serial Data4 Output Pin
Serial Data
Serial Data3 Output Pin
Serial Data2 A Output Pin
RDY Pin
Status
Ground Pin 0V
Power Supply
Power Supply Pin 3.0 to 3.6V (typ. 3.3V)
I2C BUS Select Pin
I2C
I2CSEL= “L”: SPI Interface
I2CSEL= “H”: I2CBUS Interface
I2CSEL should be connected to “L” (VSS) or “H” (VDD).
Power Down N Pin
Power Down
The AK7736B is powered-down by this pin.
This pin must be set to “L” when power-up the AK7736B
Serial Data2 A Input Pin
Serial Data
LR Channel Select Clock Pin
System Clock
Serial Bit Clock Output Pin
Clock Output Pin
Clock Output
Status Output Pin
Status
Control Data Output Pin for Microprocessor Interface
Microprocessor
Hi-Z output when the CSN pin = “H”
Interface
LR Channel Select Clock Pin 2 (for FSCONV)
System Clock
External Conditional Jump Pin 2
Conditional Input
Serial Bit Clock Input Pin 2 (for FSCONV)
System Clock
External Conditional Jump Pin 1
Conditional Input
Serial Data4 Input Pin
Serial Data
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[AK7736B]
Microprocessor Interface Request N Pin (I2CSEL pin= “L”)
Set this pin to “H” when not interfacing to a microprocessor or during
power-down.
CAD1
I I2CBUS Address Pin 1 (I2CSEL pin= “H”)
SI
I Serial Data Input Pin for Microprocessor Interface
Set this pin to “L” when not using.
2
CAD0
I I C BUS Address Pin 0 (I2CSEL pin= “H”)
SDA
O Control Data Input /Output Pin (I2CSEL pin= “L”)
“Hi-Z” Output. This pin must be open when the I2CSEL pin = “L”.
I/O Control Data Input /Output Pin (I2CSEL pin= “H”)
SDA: I2C BUS Interface
SCLK
I Control Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”)
Set this pin to “H” when no clock is input.
SCL
I Control Data Clock Pin (I2CSEL pin= “H”)
SCL: I2C BUS Interface
VDD
- Power Supply Pin 3.0 to 3.6V (typ. 3.3V)
VSS
- Ground Pin 0V
AVDRV
AVDRV pin
Connect a 1F capacitor between this pin and the VSS pin (No. 35).
No external circuits should be connected to this pin.
SDIN3
I Serial Data3 Input Pin
VSS
- Ground Pin 0V
VDD
- Power Supply Pin 3.0 to 3.6V (typ. 3.3V)
BITCLKI I Serial Bit Clock Input Pin 3 (for SRC)
3
LRCLKI3 I LR Channel Select Clock Pin 3 (for SRC)
SDIN2C
I Serial Data2 C Input Pin
30 CSN
31
32
33
34
35
36
37
38
39
40
41
42
I
43 JX0
I
44 EXPDN
45 VDD
TESTI2
46
O
I
External Conditional Jump Pin 0
Power Down Signal Output Pin
Power Supply Pin 3.0 to 3.6V (typ. 3.3V)
Test Pin (internal pull-down)
This pin must be connected to VSS.
47 VSS
- Ground Pin 0V
LFLT
O PLL RC Component Connect Pin
48
Connect C=12nF between this pin and No.47 (VSS) pin.
Note 1. All digital input pins must not be allowed to float
Note 2. The I2CSEL pin must be fixed to “L” (VSS) or “H” (TVDD).
Microprocessor
Interface
I2C
Microprocessor
Interface
I2C
Open
I2C
Microprocessor
Interface
I2C
Power Supply
Analog Output
Serial Data
Power Supply
System Clock
Serial Data
Conditional
Input
Power Down
Power Supply
Test
Power Supply
Analog Output
■ Handling of Unused Pin
Unused I/O pins must be connected appropriately:
Pin Name
Setting
Output Pins
Leave Open
Input/Output Pins
SDA
Leave Open
LRCLK1
Connect to VSS
BITCLK1
Connect to VSS
Input Pins
Connect to VSS
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[AK7736B]
■ Output pin Status in Power-down Mode (PDN pin = “L”)
No
2
3
7
8
12
13
14
15
16
Pin Name
SDOUT2B
SDOUT1
BITCLK1
LRCLK1
XTO
SDOUT4
SDOUT3
SDOUT2A
RDY
I/O
O
O
I/O
I/O
O
O
O
O
O
Power-down Status
“L” Output
“L” Output
Input
Input
“H” Output
“L” Output
“L” Output
“L” Output
“L” Output
No
22
23
24
25
26
32
44
48
Pin Name
LRCLKO
BITCLKO
CLKO
STO
SO
SDA
EXPDN
LFLT
I/O
O
O
O
O
O
I/O
O
O
Power-down Status
“L” Output
“L” Output
“L” Output
“L” Output
“Hi-Z” Output
“Hi-Z” Output
“L” Output
“L” Output
■ Relationship between the I2CSEL Pin and the SDA Pin
SPI
Interface
I2C BUS support
I2CSEL
L
L
H
H
PDN
L
H
L
H
SDA
Hi-Z
Hi-Z
“Hi-Z” → pull-up
function
6. Absolute Maximum Ratings
(VSS=0V: All voltages are with respect to ground)
Parameter
Symbol
Power Supply
TVDD
TVDD
VDD
VDD
Input Current (except for power supply pin)
IIN
Digital Input Voltage (1pin-8pin)
VINDT
Digital Input Voltage (except 1pin-8pin)
VIND
Operating Ambient Temperature
Ta
Storage Temperature
Tstg
min
max
Unit
-0.3
-0.3
–
-0.3
-0.3
-40
-65
4.3
4.3
±10
(TVDD+0.3)
(VDD+0.3)
85
150
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS=0V: All voltages are with respect to ground.)
Parameter
Symbol
min
typ
max
Unit
Power Supply
TVDD
TVDD
1.7
1.8
3.6
V
VDD
VDD
3.0
3.3
3.6
V
Note 3. The TVDD pin is the power supply pin for pin number 1 ~ 8 pins.
Note 4. The power-up sequence with VDD and TVDD is not critical. The PDN pin should be held “L” when
power is supplied. The PDN pin is allowed to be “H” after all power supplies are applied and settled.
Note 5. Do not turn off the power supply of the AK7736B with the power supply of the surrounding device
turned on. VDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for
VDD in the SDA and SCL pins.)
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[AK7736B]
8. Electrical Characteristics
■ SRC Characteristics
1) SRC
(Ta= -40°C to 85°C; TVDD=1.8V, VDD=3.3V; VSS=0V; data = 24bit; measurement bandwidth = 20Hz~FSO/2;
unless otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
8
96
kHz
Output Sample Rate
FSO
8
96
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=44.1kHz/96kHz
-111
dB
FSO/FSI=48kHz/44.1kHz
-112
dB
FSO/FSI=48kHz/96kHz
-113
dB
FSO/FSI=48kHz/8kHz
-111
-103
dB
FSO/FSI=16kHz/48kHz
-113
dB
FSO/FSI=16kHz/44.1kHz
-100
dB
FSO/FSI=8kHz/48kHz
-113
dB
FSO/FSI=8kHz/44.1kHz
-95
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
113
dB
FSO/FSI=44.1kHz/96kHz
113
dB
FSO/FSI=48kHz/44.1kHz
113
dB
FSO/FSI=48kHz/96kHz
113
dB
FSO/FSI=48kHz/8kHz
108
113
dB
FSO/FSI=16kHz/48kHz
113
dB
FSO/FSI=16kHz/44.1kHz
113
dB
FSO/FSI=8kHz/48kHz
111
dB
FSO/FSI=8kHz/44.1kHz
114
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted)
FSO/FSI=44.1kHz/48kHz
115
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
2) FSCONV
(Ta= -40°C to 85°C; TVDD=1.8V, VDD=3.3V; VSS=0V; data = 24bit; measurement bandwidth = 20Hz~FSO/2;
unless otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
44.1
48
kHz
Output Sample Rate
FSO
8
16
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=16kHz/48kHz
-114
dB
FSO/FSI=16kHz/44.1kHz
-95
dB
FSO/FSI=8kHz/48kHz
-115
dB
FSO/FSI=8kHz/44.1kHz
-97
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=16kHz/48kHz
114
dB
FSO/FSI=16kHz/44.1kHz
114
dB
FSO/FSI=8kHz/48kHz
114
dB
FSO/FSI=8kHz/44.1kHz
114
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted)
FSO/FSI=8kHz/48kHz
117
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
0.363
Note 6. Input signal frequency bandwidth of FSCONV must be attenuated more than 4kHz when the output
sampling rate is 8kHz, or must be attenuated more than 8kHz when the output sampling rate is
16kHz.
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[AK7736B]
■ DC Characteristics
(Ta= -40°C to 85°C, VSS=0V, VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V)
Parameter
Symbol
min
typ
max
Unit
High Level Input Voltage 1 (Note 7)
VIH1
80%TVDD
V
Low Level Input Voltage 1 (Note 7)
VIL1
20%TVDD
V
High Level Input Voltage 2 (Note 8)
VIH2
80%VDD
V
Low Level Input Voltage 2 (Note 8)
VIL2
20%VDD
V
SCL, SDA High Level Input Voltage
VIH3
70%VDD
V
SCL, SDA Low Level Input Voltage
VIL3
30%VDD
V
High Level Output Voltage1 Iout= -100A (Note 7)
VOH1
TVDD-0.3
V
1.7 ≤ TVDD < 3.0
3.0 ≤ TVDD ≤ 3.6
VOH1
TVDD-0.5
Low Level Output Voltage1 Iout=100A (Note 7)
VOL1
0.3
V
1.7 ≤ TVDD < 3.0
3.0 ≤ TVDD ≤ 3.6
VOL1
0.5
VOH2
VDD-0.5
V
High Level Output Voltage2 Iout= -100A (Note 8)
VOL2
0.5
V
Low Level Output Voltage2 Iout=100A (Note 8)
SDA Low Level Output Voltage Iout=3mA
VOL3
0.4
V
Input Leak Current
(Note 9)
Iin
±10
A
Input Leak Current with pulled-down (Note 10)
Iid
81
A
Note 7. TESTI1, SDOUT2B, SDOUT1, SDIN1, SDIN2B, TESTI3, BITCLK1 and LRCLK1 pins. Pin no.
1 to 8.
Note 8. Except 1pin-8pin, SDA and SCL pins
Note 9. Pull-down pins, and the XTI pin is not included.
Note 10. LRCLK1, BITCLK1, TESTI1, TESTI2 and TESTI3 pins are internal pulled-down pin. (typ.
40.7kΩ)
56H
57H
58H
59H
60H
61H
62H
63H
64H
65H
■ Current Consumption
(Ta=25°C, VSS=0V, VDD=3.0 to 3.6V(typ=3.3V, max=3.6V), TVDD=1.7 to 3.6V(typ=1.8V, max=3.6V))
Parameter
min
typ
max
Unit
Normal Operation Mode (Note 11) TVDD
0.3
0.5
mA
VDD
31
mA
50
Power-down Mode
TVDD
0.01
A
(PDN = L)
VDD
1
A
Note 11. The current consumption changes depending on the system frequency and contents of the DSP
program.
6H
MS1562-E-00-PB
2013/10
- 10 -
[AK7736B]
9. Digital Filter Characteristics
■ SRC Block
(Ta= -40°C to 85°C, VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V)
Parameter
Symbol
min
typ
max
Unit
Passband -0.01dB
0.980≤FSO/FSI≤6.000
PB
0
0.4583FSI
kHz
0.900≤FSO/FSI<0.990
PB
0
0.4167FSI
kHz
0.533≤FSO/FSI<0.909
PB
0
0.2182FSI
kHz
0.490≤FSO/FSI<0.539
PB
0
0.2177FSI
kHz
0.450≤FSO/FSI<0.495
PB
0
0.1948FSI
kHz
0.225≤FSO/FSI<0.455
PB
0
0.1312FSI
kHz
Passband -0.50dB
0.167≤FSO/FSI<0.227
PB
0
0.0658FSI
kHz
Stopband
0.980≤FSO/FSI≤6.000
SB
0.5417FSI
kHz
0.900≤FSO/FSI<0.990
SB
0.5021FSI
kHz
0.533≤FSO/FSI<0.909
SB
0.2974FSI
kHz
0.490≤FSO/FSI<0.539
SB
0.2812FSI
kHz
0.450≤FSO/FSI<0.495
SB
0.2604FSI
kHz
0.225≤FSO/FSI<0.455
SB
0.1802FSI
kHz
0.167≤FSO/FSI<0.227
SB
0.0970FSI
kHz
Passband Ripple
0.225≤FSO/FSI≤6.000
PR
±0.01
dB
0.167≤FSO/FSI<0.227
PR
±0.50
dB
Stopband Attenuation
0.450≤FSO/FSI≤6.000
SA
95.2
dB
0.167≤FSO/FSI<0.455
SA
90.0
dB
Group Delay
GD
(Tsi=1/fsi,Tso=1/fso)
54Tsi + 9Tso
Tsi,Tso
(Note 12)
Note 12. This delay is the a period from the rising edge of LRCLKI3, just after the data is input, to the rising
edge of LRCLKO, just before the data is output, when there is no phase difference between Input
and Output signals.
67H
■ FSCONV Block
(Ta= -40°C to 85°C, VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V)
Parameter
Symbol
min
typ
max
Unit
Passband -0.01dB
0.167≤FSO/FSI≤0.363
PB
0
0.1814FSI
kHz
Stopband
0.167≤FSO/FSI≤0.363
SB
0.8185FSI
kHz
Passband Ripple
0.167≤FSO/FSI≤0.363
PR
±0.005
dB
Stopband Attenuation 0.167≤FSO/FSI≤0.363
SA
94.0
dB
Group Delay
(Tsi=1/fsi,Tso=1/fso)
GD
8Tsi + 1Tso
Tsi,Tso
(Note 13)
Note 6. Input signal frequency bandwidth of FSCONV must be attenuated more than 4kHz when the output
sampling rate is 8kHz, or must be attenuated more than 8kHz when the output sampling rate is
16kHz.
Note 13. This delay is the a period from the rising edge of LRCLKI2, just after the data is input, to the rising
edge of LRCLKO, just before the data is output, when there is no phase difference between Input
and Output signals.
68H
69H
MS1562-E-00-PB
2013/10
- 11 -
[AK7736B]
10. Switching Characteristics
■ System Clock
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V; CL=20pF)
Parameter
Symbol
min
typ
max
a) with a Crystal Oscillator
CKM[2:0]bits=0h
fXTI
11.2896
MHz
12.288
CKM[2:0]bits=1h
fXTI
16.9344
MHz
18.432
b) with an External Clock
Duty Cycle
40
50
60
%
CKM[2:0]bits=0h,2h
fXTI
11.0
11.2896
12.4
MHz
12.288
CKM[2:0]bits=1h
fXTI
16.5
16.9344
18.6
MHz
18.432
LRCLK1 Frequency
(Note 14)
fs
8
96
kHz
BITCLK1 Frequency
(Note 15)
32,48,64
fs
High Level Width
tBCLKH
64
ns
Low Level Width
tBCLKL
64
ns
Frequency
fBCLK
0.23
3.072
6.2
MHz
LRCLKI2 Frequency (FSCONV) (Note 16) fs
44.1
48
kHz
BITCLKI2 Frequency (FSCONV) (Note 17)
32,48,64,12
fs
8
High Level Width
tBCLKH
64
ns
Low Level Width
tBCLKL
64
ns
Frequency
fBCLK
1.25
3.072
6.2
MHz
LRCLKI3 Frequency (SRC)
fs
8
96
kHz
BITCLKI3 Frequency (SRC)
32,48,64,12
fs
8
High Level Width
tBCLKH
32
ns
Low Level Width
tBCLKL
32
ns
Frequency
fBCLK
0.23
3.072
12.4
MHz
Note 14. LRCLK1 frequency and sampling rate (fs) should be the same.
Note 15. When BITCLK1 is used as a master clock reference clock, it should be synchronized with LRCLK1,
and its frequency should be fixed.
Note 16. fs=8~48kHz in CKM mode 4.
Note 17. 128fs is inhibited in CKM mode 4.
70H
71H
72H
73H
■ Power Down
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V)
Parameter
Symbol
min
PDN
(Note 18)
tRST
600
Note 18. The PDN pin must be “L” when power up the AK7736B.
74H
MS1562-E-00-PB
typ
max
Unit
ns
2013/10
- 12 -
[AK7736B]
■ Serial Data Interface
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V; CL=20pF)
Parameter
Symbol
min
typ
DSP Section Input SDIN1, 2A, 2B, 2C, 3, 4 (Note 19)
Delay Time from BITCLK1 “↑” to LRCLK1 (Note 20) tBLRD
20
Delay Time from LRCLK1 to BITCLK1 “↑” (Note 20) tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
80
Serial Data Input Latch Hold Time
tBSIDH
80
SRC Section Input SDIN3
Delay Time from BITCLKI3 “↑” to LRCLKI3 (Note 21)
tBLRD
20
Delay Time from LRCLKI3 to BITCLKI3 “↑” (Note 21)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
FSCONV Section Input SDIN4
(Note 22)
Delay Time from BITCLKI2 “↑” to LRCLKI2 (Note 23)
tBLRD
20
Delay Time from LRCLKI2 to BITCLKI2 “↑” (Note 23)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
Output SDOUT1, SDOUT2, SDOUT3, SDOUT4
BITCLKO Frequency
(Note 24)
fBCLK
64
BITCLKO Duty Factor
(Note 24)
50
Delay Time from BITCLKO “↓” to LRCLKO (Note 25)
tMBL
-20
Delay Time from LRCLK1 to Serial Data Output (Note 26) tLRD
Delay Time from BITCLK1“↓” to Serial Data Output
tBSOD
(Note 27)
Delay Time from LRCLKO to Serial Data Output (Note 26) tLRD
Delay Time from BITCLKO “↓” to Serial Data Output
tBSOD
(Note 28)
SDINn → SDOUTn (n=1, 2A, 2B, 2C, 3, 4)
Delay Time from SDINn to SDOUTn Output
tIOD
Note 19. In CKM mode 4, these are the time from LRCKLI2 or BITCLKI2.
Note 20. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↓”.
Note 21. When BITCLKI3 polarity is inverted, delay time is from BITCLKI3 “↓”.
Note 22. Except CKM mode 4.
Note 23. When BITCLKI2 polarity is inverted, delay time is from BITCLKI2 “↓”.
Note 24. Except slave mode.
Note 25. When BCKOP bit = “1”, delay time is from BITCLKO “↑”.
Note 26. Except I2S compatible mode.
Note 27. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↑”.
Note 28. When BITCLKO polarity is inverted, delay time is from BITCLKO “↑”.
max
Unit
75H
ns
ns
ns
ns
76H
7H
ns
ns
ns
ns
78H
79H
80H
ns
ns
ns
ns
81H
82H
83H
84H
85H
86H
40
80
80
fs
%
ns
ns
ns
87H
8H
80
80
89H
MS1562-E-00-PB
60
ns
2013/10
- 13 -
[AK7736B]
■ Microprocessor Interface
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
min
typ
Microprocessor Interface Signal
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
200
SCLK High Level Width
tSCLKH
200
Microprocessor → AK7736B
CSN High Level Width
tWRQH
500
From CSN “↑” to PDN “↑”
tRST
600
From PDN “↑” to CSN “↓”
tIRRQ
1
From CSN “↓” to SCLK “↓”
tWSC
500
From SCLK “↑” to CSN “↑”
tSCW
800
SI Latch Setup Time
tSIS
200
SI Latch Hold Time
tSIH
200
AK7736B → Microprocessor
Delay Time from SCLK “↓” to SO Output
tSOS
Hold Time from SCLK “↑” to SO Output (Note 29) tSOH
200
Note 29. Except when input the eighth bit of the command code.
max
Unit
2.1
MHz
ns
ns
ns
ns
ms
ns
ns
ns
ns
200
90H
ns
ns
■ I2C-BUS Interface
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
min
I2C Timing
SCL clock frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed By Input Filter tSP
0
Capacitive load on bus
Cb
MS1562-E-00-PB
typ
max
Unit
400
kHz
s
s
s
s
s
s
s
s
s
s
ns
pF
0.9
0.3
0.3
50
400
2013/10
- 14 -
[AK7736B]
■ Timing Diagram
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH2
VIL2
1/fs
ts=1/fs
1/fs
LRCLK1(I)
LRCLKI2
VIH1,2
LRCLKI3
VIL1,2
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
BITCLK1(I)
VIH1,2
BITCLKI2
VIL1,2
BITCLKI3
tBCLKH
tBCLKL
Figure 3. System Clock
PDN
tRST
VIL2
Figure 4. Power-down
MS1562-E-00-PB
2013/10
- 15 -
[AK7736B]
VIH1
VIL1
D
LRCLK1(I)
tBLRD
D
tLRBD
D
BITCLK1(I)
VIH1
VIL1
D
tBSIDS
D
tBSIDH
VIH1,2
VIL1,2
D
SDINn
n=1,2A,2B,2C,3,4
D
VIH2
VIL2
D
LRCLKI3
tBLRD
D
tLRBD
D
BITCLKI3
VIH2
VIL2
D
tBSIDS
D
tBSIDH
VIH2
VIL2
D
SDIN3
D
VIH2
VIL2
D
LRCLKI2
tBLRD
BITCLKI2
D
tLRBD
D
VIH2
VIL2
D
tBSIDS
D
tBSIDH
VIH2
VIL2
D
SDIN4
D
Figure 5. Slave Mode Input Interface
50%VDD
LRCLKO
D
tMBL
tMBL
D
BITCLKO
tBSIDS
50%VDD
D
tBSIDH
VIH1, 2
VIL1,
2
D
SDINn
n=1, 2A, 2B, 2C, 3, 4
D
Figure 6. Master Mode Input Interface
MS1562-E-00-PB
2013/10
- 16 -
[AK7736B]
VIH1
VIL1
D
LRCLK1(I)
D
tLRD
D
BITCLK1(I)
tLRD
SDOUTn D
n=1,2A,2B,3,4
VIH1
VIL1
D
tBSOD
tBSOD D
D
D
50%VDD, TVDD
D
Figure 7. Slave Mode Output Interface
LRCLKO
LRCLK1(O)
50%VDD
D
tLRD
D
BITCLKO
BITCLK1(O)
tLRD
D
SDOUTn
n=1,2A,2B,3,4
50%VDD
D
tBSOD
tBSOD
D
Figure 8. Master Mode Output Interface
MS1562-E-00-PB
D
50%VDD,TVDD
D
2013/10
- 17 -
[AK7736B]
VIH3
VIL3
CSN
tWRF
tWRR
tSF
tSR
VIH3
VIL3
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
VIH3
PDN
VIL3
VIH3
CSN
VIL3
tRST
tIRRQ
Figure 9. Microprocessor Interface Signal
VIH3
VIL3
tWRQH
CSN
VIH3
SI
VIL3
tSIS
tSIH
VIH3
VIL3
SCLK
tWSC
tSCW
tWSC
tSCW
Figure 10. Microprocessor → AK7736B
MS1562-E-00-PB
2013/10
- 18 -
[AK7736B]
SCLK
VIH3
VIL3
SO
50%VDD
tSOH
tSOS
Figure 11. AK7736B → Microprocessor
VIH3
SDA
VIL3,VOL3
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH3
SCL
VIL3
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 12. I2C-BUS Interface
MS1562-E-00-PB
2013/10
- 19 -
[AK7736B]
11. Package
■ Outline Dimensions
48pin LQFP (Unit mm)
(ASECL: LQFP48-7x7-0.50 PP-C-06-B268)
■ Materials and Lead Specification
Package: Epoxy
Lead frame: Copper
Lead-finish: Soldering (Pb free) plate
MS1562-E-00-PB
2013/10
- 20 -
[AK7736B]
■ Marking
AKM
AK7736BVQ
XXXXXXX
￥0VT
48
1
1) pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK7736BVQ
4) Asahi Kasei Logo
Revision History
Date (Y/M/D) Revision Reason
13/10/03
00
First Edition
Page
Contents
MS1562-E-00-PB
2013/10
- 21 -
[AK7736B]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants any
license to any intellectual property rights or any other rights of AKM or any third party with respect
to the information in this document. You are fully responsible for use of such information contained
in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR
ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF
SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do
not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and regulations.
The Products and related technology may not be used for or incorporated into any products or
systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
Thank you for your access to AKM product information.
More detail product information is available, please contact our
sales office or authorized distributors.
MS1562-E-00-PB
2013/10
- 22 -