Pulsed IV/RF Measurements for Compact Model Extraction Your Calibration, Measurement & Modeling Solutions Partner! System Design from Compact Models Component level Pulsed IV and RF measurements Angelov GaN FET model extraction VNA Load Pull model validation Circuit level IC Design - ADS IC X-Parameter model - ADS Your Calibration, Measurement & Modeling Solutions Partner! System level Simulation at system level Compact FET model extraction flow 1.18 1.6 y = 0.0049x + 0.6889 1.2 Rs 1 0.6 1.04 0.4 1.02 0 Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Non-linear capacitances IV Model 1.1 1.08 1.06 y = 0.0029x + 0.6375 0.8 Small-Signal y = -0.0008x + 1.1543 1.12 Idss Rs, Rd 1.16 1.14 Rd 1.4 50 100 T°C 150 200 0 50 100 T°C 150 200 Thermal model Trapping effects Dgs=f(Vgs) Dgs=f(Vgs,T) Dgd=f(Vgd) Dgd=f(Vgd,T) Ids=f(Vgs,Vds) Ids=f(Vgs,Vds,T) Ids=f(Vgs_trap,Vds,T) Cgs=f(Vgs) Cgd=f(Vgd) Rs=f(T) Rd=f(T) Various effects are successively added Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements – Why? Self-Heating Trapping Effects Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements – How? Short pulse : Quasi-isothermal conditions Low duty cycle : Constant mean temperature Quiescent bias point : Thermal conditions fixed Several quiescent bias point Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV – Block Diagram How to get accurate pulsed IV measurements ? PIV system Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV – Accuracy Considerations How to get accurate pulsed IV measurements ? Gate +20V 15 bits + sign 250V Drain 16 bits 15 bits + sign 25V -20V Pulse shape monitoring 20ns time resolution Your Calibration, Measurement & Modeling Solutions Partner! 16 bits Pulsed IV – Accuracy Considerations How to get accurate pulsed IV measurements ? 1A AM212 100mA Gate access 33µA 4mA 1A 3,3µA 400µA 100mA 10mA 330nA 40µA 10mA 1mA 33nA 4µA 1mA 0mA -2V -20V 650µV 20mV 20V 65µV 2mV 2V 0V Measurement Resolution Voltage Absolute Accuracy Voltage Range Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV – Accuracy Considerations How to get accurate pulsed IV measurements ? 10A AM221 200µA 20mA Drain access 1A 0A 22µA 2mA Measurement Resolution Voltage Absolute Accuracy Voltage Range 0,53mV 50mV 0V 4,9mV 500mV 25V Your Calibration, Measurement & Modeling Solutions Partner! 250V Pulsed S-parameter measurements Pulsed S parameter measurements Bias Bias Your Calibration, Measurement & Modeling Solutions Partner! Pulsed S-parameter measurements The first & most important point : • Pulsed S parameter measurements must not be noisy • Small S2P measurement variation = strong influence over the linear model extraction : optimization algorithm Requirements : Dynamic range in pulsed mode > 90dB for Duty Cycle ~ 5% Your Calibration, Measurement & Modeling Solutions Partner! Pulsed S-parameter measurements Pulsed S-parameter measurements must not be noisy at low duty cycle with narrow pulse width Pulse detection methods Narrowband detection Wideband detection Receiver samples Receiver samples IF filter IF filter • No pulse desensitization • • Increased noise with narrow pulse width due to wider IF bandwidth Narrower minimum pulse width than wideband pulse • Reduced dynamic range with low duty cycle due to pulse desensitization by 20*log(duty cycle) • Limited pulse width by maximum available IF bandwidth Your Calibration, Measurement & Modeling Solutions Partner! PNA/PNA-X Noise reduction techniques and performances Peak-to-peak noise with wideband detection at 10% duty cycle Averaging 20 times in calibration and measurements No averaging in calibration and measurements Pulse width (IFBW) 0.03 dB 10 us (150 kHz) 0.04 dB 5 us (280 kHz) 0.06 dB 0.09 dB 1 us (1.5 MHz) 500 ns (3 MHz) 0.005 dB 0.006 dB 0.012 dB 0.013 dB Your Calibration, Measurement & Modeling Solutions Partner! PNA/PNA-X Noise reduction techniques and performances Dynamic range with wideband detection at 10% duty cycle with 10 us, 5 us, 1 us, 500 ns pulse width No averaging in calibration and measurements, 1% smoothing on Averaging 20 times in calibration and measurements, 1% smoothing on Your Calibration, Measurement & Modeling Solutions Partner! PNA/PNA-X Noise reduction techniques and performances Peak-to-peak noise at 10% duty cycle Wideband detection with 20 times averaging in calibration and measurements Narrowband detection with no averaging in calibration and measurements Pulse width 0.005 dB 10 us 0.009 dB 0.006 dB 5 us 0.009 dB 0.012 dB 0.013 dB 1 us 500 ns 0.012 dB 0.011 dB Your Calibration, Measurement & Modeling Solutions Partner! PNA/PNA-X Noise reduction techniques and performances Dynamic range with narrowband detection at 500 ns pulse width Hardware gating Crystal filter No Averaging, 1% smoothing on, 500 Hz IF bandwidth >100 dB at 10% >100 dB at 5% 90 dB at 1% 85 dB at 0.5% Software gating Spectral nulling Your Calibration, Measurement & Modeling Solutions Partner! VNA performance comparisons E836x Legacy PNA N524xA PNA-X N522xA New PNA Pulse generator External Internal/External Internal/External Pulse modulator External Internal/External Internal/External Max BW/Min PW 35 kHz / 50 us 15 MHz / 100 ns 15 MHz / 100 ns High level noise* 0.006 dBrms 0.002 dBrms 0.002 to 0.003 dBrms Dynamic range** 114 to 123 dB 124 to 129 dB 127 dB Min IF gate width 20 ns <20 ns <20 ns Dynamic range*** 85 dB <105 dB <105 dB Wideband detection Narrowband detection * Specified as trace noise magnitude, at 20 GHz, at 1 kHz IF bandwidth ** Specified performance at 20 GHz, at 10 Hz IF bandwidth *** Measured performance at 10 GHz at 10 Hz IF bandwidth, 1% duty cycle Your Calibration, Measurement & Modeling Solutions Partner! PNA/PNA-X internal pulse access • Internal or external master pulse (PULSE SYNC IN) • Synchronized data acquisition (P0) • Synchronized internal pulse generators (P1 – P4) with independent delay and width • Internal or external drive for modulators or receiver gates N1966A Pulse I/O adapter Search “1408-21” on www.agilent.com Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV/RF parameter measurements How to get accurate pulsed IV measurements ? Synchronisation between Pulse IV and pulse S parameters Your Calibration, Measurement & Modeling Solutions Partner! Pulsed S-parameter measurements How to get accurate pulsed IV measurements ? Synchronisation between Pulse IV and pulse S parameters Your Calibration, Measurement & Modeling Solutions Partner! Compact FET model extraction flow 1.18 1.6 y = 0.0049x + 0.6889 1.2 Rs 1 0.6 1.04 0.4 1.02 0 Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Non-linear capacitances IV Model 1.1 1.08 1.06 y = 0.0029x + 0.6375 0.8 Small-Signal y = -0.0008x + 1.1543 1.12 Idss Rs, Rd 1.16 1.14 Rd 1.4 50 100 T°C 150 200 0 50 100 T°C 150 200 Thermal model Trapping effects Dgs=f(Vgs) Dgs=f(Vgs,T) Dgd=f(Vgd) Dgd=f(Vgd,T) Ids=f(Vgs,Vds) Ids=f(Vgs,Vds,T) Ids=f(Vgs_trap,Vds,T) Cgs=f(Vgs) Cgd=f(Vgd) Rs=f(T) Rd=f(T) Various effects are successively added Your Calibration, Measurement & Modeling Solutions Partner! Thermal effects Your Calibration, Measurement & Modeling Solutions Partner! Thermal effects • Temperature dependence with ambient or chuck temperature 0.9 0.5 1.0 0.8 -40°C 0.7 0.3 0.3 0.2 0.1 Ids (A) 0.4 150°C 0.4 0.6 0.5 Ids (A) Ids (A) 25°C 0.8 0.6 0.4 0.2 0.2 0.1 -0.0 0.0 0.0 -0.2 -0.1 0 5 10 15 20 25 30 35 40 -0.1 0 45 5 10 15 20 25 30 35 40 45 Vds (V) Vds (V) 1 0 5 10 15 20 25 Vds (V) • Static and Dynamic self-heating effects 1.0 Static 0.8 2 Ids (A) 0.6 0.4 0.2 -0.0 -0.2 0 20 40 60 80 100 Vds (V) Your Calibration, Measurement & Modeling Solutions Partner! Dynamic 30 35 40 45 Thermal effects Your Calibration, Measurement & Modeling Solutions Partner! Thermal effects Thermal resistance extraction → coincidence method Ids DC, Tchuck1 = 25°C same Vgs Pulsed from (0,0), Tchuck2 = 100°C DC curve Tj1 = Tchuck1 + Rth*Pdiss1 Pulsed curve Tj2 = Tchuck2 + Rth*Pdiss2 Vds =0 At intersection point Tj1 =Tj2 => Rth = (Tchuch2 – Tchuck1)/ Pdiss1 Tchuck1 + Rth*Pdiss1 = Tchuck2 Your Calibration, Measurement & Modeling Solutions Partner! Thermal effects Thermal impedance extraction – by measurements Your Calibration, Measurement & Modeling Solutions Partner! Trapping effects Your Calibration, Measurement & Modeling Solutions Partner! Trapping effects • Charge of the capacitance = Ionized traps Charge through Rcapture, Emission through Rémission C R Rcapture Port Vin Diode C8 signal reshaping circuit diode Port Vout R Remission Diode = dissymmetry of the capture and emission process Tuning of the magnitude of the trapping effects Fundamental assumption : dissymetry of the capture and emission process Your Calibration, Measurement & Modeling Solutions Partner! Trapping effects Id (A) Id (A) Measurements to extract Gate-lag at very low dissipated power Vds(V) Response to an ideal square shaped pulsed voltage Id (A) Time (ms) Emission Time (ms) Your Calibration, Measurement & Modeling Solutions Partner! Trapping effects Id (A) Id (A) Measurements to extract Drain-lag at very low dissipated power Time (ms) Vds(V) Id (A) Capture Emission Time (ms) Your Calibration, Measurement & Modeling Solutions Partner! Trapping effects • Bias dependant gate lag -> current reduction over the entire characteristic Bias dependent drain lag -> current reduction and shifts the knee-voltage to a higher Vds Model covers knee walkout to avoid errors in calculation of output power. 0.7 H 0.6 gate-lag : Id ↘ => Pout ↘ 0.5 drain-lag : Id ↘ Vknee↗ => Pout ↘ Ids (A) (H) 0.4 0.3 0.2 0.1 0.0 -0.1 0 5 10 15 20 25 30 35 40 Vds (V) Your Calibration, Measurement & Modeling Solutions Partner! 45 50 55 60 Trapping effects • Decreasing form of the mean output current only reproduced with traps accurately modeled 4 H Ids ↘ 0.30 meas 0.25 model without traps model model with traps model 0.20 0.15 -5 0 (H) (H) (W) Pout W Pout Pout W (H) 5 10 15 20 25 30 2 1 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Pin (W) Pin( dBm) 4 3 3 0 -10 H H Pout W (H) (H) Pout W (H) Ids (A) (H) (H) (A) (H) IdsIds(A) 0.35 H Pout ↘ 2 meas model without traps model model with traps model 1 0 25 30 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Pin (W) A Drain-Lag Model for AlGaN/GaN Power HEMTs, Jardel, O. ; Charbonniaud, Microwave Symposium, 2007. IEEE/MTT-S International 2007 Your Calibration, Measurement & Modeling Solutions Partner! Compact FET model extraction flow 1.18 1.6 y = 0.0049x + 0.6889 1.2 Rs 1 0.6 1.04 0.4 1.02 0 Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Non-linear capacitances IV Model 1.1 1.08 1.06 y = 0.0029x + 0.6375 0.8 Small-Signal y = -0.0008x + 1.1543 1.12 Idss Rs, Rd 1.16 1.14 Rd 1.4 50 100 T°C 150 200 0 50 100 T°C 150 200 Thermal model Trapping effects Dgs=f(Vgs) Dgs=f(Vgs,T) Dgd=f(Vgd) Dgd=f(Vgd,T) Ids=f(Vgs,Vds) Ids=f(Vgs,Vds,T) Ids=f(Vgs_trap,Vds,T) Cgs=f(Vgs) Cgd=f(Vgd) Rs=f(T) Rd=f(T) Various effects are successively added Your Calibration, Measurement & Modeling Solutions Partner! Your Calibration, Measurement & Modeling Solutions Partner!