SI4816BDY-T1-E3

Si4816BDY
Vishay Siliconix
Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode
FEATURES
PRODUCT SUMMARY
VDS (V)
Channel-1
30
Channel-2
RDS(on) (Ω)
ID (A)
0.0185 at VGS = 10 V
6.8
0.0225 at VGS = 4.5 V
6.0
0.0115 at VGS = 10 V
11.4
0.016 at VGS = 4.5 V
9.5
• Halogen-free According to IEC 61249-2-21
Available
• LITTLE FOOT® Plus Power MOSFET
• 100 % Rg Tested
Qg (Typ.)
7.8
11.6
SCHOTTKY PRODUCT SUMMARY
VDS (V)
VSD (V)
Diode Forward Voltage
IF (A)
30
0.50 V at 1.0 A
2.0
D1
SO-8
G1
G1
1
8
D1
A/S2
2
7
D2/S1
A/S2
3
6
D2/S1
G2
4
5
D2/S1
N-Channel 1
MOSFET
S1/D2
Schottky Diode
G2
Top View
N-Channel 2
MOSFET
Ordering Information: Si4816BDY-T1-E3 (Lead (Pb)-free)
Si4816BDY-T1-GE3 (Lead (Pb)-free and Halogen-free)
S2
A
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Channel-1
Parameter
Symbol
10 s
Channel-2
Steady State
Drain-Source Voltage
VDS
30
Gate-Source Voltage
VGS
20
Continuous Drain Current (TJ = 150 °C)a
TA = 25 °C
TA = 70 °C
ID
a
Continuous Source Current (Diode Conduction)
IS
Single Pulse Avalanche Current
IAS
Avalanche Energy
Maximum Power Dissipationa
6.8
5.8
11.4
4.6
9.0
L = 0.1 mH
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
30
1
PD
0.9
6.5
2.2
A
1.15
20
5
20
mJ
1.4
1.0
2.4
1.25
0.9
0.64
1.5
0.8
TJ, Tstg
Unit
8.2
40
10
EAS
Steady State
V
5.5
IDM
Pulsed Drain Current
10 s
- 55 to 150
W
°C
THERMAL RESISTANCE RATINGS
Channel-1
Parameter
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
Symbol
t ≤ 10 s
Steady State
Steady State
RthJA
RthJF
Channel-2
Schottky
Typ.
Max.
Typ.
Max.
Typ.
Max.
72
90
43
53
48
60
100
125
82
100
80
100
51
63
25
30
28
35
Unit
°C/W
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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Si4816BDY
Vishay Siliconix
MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.a
Max.
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
VGS(th)
VDS = VGS, ID = 250 µA
IGSS
VDS = 0 V, VGS = 20 V
VDS = 30 V, VGS = 0 V
Zero Gate Voltage Drain Current
IDSS
VDS = 30 V, VGS = 0 V, TJ = 85 °C
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
Diode Forward Voltageb
ID(on)
RDS(on)
gfs
VSD
Ch-1
1.0
3.0
Ch-2
1.0
3.0
Ch-1
100
Ch-2
100
Ch-1
1
Ch-2
100
Ch-1
15
Ch-2
V
nA
µA
2000
VDS = 5 V, VGS = 10 V
Ch-1
20
Ch-2
30
VGS = 10 V, ID = 6.8 A
Ch-1
A
0.0155
0.0185
VGS = 10 V, ID = 11.4 A
Ch-2
0.0093
0.0115
VGS = 4.5 V, ID = 6.0 A
Ch-1
0.0185
0.0225
VGS = 4.5 V, ID = 9.5 A
Ch-2
0.013
0.016
VDS = 15 V, ID = 6.8 A
Ch-1
30
VDS = 15 V, ID = 11.4 A
Ch-2
31
IS = 1 A, VGS = 0 V
Ch-1
0.73
1.1
IS = 1 A, VGS = 0 V
Ch-2
0.47
0.5
Ch-1
7.8
10
Ch-2
11.6
18
Ch-1
2.9
Ch-2
4.8
Ch-1
2.3
Ω
S
V
Dynamica
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Qg
Channel-1
VDS = 15 V, VGS = 5 V, ID = 6.8 A
Qgs
Qgd
Channel-2
VDS = 15 V, VGS = 5 V, ID = - 11.4 A
Ch-2
Rg
td(on)
tr
td(off)
tf
3.7
Ch-1
1.5
3.0
4.5
Ch-2
0.9
1.8
2.7
Ch-1
11
17
Ch-2
13
20
Ch-1
9
15
Ch-2
9
15
Ch-1
24
40
Ch-2
31
50
Ch-1
9
15
Ch-2
11
17
IF = 1.3 A, dI/dt = 100 A/µs
Ch-1
20
35
IF = 2.2 A, dI/dt = 100 µA/µs
Ch-2
25
40
Channel-1
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
Channel-2
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
trr
nC
Ω
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
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Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Si4816BDY
Vishay Siliconix
SCHOTTKY SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Forward Voltage Drop
VF
Maximum Reverse Leakage Current
Irm
Test Conditions
Typ.
Max.
IF = 1.0 A
0.47
0.50
IF = 1.0 A, TJ = 125 °C
0.36
0.42
VR = 30 V
0.004
0.100
VR = 30 V, TJ = 100 °C
0.7
10
VR = - 30 V, TJ = 125 °C
3.0
20
VR = 10 V
50
CT
Junction Capacitance
Min.
Unit
V
mA
pF
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40
40
VGS = 10 thru 4 V
35
30
I D – Drain Current (A)
I D – Drain Current (A)
35
25
20
15
10
30
25
20
15
TC = 125 °C
10
3V
25 °C
5
5
2V
- 55 °C
0
0.0
0
0
1
2
3
4
5
0.5
1.0
2.0
2.5
3.0
3.5
4.0
4.5
VGS – Gate-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
1200
0.05
1000
0.04
C – Capacitance (pF)
RDS(on) – On-Resistance (Ω)
1.5
0.03
VGS = 4.5 V
0.02
Ciss
800
600
400
VGS = 10 V
Coss
0.01
200
0.00
Crss
0
0
5
10
15
20
25
30
35
ID – Drain Current (A)
On-Resistance vs. Drain Current
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
40
0
5
10
15
20
25
30
VDS – Drain-to-Source Voltage (V)
Capacitance
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Si4816BDY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1.6
VGS = 10 V
ID = 6.8 A
VDS = 15 V
ID = 6.8 A
5
4
3
2
(Normalized)
1.4
R DS(on) – On-Resistance
V GS – Gate-to-Source Voltage (V)
6
1.2
1.0
0.8
1
0.6
- 50
0
0
2
4
6
8
10
- 25
0
Gate Charge
RDS(on) – On-Resistance (Ω)
I S – Source Current (A)
75
100
125
150
0.05
TJ = 150 °C
10
TJ = 25 °C
0.04
0.03
ID = 6.8 A
0.02
0.01
0.00
0.2
0.4
0.6
0.8
1.0
1.2
0
1.4
2
4
6
8
10
VGS – Gate-to-Source Voltage (V)
VSD – Source-to-Drain Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
0.4
100
0.2
80
ID = 250 µA
0.0
Power (W)
V GS(th) Variance (V)
50
On-Resistance vs. Junction Temperature
40
1
0.0
25
TJ – Junction Temperature (°C)
Qg – Total Gate Charge (nC)
- 0.2
60
40
- 0.4
20
- 0.6
- 0.8
- 50
0
- 25
0
25
50
75
TJ – Temperature (°C)
Threshold Voltage
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100
125
150
0.001
0.01
0.1
1
10
Time (s)
Single Pulse Power, Junction-to-Ambient
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Si4816BDY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
100
Limited by RDS(on)*
IDM Limited
I D – Drain Current (A)
10
1 ms
1
10 ms
ID(on)
Limited
100 ms
0.1
TC = 25 °C
Single Pulse
BVDSS Limited
0.01
0.1
1s
10 s
DC
1
10
100
VDS – Drain-to-Source Voltage (V)
* VGS > minimum V GS at which R DS(on) is specified
Safe Operating Area
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 100 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10- 3
10- 4
10- 2
10- 1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10- 4
10- 3
10- 2
10- 1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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Si4816BDY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40
40
VGS = 10 thru 5 V
32
4V
I D – Drain Current (A)
I D – Drain Current (A)
32
24
16
24
16
TC = 125 °C
8
8
25 °C
3V
- 55 °C
2V
0
0.0
0
1
2
3
4
5
0.5
1.0
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.020
2000
0.016
1600
VGS = 4.5 V
0.012
VGS = 10 V
0.008
4.0
4.5
Ciss
1200
800
Coss
400
0.004
Crss
0
0.000
0
5
10
15
20
25
0
30
6
12
18
24
30
VDS – Drain-to-Source Voltage (V)
ID – Drain Current (A)
On-Resistance vs. Drain Current
Capacitance
6
1.6
VDS = 15 V
ID = 9.5 A
1.4
4
3
2
(Normalized)
5
R DS(on) – On-Resistance
V GS – Gate-to-Source Voltage (V)
1.5
VDS – Drain-to-Source Voltage (V)
C – Capacitance (pF)
RDS(on) – On-Resistance (Ω)
0
VGS = 10 V
ID = 9.5 A
1.2
1.0
0.8
1
0
0
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6
3
6
9
12
15
0.6
- 50
- 25
0
25
50
75
100
125
Qg – Total Gate Charge (nC)
TJ – Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
150
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Si4816BDY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.05
R DS(on) – On-Resistance (Ω)
I S – Source Current (A)
40
TJ = 150 °C
10
TJ = 25 °C
1
0.0
0.04
0.03
0.02
ID = 9.5 A
0.01
0.00
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
2
VSD – Source-to-Drain Voltage (V)
6
8
10
VGS – Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
10
100
1
80
VDS = 30 V
0.1
Power (W)
IR – Reverse Current (mA)
4
VDS = 24 V
0.01
60
40
0.001
20
0.0001
0.00001
0
0
25
50
75
100
125
150
0.001
0.01
TJ – Temperature (°C)
0.1
1
10
Time (s)
Reverse Current vs. Junction Temperature
Single Pulse Power, Junction-to-Ambient
100
Limited by RDS(on)*
IDM Limited
I D – Drain Current (A)
10
1 ms
1
ID(on)
Limited
10 ms
100 ms
0.1
1s
TC = 25 °C
Single Pulse
10 s
DC
BVDSS Limited
0.01
0.1
1
10
100
VDS – Drain-to-Source Voltage (V)
* VGS > minimum V GS at which R DS(on) is specified
Safe Operating Area
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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Si4816BDY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
t1
0.05
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 82 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
4. Surface Mounted
Single Pulse
0.01
10- 4
10- 3
10- 2
10- 1
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10- 4
10- 3
10- 2
10- 1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
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Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Si4816BDY
Vishay Siliconix
SCHOTTKY TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
20
10
TJ = 150 °C
I F − Forward Current (A)
I R – Reverse Current (mA)
10
1
30 V
0.1
24 V
0.01
TJ = 25 °C
0.001
0.0001
0
25
50
75
100
125
1
0.0
150
0.3
0.6
0.9
1.2
TJ – Temperature (°C)
VF − Forward Voltage Drop (V)
Reverse Current vs. Junction Temperature
Forward Voltage Drop
1.5
200
C – Capacitance (pF)
160
120
80
Coss
40
0
0
6
12
18
24
30
VDS – Drain-to-Source Voltage (V)
Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73026.
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72606
Revision: 21-Jan-08
Legal Disclaimer Notice
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
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Document Number: 91000