SQ4470EY-T1-GE3

SQ4470EY
www.vishay.com
Vishay Siliconix
Automotive N-Channel 60 V (D-S) 175 °C MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• TrenchFET® Power MOSFET
60
RDS(on) () at VGS = 10 V
0.012
RDS(on) () at VGS = 6 V
0.014
ID (A)
• AEC-Q101 Qualifiedc
• 100 % Rg and UIS Tested
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
16
Configuration
Single
D
SO-8
S
1
8
D
S
2
7
D
S
3
6
D
G
4
5
D
G
S
Top View
N-Channel MOSFET
ORDERING INFORMATION
Package
SO-8
Lead (Pb)-free and Halogen-free
SQ4470EY-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
TC = 25 °C
TC = 125 °C
Continuous Source Current (Diode Conduction)
Pulsed Drain Currenta
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipationa
L = 0.1 mH
TC = 25 °C
TC = 125 °C
Operating Junction and Storage Temperature Range
ID
V
16
9
IS
6
IDM
67
IAS
50
EAS
125
PD
UNIT
7.1
2.3
A
mJ
W
TJ, Tstg
- 55 to + 175
°C
SYMBOL
LIMIT
UNIT
RthJA
80
RthJF
21
THERMAL RESISTANCE RATINGS
PARAMETER
Junction-to-Ambient
Junction-to-Foot (Drain)
PCB
Mountb
°C/W
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. When mounted on 1" square PCB (FR-4 material).
c. Parametric verification ongoing.
S12-1845-Rev. C, 30-Jul-12
Document Number: 65673
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ4470EY
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS
VGS = 0, ID = 250 μA
60
-
-
VGS(th)
VDS = VGS, ID = 250 μA
2.5
3.0
3.5
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 20 V
-
-
± 100
VGS = 0 V
VDS = 60 V
-
-
1.0
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V
VDS = 60 V, TJ = 125 °C
-
-
50
VGS = 0 V
VDS = 60 V, TJ = 175 °C
-
-
250
On-State Drain Currenta
ID(on)
VGS = 10 V
VDS5 V
30
-
-
VGS = 10 V
ID = 6 A
-
0.010
0.012
VGS = 10 V
ID = 6 A, TJ = 125 °C
-
-
0.021
VGS = 10 V
ID = 6 A, TJ = 175 °C
-
-
0.025
VGS = 6 V
ID = 5 A
-
0.012
0.014
-
25
-
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
Forward Transconductanceb
RDS(on)
gfs
VDS = 15 V, ID = 6 A
V
nA
μA
A

S
Dynamicb
-
2531
3165
-
382
480
Crss
-
153
195
Qg
-
45
68
-
9.9
-
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Qgs
Gate-Drain
Chargec
Gate Resistance
Turn-On Delay
Timec
Rise Timec
Turn-Off Delay Timec
Fall Timec
VGS = 0 V
VDS = 25 V, f = 1 MHz
VGS = 10 V
VDS = 30 V, ID = 12 A
Qgd
pF
nC
-
11.2
-
f = 1 MHz
0.40
0.87
1.30
td(on)
-
13
20
tr
VDD = 30 V, RL = 2.5 
ID  12 A, VGEN = 10 V, Rg = 1 
-
12
18
-
25
38
-
9
14
-
-
67
A
-
0.72
1.2
V
Rg
td(off)
tf

ns
Source-Drain Diode Ratings and Characteristicsb
Pulsed Currenta
ISM
Forward Voltage
VSD
IF = 1.7 A, VGS = 0
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.




Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S12-1845-Rev. C, 30-Jul-12
Document Number: 65673
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ4470EY
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
50
50
VGS = 10 V thru 6 V
40
ID - Drain Current (A)
ID - Drain Current (A)
40
30
VGS = 5 V
20
30
TC = 25 °C
20
10
10
TC = - 55 °C
TC = 125 °C
VGS = 4 V
0
0
0
2
4
6
8
VDS - Drain-to-Source Voltage (V)
0
10
2
4
6
8
VGS - Gate-to-Source Voltage (V)
10
Transfer Characteristics
Output Characteristics
10
80
8
64
gfs - Transconductance (S)
ID - Drain Current (A)
TC = - 55 °C
6
TC = 25 °C
4
TC = 25 °C
48
TC = 125 °C
32
16
2
TC = 125 °C
TC = - 55 °C
0
0
0
2
4
6
8
VGS - Gate-to-Source Voltage (V)
0
10
6
Transfer Characteristics
18
24
30
Transconductance
0.050
3500
3000
Ciss
C - Capacitance (pF)
0.040
RDS(on) - On-Resistance (Ω)
12
ID - Drain Current (A)
0.030
0.020
VGS = 6 V
2500
2000
1500
C oss
1000
0.010
Crss
500
VGS = 10 V
0.000
0
0
10
20
30
40
ID - Drain Current (A)
On-Resistance vs. Drain Current
S12-1845-Rev. C, 30-Jul-12
50
0
5
10
15
20
25
VDS - Drain-to-Source Voltage (V)
30
Capacitance
Document Number: 65673
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ4470EY
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
2.1
RDS(on) - On-Resistance (Normalized)
VGS - Gate-to-Source Voltage (V)
10
ID = 12 A
VDS = 30 V
8
6
4
2
ID = 5 A
1.8
1.5
VGS = 10 V
1.2
0.9
0
0
10
20
30
40
Qg - Total Gate Charge (nC)
0.6
- 50 - 25
50
100
0.04
RDS(on) - On-Resistance (Ω)
IS - Source Current (A)
175
0.05
10
TJ = 150 °C
1
0.1
TJ = 25 °C
0.03
TJ = 150 °C
0.02
0.01
0.01
TJ = 25 °C
0.00
0
0.2
0.4
0.6
0.8
1.0
VSD - Source-to-Drain Voltage (V)
4
6
8
VGS - Gate-to-Source Voltage (V)
10
On-Resistance vs. Gate-to-Source Voltage
80
VDS - Drain-to-Source Voltage (V)
0.5
0.1
- 0.3
ID = 5 mA
- 0.7
ID = 250 μA
- 1.1
- 1.5
- 50 - 25
2
1.2
Source Drain Diode Forward Voltage
VGS(th) Variance (V)
150
On-Resistance vs. Junction Temperature
Gate Charge
0.001
0.0
0
25
50
75 100 125
T - Junction Temperature (°C)
77
ID = 1 mA
74
71
68
65
0
25
50
75
100
TJ - Temperature (°C)
Threshold Voltage
S12-1845-Rev. C, 30-Jul-12
125
150
175
- 50 - 25
0
25
50
75 100 125
TJ - Junction Temperature (°C)
150
175
Drain Source Breakdown vs. Junction Temperature
Document Number: 65673
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ4470EY
www.vishay.com
Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
100
IDM Limited
100 μs
ID - Drain Current (A)
10
1 ms
10 ms
1
Limited by RDS(on)*
0.1
0.01
0.01
TC = 25 °C
Single Pulse
100 ms
BVDSS Limited
1s
10 s, DC
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Square Wave Pulse Duration (s)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
S12-1845-Rev. C, 30-Jul-12
Document Number: 65673
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ4470EY
www.vishay.com
Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Foot (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65673.
S12-1845-Rev. C, 30-Jul-12
Document Number: 65673
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Ordering Information
www.vishay.com
Vishay Siliconix
SO-8
Ordering codes for the SQ rugged series power MOSFETs in the SO-8 package:
DATASHEET PART NUMBER
OLD ORDERING CODE a
NEW ORDERING CODE
SQ4182EY
SQ4182EY-T1-GE3
SQ4182EY-T1_GE3
SQ4184EY
SQ4184EY-T1-GE3
SQ4184EY-T1_GE3
SQ4282EY
SQ4282EY-T1-GE3
SQ4282EY-T1_GE3
SQ4284EY
SQ4284EY-T1-GE3
SQ4284EY-T1_GE3
SQ4401EY
SQ4401EY-T1-GE3
SQ4401EY-T1_GE3
SQ4410EY
SQ4410EY-T1-GE3
SQ4410EY-T1_GE3
SQ4425EY
SQ4425EY-T1-GE3
SQ4425EY-T1_GE3
SQ4431EY
SQ4431EY-T1-GE3
SQ4431EY-T1_GE3
SQ4435EY
SQ4435EY-T1-GE3
SQ4435EY-T1_GE3
SQ4470EY
SQ4470EY-T1-GE3
SQ4470EY-T1_GE3
SQ4483BEEY
SQ4483BEEY-T1-GE3
SQ4483BEEY-T1_GE3
SQ4483EY
-
SQ4483EY-T1_GE3
SQ4532AEY
-
SQ4532AEY-T1_GE3
SQ4840EY
SQ4840EY-T1-GE3
SQ4840EY-T1_GE3
SQ4850EY
SQ4850EY-T1-GE3
SQ4850EY-T1_GE3
SQ4917EY
SQ4917EY-T1-GE3
SQ4917EY-T1_GE3
SQ4920EY
SQ4920EY-T1-GE3
SQ4920EY-T1_GE3
SQ4937EY
SQ4937EY-T1-GE3
SQ4937EY-T1_GE3
SQ4940AEY
SQ4940AEY-T1-GE3
SQ4940AEY-T1_GE3
SQ4946AEY
SQ4946AEY-T1-GE3
SQ4946AEY-T1_GE3
SQ4949EY
SQ4949EY-T1-GE3
SQ4949EY-T1_GE3
SQ4961EY
SQ4961EY-T1-GE3
SQ4961EY-T1_GE3
SQ9407EY
SQ9407EY-T1-GE3
SQ9407EY-T1_GE3
SQ9945BEY
SQ9945BEY-T1-GE3
SQ9945BEY-T1_GE3
Note
a. Old ordering code is obsolete and no longer valid for new orders
Revision: 25-Aug-15
Document Number: 66624
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
PAD Pattern
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Vishay Siliconix
Recommended Land Pattern PowerPAK® MLP66-40L
2.200
0.100 0.100
0.200 0.276
0.025
0.025
0.100
1
1
40
40
0.100
0.100
0.310
0.320
0.100
1.700
2.600
0.100 0.100
0.600
0.276
2.200
0.100
4.600
0.100
All Dimensions are in milimeters
Revision: 28-Feb-14
Document Number: 67964
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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1
APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
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Document Number: 91000