DATASHEET 31/2 Digit, LCD/LED Display, A/D Converters ICL7106, ICL7107, ICL7107S Features The Intersil ICL7106 and ICL7107 are high performance, low power, 31/2 digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED) display. • Guaranteed zero reading for 0V input on all scales The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features auto zero to less than 10µV, zero drift of less than 1µV/°C, input bias current of 10pA (max) and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. • True polarity at zero for precise null detection • 1pA typical input current • True differential input and reference, direct display drive - LCD ICL7106, LED lCL7107 • Low noise - less than 15µVP-P • On-chip clock and reference • Low power dissipation - typically less than 10mW • No additional active circuits required • Enhanced display stability • Pb-free (RoHS compliant) Ordering Information PART NUMBER (Note 2) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ICL7106CPLZ ICL7106CPLZ 0 to 70 40 Ld PDIP (Note 3) E40.6 ICL7106CM44Z (Note 4) ICL7106 CM44Z 0 to 70 44 Ld MQFP Q44.10x10 ICL7106CM44ZT (Notes 4, 5) ICL7106 CM44Z 0 to 70 44 Ld MQFP Tape and Reel Q44.10x10 ICL7107CPLZ ICL7107CPLZ 0 to 70 40 Ld PDIP (Note 3) E40.6 ICL7107SCPLZ ICL7107SCPLZ 0 to 70 40 Ld PDIP (Notes 1, 3) E40.6 ICL7107CM44Z (Note 4) ICL7107 CM44Z 0 to 70 44 Ld MQFP Q44.10x10 ICL7107CM44ZT (Notes 4, 5) ICL7107 CM44Z 0 to 70 44 Ld MQFP Tape and Reel Q44.10x10 NOTES: 1. “S” indicates enhanced stability. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 4. For Moisture Sensitivity Level (MSL), please see product information page for ICL7106, ICL7107, ICL7107S. For more information on MSL, please see tech brief TB363. 5. Please refer to TB347 for details on reel specifications. October 24, 2014 FN3082.9 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2004, 2005, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ICL7106, ICL7107, ICL7107S Pin Configurations (1’s) (10’s) 6 35 REF LO G1 7 34 CREF+ E1 8 D2 9 33 CREF32 COMMON C2 10 B2 44 43 42 41 40 39 38 37 36 35 34 33 2 32 NC TEST 3 31 C3 OSC 3 4 30 A3 NC 5 29 G3 OSC 2 6 28 BP/GND OSC 1 7 27 POL 27 INT V+ 8 26 AB4 26 V- D1 9 25 E3 25 G2 (10’s) C1 10 24 F3 24 C3 B1 11 23 12 13 14 15 16 17 18 19 20 21 22 B3 31 IN HI 30 IN LO 11 A2 12 29 A-Z F2 13 28 BUFF D3 B3 F3 14 15 16 17 E3 18 23 A3 19 22 G3 POL 20 21 BP/GND Submit Document Feedback 2 NC NC 1 G2 (100’s) (1000) AB4 (MINUS) V- 36 REF HI F1 INT 5 BUFF 37 TEST A1 A-Z 4 IN LO 38 OSC 3 B1 IN HI 3 COMMON 39 OSC 2 C1 CREF+ 40 OSC 1 2 CREF- 1 REF LO V+ D1 E2 (100’s) ICL7106, ICL7107 (MQFP) TOP VIEW REF HI ICL7106, ICL7107, ICL7107S (PDIP) TOP VIEW A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Absolute Maximum Ratings Thermal Information Supply Voltage ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V ICL7107, V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V ICL7107, V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V Analog Input Voltage (Either Input) (Note 6) . . . . . . . . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input). . . . . . . . . . . . . . . . . . . . . . . . V+ to VClock Input ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+ Thermal Resistance (Typical) JA (oC/W) 50 PDIP Package (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . MQFP Package (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile (MQFP Package only) . . . . . . . . . . . . . . . see TB493 NOTE: Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 7. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Note 8) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Zero Input Reading VIN = 0.0V, full scale = 200mV -000.0 000.0 +000.0 Digital Reading Stability (Last Digit) (ICL7107S Only) Fixed input voltage (Note 11) -000.0 000.0 +000.0 Digital Reading Ratiometric Reading VlN = VREF, VREF = 100mV Rollover Error -VIN = +VlN 200mV Difference in reading for equal positive and negative inputs near full scale - ±0.2 ±1 Counts Linearity Full scale = 200mV or full scale = 2V maximum deviation from best straight line fit (Note 10) - ±0.2 ±1 Counts Common Mode Rejection Ratio VCM = 1V, VIN = 0V, full scale = 200mV (Note 10) - 50 - µV/V Noise VIN = 0V, full scale = 200mV (peak-to-peak value not exceeded 95% of time) - 15 - µV Leakage Current Input VlN = 0 (Note 10) - 1 10 pA Zero Reading Drift VlN = 0, 0°C to +70°C (Note 10) - 0.2 1 µV/°C Scale Factor Temperature Coefficient VIN = 199mV, 0°C to +70°C, (ext. ref. 0ppm/×°C) (Note 10) - 1 5 ppm/°C End Power Supply Character V+ Supply Current VIN = 0 (does not include LED current for ICL7107) - 1.0 1.8 mA End Power Supply Character V- Supply Current ICL7107 Only - 0.6 1.8 mA COMMON Pin Analog Common Voltage 25kΩ between common and positive supply (with respect to + supply) 2.4 3.0 3.2 V Temperature Coefficient of Analog Common 25kΩ between common and positive supply (with respect to + supply) - 80 - ppm/°C V+ = to V- = 9V (Note 9) 4 5.5 6 V 999 999/1000 1000 Digital Reading DISPLAY DRIVER ICL7106 ONLY Peak-to-Peak Segment Drive Voltage Peak-to-Peak Backplane Drive Voltage Submit Document Feedback 3 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Electrical Specifications (Note 8) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Except Pins AB4 and POL 5 8 - mA Pin AB4 Only 10 16 - mA Pin POL Only 4 7 - mA DISPLAY DRIVER ICL7107 ONLY Segment Sinking Current V+ = 5V, segment voltage = 3V NOTES: 8. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at TA = +25°C, fCLOCK = 48kHz. ICL7106 is tested in the circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2. 9. Back plane drive is in phase with segment drive for “off” segment, 180 degrees out of phase for “on” segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 10. Limit is not production tested. The maximum was established via characterization and/or design simulations. 11. Sample tested. Typical Applications and Test Circuits IN A3 23 G3 22 BP 21 19 AB4 20 POL C3 24 18 E3 17 F3 V- 26 G2 25 16 B3 INT 27 DISPLAY 15 D3 14 E2 A-Z 29 BUFF 28 C3 13 F2 IN HI 31 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 TEST 37 C5 C1 R4 REF HI 36 OSC 3 38 OSC 2 39 OSC 1 40 C4 + R5 R1 R3 9V - - + B1 A1 F1 G1 E1 D2 4 5 6 7 8 9 12 A2 C1 3 11 B2 D1 2 10 C2 V+ 1 ICL7106 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ DISPLAY FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE + +5V IN INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 GND 21 14 E2 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL DISPLAY BUFF 28 A-Z 29 C3 13 F2 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 IN HI 31 C5 C1 R4 REF HI 36 TEST 37 OSC 3 38 OSC 2 39 OSC 1 40 C4 -5V R5 R1 R3 - B1 A1 F1 G1 E1 D2 4 5 6 7 8 9 12 A2 C1 3 11 B2 D1 2 10 C2 V+ 1 ICL7107 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ DISPLAY FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE Submit Document Feedback 4 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Design Information Summary Sheet • DISPLAY COUNT • OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 48kHz V IN COUNT = 1000 --------------V REF • CONVERSION CYCLE • OSCILLATOR PERIOD tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48kHz; tCYC = 333ms tOSC = RC/0.45 • INTEGRATION CLOCK FREQUENCY • COMMON MODE INPUT VOLTAGE fCLOCK = fOSC/4 (V- + 1V) < VlN < (V+ - 0.5V) • INTEGRATION PERIOD • AUTO-ZERO CAPACITOR tINT = 1000 x (4/fOSC) 0.01µF < CAZ < 1µF • 60/50Hz REJECTION CRITERION • REFERENCE CAPACITOR tINT/t60Hz or tlNT/t60Hz = Integer 0.1µF < CREF < 1µF • OPTIMUM INTEGRATION CURRENT • VCOM IINT = 4µA Biased between Vi and V-. • FULL SCALE ANALOG INPUT VOLTAGE • VCOM V+ - 2.8V VlNFS (Typ) = 200mV or 2V Regulation lost when V+ to V- < 6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. • INTEGRATE RESISTOR V INFS R INT = ----------------I INT • ICL7106 POWER SUPPLY: SINGLE 9V • INTEGRATE CAPACITOR V+ - V- = 9V Digital supply is generated internally VGND V+ - 4.5V t INT I INT C INT = -------------------------------V INT • INTEGRATOR OUTPUT VOLTAGE SWING • ICL7106 DISPLAY: LCD t INT I INT V INT = -------------------------------C INT Type: Direct drive with digital logic supply amplitude. • ICL7107 POWER SUPPLY: DUAL ±5.0V • VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND • ICL7107 DISPLAY: LED Type: Nonmultiplexed Common Anode Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DEINTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC Submit Document Feedback 5 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Detailed Description to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: Analog Section Figure 3 shows the analog section for the ICL7106 and ICL7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) deintegrate (DE). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. Deintegrate Phase The final phase is deintegrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output STRAY REF HI 34 36 V+ REF LO 35 A-Z Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to deintegrate a positive signal but lose charge (decrease voltage) when called up to deintegrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (see “Component Value Selection” on page 10.) RINT DE+ CINT A-Z 29 INT INTEGRATOR - - 31 DE- 1 28 + + INT CAZ BUFFER V+ 33 10A IN HI The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. CREF - A-Z 6.2V DE+ 32 30 INT DE- - + TO DIGITAL SECTION A-Z A-Z COMMON 27 2.8V INPUT HIGH N (EQ. 1) Differential Input STRAY CREF CREF+ V IN DISPLAY COUNT = 1000 --------------- V REF COMPARATOR - + INPUT LOW A-Z AND DE(±) IN LO V- FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107 Submit Document Feedback 6 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Analog COMMON V+ This pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (15Ω), and a temperature coefficient typically less than 80ppm/×°C. V REF HI Analog COMMON is also used as the input low return during auto-zero and deintegrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. IZ ICL7106 ICL7107 V- FIGURE 4A. The limitations of the on chip reference should also be recognized, however. With the ICL7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25µV to 80µVP-P. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between overrange and a non-overrange count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. The ICL7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. 6.8V ZENER REF LO V+ V 6.8kΩ 20kΩ ICL7106 ICL7107 ICL8069 1.2V REFERENCE REF HI REF LO COMMON FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. On the ICL7106 it is coupled to the internally generated digital supply through a 500Ω resistor. Thus, it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied. V+ 1MΩ TO LCD DECIMAL POINT ICL7106 BP TEST 21 37 TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “1888”. The TEST pin will sink about 15mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave). This may burn the LCD display if maintained for extended periods. Submit Document Feedback 7 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Digital Section V+ Figures 7 and 8 show the digital section for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relatively large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. V+ BP ICL7106 TO LCD DECIMAL POINTS DECIMAL POINT SELECT TEST CD4030 GND FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE Figure 8 is the Digital Section of the ICL7107. It is identical to the ICL7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. a a f a g b e c a f b b f g c e d b g c d e c d BACKPLANE 21 LCD PHASE DRIVER 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 7 SEGMENT DECODE 7 SEGMENT DECODE 200 0.5mA LATCH SEGMENT OUTPUT 2mA 1000’s COUNTER INTERNAL DIGITAL GROUND 100’s COUNTER 10’s COUNTER 1’s COUNTER TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 1 V+ CLOCK 4 † LOGIC CONTROL 6.2V 500Ω † THREE INVERTERS INTERNAL DIGITAL GROUND ONE INVERTER SHOWN FOR CLARITY VTH = 1V 37 26 40 OSC 1 39 OSC 2 38 TEST V- OSC 3 FIGURE 7. ICL7106 DIGITAL SECTION Submit Document Feedback 8 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S a a a f g b f b e g c c a f b e d e c d 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ b g c d 7 SEGMENT DECODE 7 SEGMENT DECODE LATCH 0.5mA TO SEGMENT 1000’s COUNTER 100’s COUNTER 10’s COUNTER 1’s COUNTER 8mA TO SWITCH DRIVERS FROM COMPARATOR OUTPUT DIGITAL GROUND V+ 1 V+ CLOCK 4 † LOGIC CONTROL 37 † THREE INVERTERS 27 ONE INVERTER SHOWN FOR CLARITY 40 OSC 1 39 OSC 2 TEST 500Ω DIGITAL GROUND 38 OSC 3 FIGURE 8. ICL7107 DIGITAL SECTION System Timing INTERNAL TO PART Figure 9 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used: 4 CLOCK 4 CLOCK 1. Figure 9A. An external oscillator connected to pin 40. 2. Figure 9B. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference deintegrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc., should be selected. For 50Hz rejection, oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc., would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). 40 39 38 GND ICL7107 TEST ICL7106 FIGURE 9A. INTERNAL TO PART 40 39 38 R C RC OSCILLATOR FIGURE 9B. FIGURE 9. CLOCK CIRCUITS Submit Document Feedback 9 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Component Value Selection Reference Voltage Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100µA of quiescent current. They can supply 4µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470kΩ is near optimum and similarly a 47kΩ for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the ICL7106 or the ICL7107, when the analog COMMON is used as a reference, a nominal +2V full scale integrator swing is fine. For the ICL7107 with +5V supplies and analog COMMON tied to supply ground, a ±3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.22µF and 0.10µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47µF capacitor is recommended. On the 2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. The analog input required to generate full scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 120kΩ and 0.22µF. This makes the system slightly quieter and also avoids a divider network on the input. The ICL7107 with ±5V supplies can accept input signals up to ±4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. ICL7107 Power Supplies The ICL7107 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lC. Figure 10 shows this application. See the ICL7660 datasheet for an alternative. In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than ±1.5V. 3. An external reference is used. V+ Reference Capacitor CD4009 A 0.1µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent rollover error. Generally 1µF will hold the rollover error to 0.5 count in this instance. Oscillator Components 1N914 OSC 2 (EQ. 2) + 10µF OSC 3 0.047 µF ICL7107 For all ranges of frequency a 100kΩ resistor is recommended and the capacitor is selected as shown in Equation 2: 0.45 f = ----------- For 48kHz Clock (3 Readings/sec), RC V+ OSC 1 - 1N914 GND V- V- = 3.3V C = 100pF. FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V Submit Document Feedback 10 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Typical Applications Application Notes The ICL7106 and ICL7107 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Intersil Corporation. NOTE # DESCRIPTION AN016 “Selecting A/D Converters” AN017 “The Integrating A/D Converter” AN018 “Do’s and Don’ts of Applying A/D Converters” AN023 “Low Cost Digital Panel Meter Designs” AN046 “Building a Battery-Operated Auto Ranging DVM with the ICL7106” AN052 “Tips for Using Single Chip 31/2 Digit A/D Converters” AN9609 “Overcoming Common Mode Range Issues When Using Intersil Integrating Converters” Typical Applications TO PIN 1 OSC 1 40 OSC 2 39 100kΩ OSC 2 39 OSC 3 38 TEST 37 TO PIN 1 OSC 1 40 OSC 3 38 SET VREF = 100mV 100pF TEST 37 REF HI 36 REF HI 36 REF LO 35 REF LO 35 CREF 34 CREF 33 1kΩ IN A-Z 29 - 47kΩ + 9V - INT 27 0.22µF G2 25 C3 24 A3 23 +5V 1kΩ A-Z 29 BUFF 28 22kΩ 0.1µF 1MΩ IN HI 31 IN LO 30 SET VREF = 100mV 100pF COMMON 32 + 0.01µF 0.47µF BUFF 28 V - 26 CREF 34 CREF 33 1MΩ IN HI 31 IN LO 30 22kΩ 0.1µF COMMON 32 100kΩ + IN 0.01µF 0.47µF - 47kΩ INT 27 V - 26 0.22µF -5V G2 25 TO DISPLAY G3 22 C3 24 A3 23 TO DISPLAY G3 22 BP 21 TO BACKPLANE GND 21 Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V battery). Values shown are for 200mV full scale, 3 readings/sec. IN LO may be tied to either COMMON for inputs floating with respect to supplies, or GND for single ended inputs. (See discussion in “Analog COMMON” on page 7.) FIGURE 11. ICL7106 USING THE INTERNAL REFERENCE FIGURE 12. ICL7107 USING THE INTERNAL REFERENCE Submit Document Feedback 11 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Typical Applications (Continued) TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 100kΩ OSC 2 39 OSC 2 39 OSC 3 38 OSC 3 38 SET VREF = 100mV 100pF TEST 37 TEST 37 REF HI 36 1kΩ CREF 34 0.1µF CREF 33 10kΩ 10kΩ 1MΩ IN HI 31 A-Z 29 CREF 33 IN LO 30 - 6.8V 1MΩ + IN 0.01µF 0.47µF A-Z 29 - 47kΩ BUFF 28 INT 27 INT 27 0.22µF V - 26 100kΩ 0.1µF IN HI 31 47kΩ BUFF 28 1kΩ COMMON 32 IN 0.47µF +5V REF LO 35 CREF 34 + 0.01µF IN LO 30 V+ 1.2V (ICL8069) COMMON 32 V- V - 26 G2 25 A3 23 SET VREF = 100mV 100pF REF HI 36 REF LO 35 C3 24 100kΩ 0.22µF -5V G2 25 C3 24 TO DISPLAY A3 23 G3 22 G3 22 GND 21 GND 21 IN LO is tied to supply COMMON establishing the correct common mode voltage. If COMMON is not shorted to GND, the input voltage may float with respect to the power supply and COMMON acts as a pre-regulator for the reference. If COMMON is shorted to GND, the input is single ended (referred to supply GND) and the preregulator is overridden. FIGURE 13. ICL7107 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) TO DISPLAY Since low TC zeners have breakdown voltages ~ 6.8V, diode must be placed across the total supply (10V). As in the case of Figure 12, IN LO may be tied to either COMMON or GND. FIGURE 14. ICL7107 WITH ZENER DIODE REFERENCE TO PIN 1 OSC 1 40 OSC 2 39 OSC 1 40 100kΩ OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 1V 100pF TEST 37 CREF 33 V+ 25kΩ 24kΩ CREF 33 1MΩ IN HI 31 0.047µF IN - A-Z 29 A3 23 10kΩ 15kΩ 1.2V (ICL8069) 1MΩ + IN 0.01µF 0.47µF +5V - 47kΩ INT 27 0.22µF V- G2 25 C3 24 IN LO 30 BUFF 28 INT 27 V - 26 0.1µF IN HI 31 470kΩ BUFF 28 1kΩ COMMON 32 + 0.01µF A-Z 29 REF LO 35 CREF 34 0.1µF COMMON 32 IN LO 30 SET VREF = 100mV 100pF REF HI 36 REF HI 36 REF LO 35 CREF 34 TO PIN 1 100kΩ V - 26 G2 25 C3 24 TO DISPLAY 0.22µF A3 23 TO DISPLAY G3 22 G3 22 GND 21 BP/GND 21 An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. FIGURE 15. ICL7106 AND ICL7107: RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE Submit Document Feedback 12 FIGURE 16. ICL7107 OPERATED FROM SINGLE +5V FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Typical Applications (Continued) TO PIN 1 V+ OSC 1 40 100kΩ OSC 2 39 100pF TEST 37 OSC 2 39 REF HI 36 REF HI 36 REF LO 35 CREF 34 CREF 34 0.1µF CREF 33 100pF TEST 37 REF LO 35 CREF 33 SCALE FACTOR ADJUST 100kΩ 1MΩ 100kΩ 220kΩ 0.1µF 22kΩ COMMON 32 COMMON 32 IN HI 31 IN HI 31 IN LO 30 IN LO 30 0.47µF A-Z 29 47kΩ BUFF 28 INT 27 0.22µF V - 26 A-Z 29 BUFF 28 INT 27 V - 26 ZERO ADJUST 0.01µF 0.47µF SILICON NPN MPS 3704 OR SIMILAR 47kΩ 9V 0.22µF G2 25 G2 25 A3 23 100kΩ OSC 3 38 OSC 3 38 C3 24 TO PIN 1 OSC 1 40 TO DISPLAY C3 24 A3 23 G3 22 G3 22 GND 21 BP 21 The resistor values within the bridge are determined by the desired sensitivity. FIGURE 17. ICL7107 MEASURING RATIOMETRIC VALUES OF QUAD LOAD CELL Submit Document Feedback 13 TO DISPLAY TO BACKPLANE A silicon diode-connected transistor has a temperature coefficient of about -2mV/°C. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. FIGURE 18. ICL7106 USED AS A DIGITAL CENTIGRADE THERMOMETER FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Typical Applications (Continued) +5V V+ TO LOGIC VCC 1 V+ OSC 1 40 1 V+ OSC 1 40 2 D1 OSC 2 39 2 D1 OSC 2 39 3 C1 OSC 3 38 3 C1 OSC 3 38 4 B1 TEST 37 4 B1 TEST 37 5 A1 REF HI 36 5 A1 REF HI 36 6 F1 REF LO 35 6 F1 REF LO 35 TO CREF 34 LOGIC GND CREF 33 7 G1 8 E1 O/RANGE 9 D2 COMMON 32 10 C2 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 TO LOGIC VCC 12kΩ The LM339 is required to ensure logic compatibility with heavy display loading. LM339 + - VO/RANGE + - + - U/RANGE U/RANGE - CREF 34 8 E1 CREF 33 9 D2 COMMON 32 10 C2 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 V- + CD4023 OR 74C10 CD4023 OR 74C10 7 G1 33kΩ CD4077 FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL7106 OUTPUTS FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUT TO PIN 1 OSC 1 40 100kΩ OSC 2 39 10µF SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) OSC 3 38 TEST 37 100pF 5µF CA3140 REF HI 36 - REF LO 35 CREF 34 CREF 33 100kΩ + AC IN 1N914 1kΩ 22kΩ 470kΩ 0.1µF 2.2MΩ COMMON 32 10kΩ 1µF IN HI 31 1µF 10kΩ 1µF 4.3kΩ IN LO 30 0.47µF A-Z 29 47kΩ BUFF 28 0.22µF 10µF + 9V - INT 27 100pF (FOR OPTIMUM BANDWIDTH) 0.22µF V - 26 G2 25 C3 24 A3 23 TO DISPLAY G3 22 BP 21 TO BACKPLANE Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 21. AC TO DC CONVERTER WITH ICL7106 Submit Document Feedback 14 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Typical Applications (Continued) +5V DM7407 ICL7107 130Ω LED SEGMENTS 130Ω 130Ω FIGURE 22. DISPLAY BUFFERING FOR INCREASED DRIVE CURRENT Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 24, 2014 FN3082.9 Updated to the newest template. Page 1: Updated copyright area. Ordering Information table - removed all non Pb-free parts (all obsolete: ICL7106CPL, ICL7106CM44, ICL7107CPL, ICL7107RCPL, ICL7107RCPLZ, ICL7107SCPL, ICL7107CM44, ICL7107CM44T) and removed ICL7107RCPLZ (obsolete). Page 2, Removed the PDIP pinout for the ICL7107R, as it is obsolete. Page 4, Reworded Electrical Spec Note 9 (formerly note 5) from: "Not tested, guaranteed by design." to: "Limit is not production tested. The maximum was established via characterization and/or design simulations." Page 15, Added Revision History and About Intersil verbiage. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 15 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 50.3 53.2 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). Submit Document Feedback 16 FN3082.9 October 24, 2014 ICL7106, ICL7107, ICL7107S Metric Plastic Quad Flatpack Packages (MQFP) Q44.10x10 (JEDEC MS-022AB ISSUE B) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D D1 -D- INCHES -A- -B- E E1 e PIN 1 SEATING A PLANE -H- 0.076 0.003 -C- 12o-16o 0.40 0.016 MIN 0.20 M 0.008 C A-B S 0o MIN A2 A1 0o-7o L MIN MAX MIN MAX NOTES A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 N 44 44 e 0.032 BSC 0.80 BSC 7 Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . b 4. Dimensions D1 and E1 to be determined at datum plane -H- . b1 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. BASE METAL WITH PLATING SYMBOL D S 0.13/0.17 0.005/0.007 12o-16o MILLIMETERS 0.13/0.23 0.005/0.009 For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 17 FN3082.9 October 24, 2014