NOKIA6610 LCD controller

MF1387-04
S1D15G00 Series
Rev. 1.0
“Seiko Epson is neither licensed nor authorized to license its customers under one or more patents held by
Motif Corporation to use this integrated circuit in the manufacture of liquid crystal display modules. Such
license, however, may be obtained directly from MOTIF by writing to: Motif, Inc., c/o In Focus Systems, Inc.,
27700A SW Parkway Avenue, Wilsonville, OR 97070-9215, Attention: Vice President Corporate
Development.”
 Seiko Epson Corporation 2001, All rights reserved.
Rev. 1.0
Contents
1. DESCRIPTION .................................................................................................................................................. 1
2. FEATURES ........................................................................................................................................................ 1
3. BLOCK DIAGRAM ............................................................................................................................................. 2
4. PIN LAYOUT ..................................................................................................................................................... 3
5. LIST OF DEVICE MODELS ............................................................................................................................... 3
6. PIN COORDINATE ............................................................................................................................................ 4
7. PIN DESCRIPTION ........................................................................................................................................... 6
8. FUNCTIONAL DESCRIPTION ........................................................................................................................ 11
9. COMMANDS ................................................................................................................................................... 30
10. ABSOLUTE MAXIMUM RATING ..................................................................................................................... 42
11. ELECTRIC CHARACTERISTICS .................................................................................................................... 43
12. MPU INTERFACES (EXAMPLES FOR YOUR REFERENCE) ....................................................................... 53
13. PERIPHERAL CONNECTION EXAMPLES .................................................................................................... 58
14. EEPROM INTERFACE .................................................................................................................................... 60
15. CAUTIONS ...................................................................................................................................................... 61
–i–
Rev. 1.0
S1D15G00 Series
1. DESCRIPTION
2. FEATURES
S1D15G00 series are the LCD drivers equipped with
the liquid crystal drive power circuit to realize color
display with one chip.
S1D15G00 can be directly connected to the MPU bus to
store parallel or serial gray-scale display data from
MPU on the built-in RAM and to generate liquid crystal
drive signals independent from MPU. S1D15G00
generates 396 segment outputs and 160*1 common
outputs for driving liquid crystal. It incorporates the
display RAM with capacity of 396 × 168 × 4 (16 grayscale). A single dot of pixel on the liquid crystal panel
corresponds to 4 bits of the built-in RAM, enabling to
display 132 (RGB) × 160 pixels with one chip.
Read or write operations from MPU to the display RAM
can be performed without resorting to external actuating
clock signals. S1D15G00 allows you to run the display
system of high performance and handy equipment at the
minimum power consumption thanks to its low-power
liquid crystal drive power circuit and oscillation circuit.
*1 : The S1D15G00D10*100 generates 300 segment
outputs and 120 common outputs. It incorporates
the display RAM with 300 × 168 × 4 capacity and
displays 100 (RGB) × 120 pixels.
• Number of liquid crystal-drive outputs:
396 segment outputs and 160 common outputs.
• Low cross talk by frame rate modulation.
• 256 color from 4096-color display or full 4096-color
display.
When 256 color from 4096-color display is selected:
8 gray-scale for red and green and 4 gray-scale for
blue (intermediate tone is selected with the command).
When 4096-color display is selected: 16 gray-scale
for red, green and blue.
• Direct data display with display RAM
(When the LCD is set to normally black)
RAM bit Data “0000” ... OFF (Black)
“1111” ...ON (Maximum RGB display)
(Normally black LCD, using "inverse display" command)
• Partial display function: You can save power by
limiting the display space. This function is most
suited for handy equipment in the standby mode.
• Display RAM : 396 × 168 × 4 = 266,112 bits.*1
*1: The S1D15G00D10*000 has RAM of 300 × 120
× 4 = 144,000 bits.
• MPU interface: S1D15G00 can be directly connected
to both of the 8/16-bit parallel 80 and 68 series MPU.
Two type serial interface are also available.
• 3 pins serial : CS, SCL and SI (D/C + 8-bit data)
• 4 pins serial : CS, SCL, SI and A0
• Abundant command functions: Area scroll function,
automatic page & column increment function, display
direction switching function and power circuit control
function.
• Built-in liquid crystal drive power circuit: S1D15G00
is equipped the charge pump booster circuit, voltage
follower circuit and electric volume control circuit.
• Oscillation circuit with built-in high precision CR
(external clock signals acceptable)
• EEPROM interface functions
• Low current consumption
500µA (Conditions: S1D15G00D01B100, VDD =
VDDI = 3.0V, frame frequency 130Hz, V2 = 6.0V, all
display RAM data is “0”)
• Supply voltage
Power for input/output system power:
VDDI–GND=1.7V to 3.6V
Power for internal circuit operation:
VDD–GND=2.6V to 3.6V
Reference power for booster circuit:
VDD2–GND=2.6V to 3.6V
Power for liquid crystal drive:
V3–MV3 =12.0V to 21.0V
• Wider operational range: –40°C to 85°C.
• Shipping from: Chip with gold bump. COF.
• Note that the radiation resistant design or light
resistance design in strict sense is not employed for
S1D15G00.
Rev. 1.0
EPSON
1
S1D15G00 Series
• • • • • • • •
COM160
COM1
• • • • • • • • • • • • • • • • • • • •
SEG396
SEG1
3. BLOCK DIAGRAM
V3
V2
V1
VC
MV1
SEG Drivers
COM Drivers
MV2(GND)
MV3
COM decoder
Shift register
SEG decoder
Display data latch
CAP1+
DDRAM
396 x 168 x 4
Display timing signal
generation circuit
CAP4–
CAP5+
SLP
YSCL
Block address
Page address
CAP4+
Power circuit
CAP1–
CAP2+
CAP2–
VCLS
CPP5–
I/O buffer
VDD2
F1,F2
CA
FR
SYNC
CL
DOFF
M/S
Column address
Oscillation
circuit
VDD3 to 5
VDD
VDDI
CLS
Bus holder
Command decoder
EEPROM
interface
MPU interface
GND
2
EPSON
SRCM
TEST
D15 to D0
SCL
SI
IF1,IF2,IF3
A0
CS
WR(R/W)
RD(E)
RES
SDA
CLOCK
RESET
GND2 to 4
Rev. 1.0
S1D15G00 Series
4. PIN LAYOUT
792
205
Y
(0,0)
Die No.
X
1
204
25.04 mm × 2.70 mm
725 µm±25 µm (for reference)
See Section 5 “List of Device Models.”
GND
Tolerance: bump of the shorter side ±3 µm, bump of the longer side ±4 µm (reference)
Driver output side: 30 µm × 137 µm
Driver input side: 82 µm × 109 µm
Bump pitch
Driver output side: 42 µm
I/O signal line side:100 µm min.
Bump height
22.5 µm±4 µm (for reference) : S1D15G00D0*B0
Alignment coordinate
1 (–11974.2, –639.2)
2 (12091.8, –730.4)
Mark size
a = 80 µm
b = 20 µm
Chip size
Chip thickness
Die No.
Potential on board
Bump size
b
a
5. LIST OF DEVICE MODELS
Model name
Die No.
Output
count
S1D15G00D00*100 D15G0D0B Segment: 396
(#)
Common: 160
S1D15G00D05*100 D15G0D5B
S1D15G00D01*100 D15G0D1B
(#)
S1D15G00D06*100 D15G0D6B
S1D15G00D03*100 D15G0D3B
(#)
S1D15G00D08*100 D15G0D8B
S1D15G00D10*100 D15G0DAB Segment: 300
(#)
Common: 120
V2 voltage
control resistor
External/Internal
Internal only
(voltage electronically
controlled via
electronic volume)
External only
(voltage controlled
via VR pin
resistance)
External only
(voltage controlled
via VR pin
resistance)
External only (voltage
via VR pin resistance)
Access
to EEPROM
MPU RAM
read
Unable to read
Frame frequency
/built-in oscillation
frequency
130 Hz
/41.6 kHz
Read enabled
×
Unable to read
Read enabled
×
Unable to read
180 Hz
/57.6 kHz
Read enabled
×
Unable to read
130 Hz
/31.2 kHz
(Note)
For “unable to read” models in the above diagram, the MPU cannot read the RAM. If the RAM must be read, use “read
enabled” models.
(#) : These models will be discontinued.
Rev. 1.0
EPSON
3
S1D15G00 Series
6. PIN COORDINATE
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
4
Pin
Name
NC
NC
V3L
V3L
V3L
V2L
V2L
V2L
V2L
V1L
V1L
V1L
V1L
VCL
VCL
VCL
VCL
VCLSL
VCLSL
VCLSL
VCLSL
MV1L
MV1L
MV1L
MV1L
MV3L
MV3L
MV3L
TESTA
TESTB
TESTC
TESTD
TESTE
TESTF
TESTF
TESTF
TESTF
TESTF
CAP2+
CAP2+
CAP2+
CAP2+
CAP2+
CAP2–
CAP2–
CAP2–
CAP2–
CAP2–
CAP1+
CAP1+
CAP1+
CAP1+
CAP1+
CAP1–
CAP1–
CAP1–
CAP1–
X
Y
–12331 –1188.5
–12211
–12091
–11971
–11851
–11731
–11611
–11491
–11371
–11251
–11131
–11011
–10891
–10771
–10651
–10531
–10411
–10291
–10171
–10051
–9931
–9811
–9691
–9571
–9451
–9331
–9211
–9091
–8971
–8871
–8771
–8671
–8571
–8451
–8336
–8221
–8106
–7991
–7871
–7756
–7641
–7526
–7411
–7291
–7176
–7061
–6946
–6831
–6711
–6596
–6481
–6366
–6251
–6131
–6016
–5901
–5786
Unit: µm
PAD
No.
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
Pin
X
Y
Name
CAP1– –5671 –1188.5
GND2 –5551
GND2 –5446
GND2 –5341
GND2 –5236.05
GND2 –5131.05
GND3 –5026.05
GND3 –4921
GND3 –4816
GND
–4711
GND
–4606
GND
–4501
VDD3
–4396
VDD3
–4291
VDD4
–4186
VDD4
–4081
TESTG –3976
VDD
–3871
VDD
–3766
VDDI
–3661
VDDI
–3556
VDDI
–3451
VDDI
–3346
FR
–3235
YSCL –3081
F1
–2927
F2
–2773
DOFF –2619
CA
–2465
SYNC –2311
SLP
–2157
SDA
–2003
RESET –1849
CLOCK –1695
TEST1 –1541
GND *6 –1387
VDDI *6 –1287
CL
–1187
CLS
–1033
GND *6 –879
VDDI *6 –779
CS
–679
A0
–525
GND *6 –371
VDDI *6 –271
SCL
–171
SI
–17
GND *6 137
VDDI *6 237
D0
337
D1
491
D2
645
D3
799
D4
953
D5
1107
D6
1261
D7
1415
EPSON
PAD Pin
No. Name
115 GND *6
116 VDDI *6
117
D8
118
D9
119
D10
120
D11
121
D12
122
D13
123
D14
124
D15
125 GND *6
126 VDDI *6
127
RD
128
WR
129 GND *6
130 VDDI *6
131
IF1
132
IF2
133
IF3
134 GND *6
135 VDDI *6
136 RES
137 TESTH
138
MS
139 VDDI
140 VDDI
141 GND
142 GND
143 GND
144 GND
145 GND4
146 GND4
147 GND4
148 GND4
149 GND4
150
VDD
151
VDD
152 VDD5
153 VDD5
154 VDD2
155 VDD2
156 VDD2
157 VDD2
158 VDD2
159 VDD2
160 CAP4+
161 CAP4+
162 CAP4+
163 CAP4+
164 CAP4+
165 CAP4–
166 CAP4–
167 CAP4–
168 CAP4–
169 CAP4–
170 CAP5+
171 CAP5+
X
Y
1569 –1188.5
1669
1769
1923
2077
2231
2385
2539
2693
2847
3001
3101
3201
3355
3509
3609
3709
3863
4017
4171
4271
4371
4525
4679
4833
4938
5043
5148
5253.05
5358.05
5463.05
5568.05
5673.05
5778.05
5883.05
5988.05
6093.05
6198.05
6303.05
6446.05
6551.05
6656.05
6761.05
6866.05
6971.05
7113.05
7228.05
7343.05
7458.05
7573.05
7693.05
7808.05
7923.05
8038.05
8153.05
8273.05
8388.05
Rev. 1.0
S1D15G00 Series
Unit: µm
PAD
No.
172
173
174
175
176
177
178
179
180
181
Pin
X
Y
Name
CAP5+ 8503.05 –1188.5
CAP5+ 8618.05
CAP5+ 8733.05
CAP5– 8853
CAP5– 8968
CAP5– 9083
CAP5– 9198
CAP5– 9313
MV 3R
9433
MV 3R
9553
PAD
No.
182
183
184
185
186
187
188
189
190
191
Pin
Name
MV 3R
MV 1R
MV 1R
MV 1R
MV 1R
VCLSR/VR *7
VCR
VCR
VCR
VCR
X
Y
9673 –1188.5
9793
9913
10033
10152.9
10273
10393
10513
10633
10753
PAD Pin
No. Name
192
V1R
193
V1R
194
V1R
195
V1R
196
V2R
197
V2R
198
V2R
199
V2R
200
V3R
X
10873 –1188.5
10993
11113
11233
11353
11473
11593
11713
11833
Unit: µm
Models other than the S1D15G00D10*000
PAD
No.
201
202
203
204
205
206
207
208
209
to
284
285
286
Pin
Name
V3R
V3R
NC
NC
NC
NC
COM1
COM2
COM3
to
COM78
COM79
COM80
X
Y
11953 –1188.5
12073
12193
12313
12327
1177
12285
12243
12201
*1
9009
8967
8925
PAD Pin
No. Name
287
NC
288 to
NC
299
300
NC
301 SEG396
302 SEG395
303 SEG394
to
to
694 SEG3
695 SEG2
696 SEG1
697
NC
X
Y
8883
1177
*2
8337
8295
8253
*3
–8211
–8253
–8295
–8337
PAD Pin
No. Name
698 to
NC
709
710
NC
711 COM81
712 COM82
713 COM83
to
to
788 COM158
789 COM159
790 COM160
791
NC
792
NC
X
*4
Pin
Name
V3R
V3R
NC
NC
NC
NC
COM1
COM2
COM3
to
COM58
COM59
COM60
X
1177
–12159
–12201
–12243
–12285
–12327
Unit: µm
Y
11953 –1188.5
12073
12193
12313
12327
1177
12285
12243
12201
*1
9849
9807
9765
Y
–8883
–8925
–8967
*5
S1D15G00D10*000
PAD
No.
201
202
203
204
205
206
207
208
209
to
264
265
266
Y
PAD Pin
X
No. Name
287
NC
8883
288 to
NC
*2
299
300
NC
8337
349 SEG348 6279
350 SEG347 6237
351 SEG346
*8
to
to
649 SEG51
650 SEG50
651 SEG49
697
NC
–8337
Y
1177
PAD
No.
698 to
709
710
711
712
713
to
768
769
770
791
792
Pin
Name
X
NC
*4
NC
COM61
COM62
COM63
to
COM118
COM119
COM120
NC
NC
–8883
–8925
–8967
*5
Y
1177
–11319
–11361
–11403
–12285
–12327
*1: You can determine the position on X coordinate from the formula “12159–42* (n–209)”, where the BUMP No. is “n”.
*2: You can determine the position on X coordinate from the formula “8841–42* (n–288)”, where the BUMP No. is “n”.
*3: You can determine the position on X coordinate from the formula “8211–42* (n–303)”, where the BUMP No. is “n”.
*4: You can determine the position on X coordinate from the formula “-8379–42* (n–698)”, where the BUMP No. is “n”.
*5: You can determine the position on X coordinate from the formula “-9009–42* (n–713)”, where the BUMP No. is “n”.
*6: This pin is used to pull up or pull down nearby pins. Thus, it can’t be used for feeding power.
*7: The pin function differs among device models.
External resisting device: It functions as the primary boost voltage output pin (VCLSR).
Internal resisting device: It functions as the regulator inverse input pin (VR).
*8: You can determine the position on X coordinate from formula “6145-42*(n–351)” where the Bump No. is “n”.
Rev. 1.0
EPSON
5
S1D15G00 Series
7. PIN DESCRIPTION
7.1 Power Supply Pins
Pin name
VDDI
VDD
VDD2
I/O
Input
power
Power
supply
Step-up
power
VDD3,VDD5 Power
supply
Power
VDD4
supply
GND
Power
supply
GND2,
Power
GND4
supply
GND3
Power
supply
Power
V3L, V3R
V2L, V2R
supply
V1L, V1R
VCL, VCR
MV1L, MV1R
MV3L, MV3R
Description
They are used to connect the power for input signals.
Number of
pins
6
They are connected to VCC - the system power. When the system
power is smaller than 2.6V, they must be connected another 2.6V
or greater power supply.
They are used to connect the power supply for the primary step-up.
The relative magnitude of potential among the pins, namely
VDD2≥V DD≥VDD1, must be observed.
They are power supply pins on the power circuit *1.
4
6
They are power supply pins on the oscillation circuit *1.
2
They are connected to the system ground.
7
They are grounding pins on the power circuit *2.
9
They are grounding pins on the oscillation circuit *2.
3
These pins are provided on the multi-level power supply for liquid
crystal drive. Relative magnitude of potential among the pins,
namely V3L(R)≥V2L(R)≥V1L(R)≥VCL(R)≥MV1L(R)≥GND≥MV 3L(R),
must be observed.
When the master operation is turned on or the internal power supply
is turned on, predetermined voltage is output at respective pins.
When S1D15G00 series are used in the master/slave array, they
connect the pins on both the master and slave drivers.
They are provided on the common driver operating power supply.
44
4
Power
4
supply
Input
Common driver operating power supply/regulator input pins *3.
1
VCLSR,VR
power
*1: Since VDD, VDD3, VDD4 and V DD5 are not internally connected, they must be externally connected to VCC - the
system power.
*2: Since GND, GND2, GND3 and GND4 are not internally connected, they must be externally connected to the system
GND (ground).
*3: The pin function differs among device models.
VCLSL
6
EPSON
Rev. 1.0
S1D15G00 Series
7.2 Pins on Liquid Crystal Drive Power Circuit
Pin name
I/O
CAP1+
CAP1–
CAP2+
CAP2–
CAP4+
CAP4–
CAP5+
CAP5–
O
O
O
O
O
O
O
O
Rev. 1.0
Description
They connect the positive going side of the primary step-up capacitor.
They connect the negative going side of the primary step-up capacitor.
They connect the positive going side of the secondary step-up capacitor.
They connect the negative going side of the secondary step-up capacitor.
They connect the positive going side of the tertiary step-up capacitor.
They connect the negative going side of the tertiary step-up capacitor.
They connect the positive going side of the tertiary step-up capacitor.
They connect the positive going side of the tertiary step-up capacitor.
EPSON
Number of
pins
5
5
5
5
5
5
5
5
7
S1D15G00 Series
7.3 MPU Interface Pins
Pin name
I/O
Description
D15 to D0
I/O
They connect to the standard 8-bit or 16-bit MPU bus via the
8/16-bit bi-directional bus.
When the following interface is selected and the CS pin is high, the
impedance of the pin becomes high.
1 8-bit parallel: D15-D18 are in the state of high impedance
2 Serial interface: D15-D0 are in the state of high impedance
This pin is used to input serial data when the serial interface is selected.
This pin is used to input serial clock when the serial interface is selected.
These pins are used to select either of the MPU interfaces.
Depending on status of IF1, IF2 and IF3, following selection is made.
SI
SCL
IF1, IF2
IF3
I
I
I
IF1
HIGH
HIGH
HIGH
LOW
LOW
LOW
A0
I
CS
I
RD (E)
I
WR (R/W)
I
RES
I
8
IF2
HIGH
HIGH
LOW
HIGH
LOW
LOW
IF3
HIGH
LOW
LOW
HIGH
HIGH
LOW
1
1
3
MPU interface type
80 series 16-bit parallel
80 series 8-bit parallel
68 series 16-bit parallel
68 series 8-bit parallel
9-bit serial
8-bit serial
Normally, the least significant bit of the MPU’s address bus is
connected to identify a parameter or display data from a command.
HIGH: Indicates that data entered to D15 to D0 or SI is a
parameter or display data.
LOW: Indicates that data entered to D15 to D0 or SI is a command.
This function is disabled when the 9-bit serial interface is selected.
This pin is used to enter chip select signal. It is activated when
CS = LOW, enabling interface with MPU.
• It goes active LOW when connected to the 80 series MPU.
This pin is used to connect RD signal from the 80 series MPU. The data
bus is maintained in the output status as long as this signal is LOW.
• It goes active HIGH when connected to the 68 series MPU.
In this case, this pin is used to enter the enable clock from 68 series MPU.
• It goes active LOW when connected to the 80 series MPU.
This pin connects WR signal from the 80 series MPU. Signal on
the data bus is latched at the positive going edge of WR signal.
• This pin enters the read/write signal when connected to the 68 series MPU.
R/W = HIGH: Read
R/W = LOW: Write
Causing RES to LOW performs initialization.
Reset operation is performed according the level of RES signal.
EPSON
Number of
pins
16
1
1
1
1
1
Rev. 1.0
S1D15G00 Series
7.4 Liquid Crystal Drive Circuit Signals
Pin name
I/O
Description
M/S
I
CLS
I
This pin is used to select either the master or slave operation.
M/S = HIGH: Master operation
It is used to select the display clock.
CLS = HIGH: Built-in CR oscillation is used.
CLS = LOW: External clock is used.
When the external clock is used (CLS = LOW), the signal is
entered to CL pin.
This pin inputs or outputs the display clock.
It outputs the display clock only when M/S = HIGH and CLS = HIGH.
Other than the above: External clock input
This pin inputs or outputs the liquid crystal frame signal.
M/S = HIGH: Outputs the signal
M/S = LOW: Inputs the signal
This pin inputs or outputs the liquid crystal synchronization signal.
M/S = HIGH: Outputs the signal
M/S = LOW: Inputs the signal
This pin inputs or outputs the field start signal.
M/S = HIGH: Outputs the signal
M/S = LOW: Inputs the signal
This pin inputs or outputs the drive pattern signal.
M/S = HIGH: Outputs the signal
M/S = LOW: Inputs the signal
This pin is used to control blanking of liquid crystal display.
M/S = HIGH: Outputs the signal
M/S = LOW: Inputs the signal
This pin inputs or outputs the line clock.
M/S = HIGH: Outputs the signal
M/S = LOW: Inputs the signal
They output the signal for the segment drive of liquid crystal.
They output the signal for common drive of liquid crystal.
CL
I/O
FR
I/O
SYNC
I/O
CA
I/O
F1, F2
I/O
DOFF
I/O
YSCL
I/O
SEGn
COMn
O
O
Rev. 1.0
EPSON
Number of
pins
1
1
1
1
1
1
1
1
396
160
9
S1D15G00 Series
7.5 EEPROM Interface Pins
Pin name
I/O
Description
SDA
O
Connected to the SDA pin of S1F65170. *1
RESET
O
Connected to the XRST pin of S1F65170. *1
CLOCK
O
Connected to the SCK pin of S1F65170. *1
* Always open if the S1F65170 is not used.
Number of
pins
1
1
1
7.6 Control Signals
Pin name
I/O
Description
SLP
O
PO0
O
It is the sleep control pin. It outputs LOW level when the sleep-in
command is executed.
This pin constantly outputs LOW level. It must be maintained open.
Number of
pins
1
1
7.7 Test Signals
Pin name
I/O
TESTA to
TESTG
TESTH
TEST1
O
10
I
I
Description
It is the test pin.
Since it outputs signals, it must be kept open.
This pin must be fixed at HIGH or LOW.
It is the IC chip test pin. This pin must be fixed at LOW.
EPSON
Number of
pins
1
1
1
Rev. 1.0
S1D15G00 Series
8. FUNCTIONAL DESCRIPTION
8.1 MPU Interfaces
8.1.1 Selecting an MPU Interface Type
S1D15G00 transfers data via the 8/16-bit bi-directional data bus or serial data input.
You can select a desired interface face through the combinations of settings of IF1, IF2 and IF2 as shown in Table 8.1.1.
Table 8.1.1
IF1
IF2
IF3
Interface type
CS
A0
HIGH
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
80 series 16-bit parallel
80 series 8-bit parallel
68 series 16-bit parallel
68 series 8-bit parallel
9-bit serial
8-bit serial
CS
CS
CS
CS
CS
CS
A0
A0
A0
A0
–
A0
RD
E
RD
RD
E
E
–
–
WR D15 to D8 D7 to D0 SI S C L
R/W
WR D15 to D8 D7 to D0 – –
WR
(HZ)
D7 to D0 – –
R/W D15 to D8 D7 to D0 – –
R/W
(HZ)
D7 to D0 – –
–
(HZ)
(HZ)
SI SCL
–
(HZ)
(HZ)
SI SCL
– : Must be fixed to either HIGH or LOW.
HZ is in the state of Hight Impedance.
8.1.2 8- or 16-bit Parallel Interface
S1D15G00 identifies type of the data bus signals according to combinations of A0, RD (E) and WR (R/W) signals as
shown in Table 8.1.2.
Table 8.1.2
68 series
80 series
A0
1
R/W
0
E
1
RD
1
WR
0
Function
Parameters or display data write.
1
1
1
0
1
Display data read.
0
0
1
0
1
1
0
1
1
0
Status read.
Control data write (command).
Except when the CS=LOW is taking place, D15 to D0 on S1D15G00 are caused to high impedance, disabling input of
A0, RD (E) and WR (R/W).
Relation between Data Bus and Gradation Data
S1D15G00 offers the 256-color display (8 gray-scale) out of 4096 colors as well as the 4096-color display (16 grayscale). When using 256-color display out of 4096 colors, you can specify color for each of R, G and B using the palette
function.
(1) 256-color display out of 4096 colors
Using RGBSET8 command enables you to set color for each of R, G and B by turning on the palette function
prepared to convert 3- or 2-bit data to 4-bit data.
1 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRGGGBB (8 bits) data is converted to RRRRGGGGBBBB (12 bits) and then
stored on the display RAM.
2 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8: RRRGGGBB (8 bits)
D7, D6, D5, D4, D3, D2, D1, D0: RRRGGGBB (8 bits)
Data of two pixels is respectively converted to RRRRGGGGBBBB (12 bits) data and then simultaneously written
to two addresses on the display RAM.
Rev. 1.0
EPSON
11
S1D15G00 Series
4096 color display
1 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGG (8 bits) 1st write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBRRRR (8 bits) 2nd write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB (8 bits) 3rd write
Data is acquired through write operations as shown above and then that of two pixels is written to the display RAM.
2 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGGBBBBXXXX (12 bits)
Data is acquired through single write operation and then written to the display RAM.
“XXXX” are dummy bits, and they are ignored for display.
8.1.3 8- and 9-bit Serial Interface
The 8-bit serial interface uses four pins - CS, SI, SCL and A0 - to enter commands and data. Meanwhile, the 9-bit serial
interface uses three pins - CS, SI and SCL - for the same purpose.
Data read is not available with the serial interface. Data entered must be 8 bits. Refer to the following chart for entering
commands, parameters or gray-scale data.
The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface
mode (described in the preceding section) at every gradation.
(1) 8-bit serial interface
When entering data (parameters): A0 = HIGH at the rising edge of the 8th SCL.
CS
dot1(G)
dot0(R)
SI
dot3(R)
dot2(B)
dot4(R)
R2
R1
R0
G2
G1
G0
B1
B0
R2
R1
R0
G2
G1
G0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
SCL
A0
When entering command: A0 = LOW at the rising edge of the 8th SCL.
CS
command
SI
command
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
SCL
A0
12
EPSON
Rev. 1.0
S1D15G00 Series
(2) 9-bit serial interface
When entering data (parameters): SI = HIGH at the rising edge of the 1st SCL.
CS
dot1(G)
dot0(R)
SI
dot3(R)
dot2(B)
R2
R1
R0
G2
G1
G0
B1
B0
D/C
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
R2
R1
R0
D/C
D7
D6
D5
D4
1
2
3
4
5
SCL
When entering commands: SI = LOW at the rising edge of the 1st SCL.
CS
command
SI
command
D/C
D7
D6
D5
D4
D3
D2
D1
D0
D/C
D7
D6
D5
D4
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCL
* If CS is caused to HIGH before 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering
succeeding sets of data, you must correctly input the data concerned again.
* In order to avoid data transfer error due to incoming noise, it is recommended to set CS at HIGH on byte basis to
initialize the serial-to-parallel conversion counter and the register.
Rev. 1.0
EPSON
13
S1D15G00 Series
8.2 Access to DDRAM and Internal Registers
S1G15G00 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the
bus holder attached to the internal, requiring the cycle time alone without needing the wait time.
For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the
DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle
is dummy and the data read in the dummy cycle is held by the bus holder, and then it is read from the bus holder to the
system bus in the succeeding read cycle. Fig. 8.2.1 illustrates these relations.
* Write operation
A0
tcyc
WR
Command write
MPU
Data write
Data write
DATA
Bus holder
Internal
Data write
signal
* Read operation
A0
Command write
WR
Dummy read
Data read
RD
MPU
External pulse
Bus holder
Command
RAM data
RAM data
Internal
Data Read
signal
Fig. 8.2.1
* There is a restriction in the read sequence of the DDRAM. Namely, the data at the specified address is not output
in the first data read conducted immediately after the memory read command (dummy read). It is read in the second
data read.
14
EPSON
Rev. 1.0
S1D15G00 Series
8.3 DDRAM
8.3.1 DDRAM
It is 396 × 168 × 4 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page
address and column address.
Since display data from MPU - D7 to D0 and D1 to D8 - correspond to one or two pixels of RGB, data transfer-related
restrictions are reduced, realizing the display flexibly.
The RAM on S1D15G00 is separated to a block per 4 line to allow the display system to process data on the block basis.
MPU’s read and write operations to and from the RAM are performed via the I/O buffer circuit. Reading of the RAM
for the liquid crystal drive is controlled from another separate circuit.
Refer to the following memory map for the RAM configuration.
1Models other than the S1D15G00D10*100 (models that have 132 RGB × 160 output)
Memory Map (When using the 8 gray-scale. 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11:0
0
1
131
P11:1
131
132
0
Color
Page
Block
0
1
2
40
41
SEGout
P10:0
R
G
B
R
G
B
R
G
B
Data
D7
D6
D4
D3
D1
D0
D7
D6
D4
D3
D1
D0
D7
D6
D4
D3
D1
D0
P10:1
D5
D2
D5
D2
D5
D2
1
2
4
5
394
395
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
160
7
161
6
162
5
163
4
164
3
165
2
166
1
167
0
3
6
396
Each of RGB data entered to D7 to D0 (3 or 2 bits) is converted to 4 bits before written to the RAM. You can change
position of R and B with DATCTL command.
Rev. 1.0
EPSON
15
S1D15G00 Series
Memory Map (When using the 8 gray-scale, 16-bit mode)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11: 0
0
0
1
1
65
P11: 1
65
65
64
64
0
R
Color
0
1
2
40
41
SEGout
P10:0
B
R
G
B
R
G
B
R
G
B
R
G
B
Data D15 D12 D9 D7 D4 D1 D15 D12 D9 D7 D4 D1
D7 D4 D1
D14 D11 D8 D6 D3 D0 D14 D11 D8 D6 D3 D0
D6 D3 D0
D13 D10
D5 D2
D5 D2
10 11 12
394 395 396
Page
Block
G
P10:1
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
160
7
161
6
162
5
163
4
164
3
165
2
166
1
167
0
1
2
D5 D2
3
4
5
D13 D10
6
7
8
9
Each of RGB data entered to D7 to D0 (3 or 2 bits) is converted to 4 bits before written to the RAM. You can change
position of R and B with DATCTL command.
16
EPSON
Rev. 1.0
S1D15G00 Series
Memory Map (When using the 16 gray-scale 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11: 0
0
0
1
1
65
P11: 1
65
65
64
64
0
R1 G1 B1 R2 G2 B2 R1 G1 B1 R
Color
D7
D6
D5
P10:1
D4
Data
Page
Block
0
1
2
40
41
SEGout
P10:0
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
160
7
161
6
162
5
163
4
164
3
165
2
166
1
167
0
1
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
2
3
4
5
6
7
8
9
D3
D2
D1
D0
G2 B2
R2 G2 B2
D7
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
D0
10 11 12
D7
D6
D5
D4
D3
D2
D1
D0
394 395 396
You can change position of R and B with DATCTL command.
Rev. 1.0
EPSON
17
S1D15G00 Series
Memory Map (When using the 16 gray-scale 16-bit mode)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11:0
0
1
131
P11:1
131
130
0
Color
Data
Page
Block
0
1
2
40
41
SEGout
P10:0
P10:1
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
160
7
161
6
162
5
163
4
164
3
165
2
166
1
167
0
R
G
B
R
G
B
R
G
B
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
1
2
3
4
5
6
394
395
396
You can change position of R and B with DATCTL command
18
EPSON
Rev. 1.0
S1D15G00 Series
2 S1D15G00D10*100 (100 RGB × 120 output)
Memory map (when 8-tone, 8-bit mode is used)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11:0
16
17
115
P11:1
115
114
16
Color
Page
Block
0
1
2
28
29
SEGout
P10:0
R
G
B
R
G
B
R
G
B
Data
D7
D6
D4
D3
D1
D0
D7
D6
D4
D3
D1
D0
D7
D6
D4
D3
D1
D0
P10:1
D5
D2
D5
D2
D5
D2
49
50
52
53
346
347
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
112
55
113
54
114
53
115
52
116
51
117
50
118
49
119
48
51
54
348
Although data is described as D7 - D0 (3 bits or 2 bits), all RGB data will be converted to 4 bits and written to the RAM.
Positions of R and B can be changed using the DATCTL command.
Rev. 1.0
EPSON
19
S1D15G00 Series
Memory map (when 8-tone, 16-bit mode is used)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11: 0
8
8
9
9
57
P11: 1
57
57
56
56
8
R
Color
Page
Block
0
1
2
28
29
SEGout
P10:0
G
B
R
G
B
R
G
B
R
G
B
Data D15 D12 D9 D7 D4 D1 D15 D12 D9 D7 D4 D1
D14 D11 D8 D6 D3 D0 D14 D11 D8 D6 D3 D0
P10:1 D13 D10
D5 D2
D13 D10
D5 D2
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
112
55
113
54
114
53
115
52
116
51
117
50
118
49
119
48
49 50 51 52 53 54 55 56 57 58 59 60
R
G
B
D7 D4 D1
D6 D3 D0
D5 D2
346 347 348
Although data is described as D7 - D0 (3 bits or 2 bits), all RGB data will be converted to 4 bits and written to the RAM.
Positions of R and B can be changed using the DATCTL command.
20
EPSON
Rev. 1.0
S1D15G00 Series
Memory map (when 16-tone, 8-bit mode is used)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11: 0
8
8
9
9
57
P11: 1
57
57
56
56
8
R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2
Color
Page
Block
0
1
2
28
29
SEGout
P10:0
Data D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
P10:1
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
112
55
113
54
114
53
115
52
116
51
117
50
118
49
119
48
49 50 51 52 53 54 55 56 57 58 59 60
R2 G2 B2
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
346 347 348
Positions of R and B can be changed using the DATCTL command.
Rev. 1.0
EPSON
21
S1D15G00 Series
Memory map (when 16-tone, 16-bit mode is used)
RGB alignment (Command of data control parameter2=000)
Column
LCD
read
direction
P11:0
16
17
115
P11:1
115
114
16
Color
Data
Page
Block
0
1
2
28
29
SEGout
P10:0
P10:1
0
167
1
166
2
165
3
164
4
163
5
162
6
161
7
160
8
159
9
158
112
55
113
54
114
53
115
52
116
51
117
50
118
49
119
48
R
G
B
R
G
B
R
G
B
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D1
D1
D1
D1
D11
D10
D9
D8
D7
D6
D5
D4
49
50
51
52
53
54
346
347
348
Positions of R and B can be changed using the DATCTL command.
22
EPSON
Rev. 1.0
S1D15G00 Series
8.3.2 Page Address Control Circuit
This circuit is used to control the address in the page direction when MPU accesses the DDRAM or when reading the
DDRAM to display image on the LCD.
You can specify a scope of the page address (start and end page) with PASET (page address set) command. When the
page-direction scan is specified with DATCTL (data control) command and the addresses are incremented from the start
up to the end page, the column address is incremented by 1 and the page address returns to the start page.
The DDRAM supports up to 168 lines*1, and thus the total page becomes 168.
*1: S1D15G00D10*000 supports up to 120 lines and the total number of pages is 120.
In the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page
address is returned to the start page.
Using the address normal/inverse parameter of DATCTL command allows you to inverse the correspondence between
the DDRAM address and common output.
8.3.3 Column Address Control Circuit
This circuit is used to control the address in the column direction when MPU accesses the DDRAM. You can specify
a scope of the column address (start and end column) using CASET (column address set). When the column-direction
scan is specified with DATCTL command and the addresses are incremented from the start to the end up to the end
column, the page address is incremented by 1 and the column address returns to the start column.
In the read operation, too, the column address is automatically incremented by 1 and returns to the start page as the end
column is reached.
Just like the page address control circuit, using the column address normal/inverse parameter of DATCTL command
enables to inverse the correspondence between the DDRAM column address and segment output. This arrangement
relaxes restrictions in the chip layout on the LCD module.
8.3.4 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU’s read or write of the DDRAM
is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM while
the LCD is turned on does not cause troubles such as flicking of the display images.
8.3.5 Block Address Circuit
This circuit associates pages on the DDRAM with COM output. S1D15G00 processes signals for the liquid crystal
display on 4-page basis (block basis). Thus, when specifying a specific area in the area scroll display or partial display,
you must designate it in block.
8.3.6 Display Data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since
DISNOR/DISINV (display normal/inverse) and DISON/DISOFF (display on/display off) commands are used to
control data in the latch circuit alone, they do not modify data in the DDRAM.
Rev. 1.0
EPSON
23
S1D15G00 Series
8.4 Area Scroll Display
Using ASCSET (area scroll set) and SCSTART (scroll start set) commands allows you to scroll the display screen
partially. You can select any one of the following four scroll patterns.
Center screen scroll
: Fixed area
Top screen scroll
Bottom screen scroll
Whole screen scroll
: Scroll area
Fig. 8.4.1
When, for example, 1/128 duty (Display area: 32 blocks = 128 lines) is selected, and the top 2 blocks = 8 lines and bottom
2 blocks = 8 lines are specified as the fixed areas and the remaining 28 blocks = 112 lines as the scroll area, 10 blocks
= 40 lines on the DDRAM can be used as the background area.
DDRAM block
LCD panel
0
1
2
32 blocks
=128 line
29
30
39
Fixed area
40
Display area
Scroll area
41
Background area
24
EPSON
Rev. 1.0
S1D15G00 Series
8.5 Partial Display
Using PTLIN (partial in) command allows you to turn on the partial display (division by line) of the screen. This mode
requires less current consumption than the whole screen display, making it suitable for the mobile equipment in the
standby state.
: Display area (partial display area)
: Non-display area
8.6 Gray-Scale Display
This function represents gray-scale by frame modulating the gray-scale date written on the display data RAM. In the
256-out-of-4096 colors (8 gray-scale) display, you can specify display colors using the command.
Normally black liquid crystal in the reverse display mode - 8 gray scale display
R (D7,D6,D5)
Black
(0,0,0)
Red
G (D4,D3,D2)
Black
(0,0,0)
(0,0,1)
(0,1,0)
(0,1,1)
(1,0,0)
(1,0,1)
(1,1,0)
(1,1,1)
B (D1,D0)
Black
(0,0)
(0,1)
(0,1)
(0,1)
(1,0)
(1,0)
(1,0)
(1,1)
(0,0,1)
(0,1,0)
(0,1,1)
(1,0,0)
(1,0,1)
(1,1,0)
(1,1,1)
Green
Blue
Any one of above
Any one of above
Respective data on red, green and blue are converted to the display data to be specified by the parameters of RGBSET8
command, and then written to the DDRAM. Blue is displayed in 4 gray-scale.
8.7 Oscillation Circuit
S1G15G00 contains the oscillation circuit whose operation does not require any external part. The oscillation circuit
is enabled only when M/S = HIGH and CLS = HIGH. When the external clock signal is (CLS = LOW or M/S = LOW),
the clock is entered from CL pin.
8.8 Display Timing Generation Circuit
This circuit generates the timing signal for display (CL, FR, SYNC, CA, F1, F2, DOFF) using the clock from the builtin oscillation circuit or the external clock.
It is also used to generate the clock to turn on the liquid crystal-drive power circuit.
When using S1D15G00 in multi-chip array, the display timing signal (CL, FR, SYNC, CA, F1, F2, DOFF) must be sent
from the master to the slave.
8.9 SEG Decoder Circuit
This circuit outputs the segment driver control signal based on display data for 4-page and the timing signal.
8.10 Liquid Crystal Drive Circuit
It outputs liquid crystal drive voltage. Responding to the decoder output signal and the display-timing signal, the
segment output pin outputs one of potentials V2, V1 , VC, MV1 or MV2 and the common output pin outputs one of
potentials V3, VC or MV3.
Rev. 1.0
EPSON
25
S1D15G00 Series
8.11 Liquid Crystal-Drive Power Circuit
The power circuit contained in S1D15G00 generates voltage required to drive liquid crystal. This low power
consumption type power circuit is consisted the voltage regulator, booster circuits (primary, secondary) and voltage
follower. The power circuit is enabled only when the master operation mode is turned on.
The power control circuit turns on or off the voltage regulator, booster circuits, Reference voltage generation circuit
and voltage follower responding to PWRCTR (power control set) command. Thus, function of the external and internal
power supplies can be partly used in parallel.
Table 8.11.1 lists the functions controlled by the 4-bit data - parameter of PWRCTR. Table 8.11.2 shows combinations
of 4 bits (combinations shown in Table 8.11.2 alone are valid).
Table 8.11.1
Item
D3
D2
D1
D0
State
Primary booster circuits control bit
Secondary booster circuit control bit
Reference voltage generation circuit control bit
Voltage adjusting circuit/Voltage follower control bit
“1”
ON
ON
ON
ON
“0”
OFF
OFF
OFF
OFF
Table 8.11.2
Function turned on
1. Entire built-in power circuit is turned on
2. Other than the secondary booster and step-down circuits
3. External power supply alone
D3
1
1
0
D2
1
0
0
D1
1
1
0
D0 External power input pins
1
–
1
V3, MV3
0 V3, V2, VC, MV1, MV 3
8.11.2 Voltage Transform Circuit
The charge pump booster circuit and the operational amplifier’s voltage follower generate each potential required to
drive the liquid crystal based on the reference voltage generated by the voltage regulator.
Ground potentials (abbreviated as GND in the following description) of the power circuit in the IC are GND2 and
GND4.
Fig. 8.11.1 illustrates mutual relationship between potentials.
Primary
boorster circuit
Secondary
boorster circuit
VCLS
V3
V2
V2 V1, VC, MV1,
generation circuit
V1
VC
VDD2
MV1
MV2
GND
Secondary
boorster circuit
MV3
Fig. 8.11.1 Mutual Relationship between Voltage Transform Circuits
26
EPSON
Rev. 1.0
S1D15G00 Series
Table 8.11.3 shows the theoretical expression of respective potentials. Since these are theoretical values, they can differ
from actual voltages depending on load on the liquid crystal.
Table 8.11.3 Theoretical Expression of Potentials
Signal name
V3
V2
V1
VC
MV1
GND(MV2)
MV3
Theoretical expression
(relative to GND = 0V)
2×(V2 –GND)
Output from voltage regulator
3/4×(V2–GND)
2/3×(V2–GND)
1/3×(V2–GND)
0V
–(V2–GND)
Theoretical expression
(relative to V C = 0V)
2×(VC–GND)
VC–GND
1/2×(VC–GND)
0V
–1/2×(VC–GND)
–(VC–GND)
–2×(VC–GND)
8.11.3 Primary Booster Circuit
The built-in booster circuit triples the voltage of VDD2-GND.
VDD2-GND voltage is tripled by capacitor C connected across CAP1+ and CAP1,CAP2+ and CAP2- as well as VCSL
and GND (or VDD2), and then output at V CSL pin.
In the case of double boosting, short circuit the CAP2+ and VCSL pin.
Fig. 8.11.2 shows how the voltage is stepped up by the capacitors connected.
VCSL=3xVDD2
GND or VDD2
GND or VDD2
C
C
+
VCSL
+
CAP2—
VCLS
VCLS=2xVDD2
CAP2—
C
+
CAP2+
CAP1—
C
+
CAP2+
VDD2
CAP1—
C
CAP1+
+
VDD2
CAP1+
GND
GND
Fig. 8.11.2 Relation between Capacitors and Voltage Step-up
8.11.4 Voltage Regulator Circuit
The voltage regulator circuit generates the liquid crystal drive voltage V2 using VCSL from the primary booster circuit.
S1D15G00 incorporates the high-precision constant voltage source, 64-step electronic volume control function and
resistor to regulate V2 voltage. The voltage regulator circuit covers a wider temperature range with fewer numbers of
parts thanks to the temperature gradient control function as well as the temperature sensing function.
However, capacitors may be required for voltage regulation between V2 and GND pins due to the load of LCD panel.
Insert the capacitors, if necessary, by observing the voltage waveforms and current consumption.
1 Built-in Resistor for V2 Voltage Regulation
The contents described in this document apply only to models that use a V2 voltage control resistor inside the IC.
Using this resistor and the electronic volume control function allows you to control the liquid crystal drive voltage V2
to an optimum level for the LCD panel with the command alone, without resorting to external resistors.
V2 output voltage can be determined from Equation A-1 as long as the relation V 2 < VCSL is met.
However, set the voltage of V2 by allowing for a drop in the voltage due to load, so that it becomes at or below 80 %
of VCSL.
Rb 
Rb   α + 2 
V 2 = 1 +
• VEV = 1 +
• 1–
• VREG (Equation A-1)
 Ra 
 Ra  
218 
Note: VREG is the constant voltage source inside the IC. It is 1.2V (Typ.) at Ta = 25°C.
Rev. 1.0
EPSON
27
S1D15G00 Series
VCSL
VEV (Constant voltage source +
Electronic volume controller)
V2
Built-in Rb
Built-in Ra
GND
Fig. 8.11.3 Voltage Regulator Circuit
Rb/Ra in Equation A-1 is the resistance ratio of the built-in V2 voltage-regulating resistance. This ratio can be varied
in 8 levels by changing parameters 2(P2) of electronic volum control command. Reference ratios of “1 + Rb/Ra” are
shown in Table 8.11.4.
Table 8.11.4 Resistance Ratio of Built-in V2 Voltage-Regulating Resistance: Parameters and “1+
R/Ra” Ratio (For reference)
Parameter
P22 P21 P20
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1+Rb/Ra ratio
V1 voltage value
3.95
4.27
4.60
4.93
5.26
5.59
5.92
6.25
Small
•
•
•
•
Large
2V2 voltage control external resistor
The contents described in this document apply only to models that use an external V2 voltage control resistor.
If you use an external resistance control model, you can set the V2 voltage using an external resistor.
Use a semi-fixed resistor for V2 voltage regulation.
VCSL
VEV
(Fixed voltage source and
Electronic volume control)
+
V2
V2
–
External resistor Rb
VR
External resistor Ra
GND
GND
Fig. 8.11.4 Voltage Regulator Circuit
Select the external Ra and Rb values to allow stable voltage supply by observing the V2 voltage waveforms.
As the VR pin has a high input impedance and it is susceptible to ambient noise, the resistors and their leads must be
placed in a short distance and they must be away from the clock source.
3Constant Voltage Source and Electronic Volume Control Circuit
The constant voltage source generates VREG - the reference voltage inside the IC. You can specify one of four types
of temperature gradients with parameters of electronic volum control command. See Fig. 8.11.5.
28
EPSON
Rev. 1.0
S1D15G00 Series
Table 8.11.5 Parameters and VREG Temperature Gradient
Parameter Temperature gradient (%/C)
0
0
–0.05
0
1
–0.1
1
0
–0.15
1
1
–0.2
The electronic volume control circuit varies α in Equation A-1 according to parameters 1(P1) of electronic volum
control command. Table 8.11.6 lists relation between the parameters and α.
Table 8.11.6 Parameters and Electronic Volume
Parameter
α
P15 P14 P13 P12 P11 P10
0
0
0
0
0
0
63
0
0
0
0
0
1
62
0
0
0
0
1
0
61
•
•
•
•
•
•
1
1
1
1
0
1
2
1
1
1
1
1
0
1
1
1
1
1
1
1
0
V1 voltage value
Small
•
•
•
Large
8.11.5 Voltage Divider/Voltage Follower Circuit
The voltage divider/voltage follower circuit V2 output from the voltage regulator circuit and then generates liquid
crystal drive voltages V1, VC and MV1 using the operational amplifier-featured voltage follower.
Capacitors may be required for voltage regulation between the GND and each of V1 , VC and MV1 pins due to the load
of LCD panel. Insert the capacitors, if necessary, by observing the voltage waveforms and current consumption.
V1 = 3/4×V2
VC = 2/4×V2
MV1 = 1/4×V2
8.11.6 Secondary Booster Circuit and Tertiary Booster/Step-Down Circuit
The secondary booster circuit boosts or steps down based on V2 and produces V 3 and MV3.
Their potential relationship is expressed with the following theoretical equation:
V3 = 2×V2
MV3 = –V2
8.11.7 Samples of Connections Peripheral to Power Circuit (For your information)
Following illustrates the connections when the entire power circuit is used.
C1
C1
+
+
CAP1+
CAP1–
CAP2+
CAP2–
Sample of common setting
VDD2
+
VCSL
C1
2
C2
2
Item
C1
C2
GND
C1
C1
+
+
Rev. 1.0
CAP4+
CAP4–
CAP5+
CAP5–
V3
V2
V1
VC
MV1
MV3
+
Setting
1.0 to 4.7
0.47 to 1.0
Unit
µF
Optimum values of C1 and C2 above vary
depending on the LCD panel to be driven.
Above values should be referenced as
information only. It is recommended to
check how patterns with high load are
displayed before finalizing the values.
C between VDD2 and GND signifies a
bias capacitor.
+
EPSON
29
S1D15G00 Series
9. COMMANDS
9.1 Command List
Following table lists the control signals and commands using the 80 series interface as the example.
Command
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
Hex Parameter
1 DISON
0
1
0
1
0
1
0
1
1
1
1
Display on
AF
None
2 DISOFF
0
1
0
1
0
1
0
1
1
1
0
Display off
AE
None
3 DISNOR
0
1
0
1
0
1
0
0
1
1
0
Normal display
A6
None
4 DISINV
0
1
0
1
0
1
0
0
1
1
1
Inverse display
A7
None
5 COMSCN 0
1
0
1
0
1
1
1
0
1
1
Common scan direction
BB
1byte
6 DISCTL
0
1
0
1
1
0
0
1
0
1
0
Display control
CA
3byte
7 SLPIN
0
1
0
1
0
0
1
0
1
0
1
Sleep in
95
None
8 SLPOUT
0
1
0
1
0
0
1
0
1
0
0
Sleep out
94
None
9 PASET
0
1
0
0
1
1
1
0
1
0
1
Page address set
75
2byte
10 CASET
0
1
0
0
0
0
1
0
1
0
1
Column address set
15
2byte
11 DATCTL
0
1
0
1
0
1
1
1
1
0
0
Data scan direction, etc.
BC
3byte
12 RGBSET8 0
1
0
1
1
0
0
1
1
1
0
256-color position set
CE
20byte
13 RAMWR
0
1
0
0
1
0
1
1
1
0
0
Writing to memory
5C
Data
14 RAMRD
0
1
0
0
1
0
1
1
1
0
1
Reading from memory
5D
Data
15 PTLIN
0
1
0
1
0
1
0
1
0
0
0
Partial display in
A8
2byte
16 PTLOUT
0
1
0
1
0
1
0
1
0
0
1
Partial display out
A9
None
17 RMWIN
0
1
0
1
1
1
0
0
0
0
0
Read and modify write
E0
None
18 RMWOUT 0
1
0
1
1
1
0
1
1
1
0
End
EE
None
19 ASCSET
0
1
0
1
0
1
0
1
0
1
0
Area scroll set
AA
4byte
20 SCSTART 0
1
0
1
0
1
0
1
0
1
1
Scroll start set
AB
1byte
21 OSCON
0
1
0
1
1
0
1
0
0
0
1
Internal oscillation on
D1
None
22 OSCOFF
0
1
0
1
1
0
1
0
0
1
0
Internal oscillation off
D2
None
23 PWRCTR
0
1
0
0
0
1
0
0
0
0
0
Power control
20
1byte
24 VOLCTR
0
1
0
1
0
0
0
0
0
0
1
Electronic volume control
81
2byte
25 VOLUP
0
1
0
1
1
0
1
0
1
1
0
Increment electronic control by 1 D6
None
26 VOLDOWN 0
1
0
1
1
0
1
0
1
1
1
Decrement electronic control by 1 D7
None
27 TMPGRD
0
1
0
1
0
0
0
0
0
1
0
Temperature gradient set
82
1 byte
28 EPCTIN
0
1
0
1
1
0
0
1
1
0
1
Control EEPROM
CD
1 byte
29 EPCOUT
0
1
0
1
1
0
0
1
1
0
0
Cancel EEPROM control
CC
None
30 EPMWR
0
1
0
1
1
1
1
1
1
0
0
Write into EEPROM
FC
None
31 EPMRD
0
1
0
1
1
1
1
1
1
0
1
Read from EEPROM
FD
None
32 EPSRRD1 0
1
0
0
1
1
1
1
1
0
0
Read register 1
7C
None
33 EPSRRD2 0
1
0
0
1
1
1
1
1
0
1
Read register 2
7D
None
34 NOP
0
1
0
0
0
1
0
0
1
0
1
NOP instruction
25
None
35 STREAD
0
0
1
30
Status
Status read
EPSON
Rev. 1.0
S1D15G00 Series
(1) Display ON (DISON) Command: 1 Parameter: None
It is used to turn the display on. When the display is turned on, segment outputs and common outputs are generated
at the level corresponding to the display data and display timing. You can’t turn on the display as long as the sleep mode
is selected. Thus, whenever using this command, you must cancel the sleep mode first.
Command
A0
0
RD WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
1
(2) Display OFF (DISOFF) Command: 1 Parameter: 0
It is used to forcibly turn the display off. As long as the display is turned off, every segment and common outputs are
forced to VC level and DOFF pin is caused to LOW.
Command
A0
0
RD WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
(3) Normal display (DISNOR) Command: 1 Parameter: 0
It is used to normally highlight the display area without modifying contents of the display data RAM.
Command
A0
0
RD WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
1
D0
0
(4) Inverse display (DISINV) Command: 1 Parameter: 0
It is used to inversely highlight the display area without modifying contents of the display data RAM. This command
does not invert non-display areas in case of using partial display.
Command
A0
0
RD WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
1
D0
1
(5) Common scan (COMSCAN) Command: 1 Parameter: 1
It is used to specify the common output scan direction. This command helps increasing degrees of freedom of wiring
on the LCD panel.
A0
Command
0
Parameter1 (P1) 1
RD WR
1
0
1
0
D7
1
*
D6
0
*
D5
1
*
D4
1
*
D3 D2 D1 D0
1
0
1
1
* P12 P11 P10
Function
Common scan direction
When 1/160 is selected for the display duty, pins and common output are scanned in the order shown below.
P12
P11
P10
0
0
0
0
0
0
1
1
0
1
0
1
Rev. 1.0
COM1 pin
1
1
80
80
→
→
←
←
Common scan direction
COM80 pin COM81 pin
80
81
80
160
1
81
1
160
EPSON
→
←
→
←
COM160 pin
160
81
160
81
31
S1D15G00 Series
(6) Display control (DISCTL) Command: 1 Parameter: 3
This command and succeeding parameters are used to perform the display timing-related setups. This command must
be selected before using SLPOUT. Don’t change this command while the display is turned on.
D4 D3 D2 D1 D0
Function
0
1
0
1
0
* P13 P12 P11 P10 CL dividing ratio, F1 and
F2 drive pattern.
Parameter2 (P2) 1
1
0
*
* P25 P24 P23 P22 P21 P20 Drive duty
Parameter3 (P3) 1
1
0
*
*
*
1 P33 P32 P31 P30 FR inverse-set value
*: Invalid bits irrelevant to the operation.
Command
Parameter1 (P1)
A0
0
1
RD WR
1
0
1
0
D7
1
*
D6
1
*
D5
0
*
P1: It is used to specify the CL dividing ratio, F1 and F2 drive-pattern switching period.
P13, P12: CL dividing ratio. They are used to change number of dividing stages of external or internal clock.
P13
0
0
1
1
P12
0
1
0
1
CL dividing ratio
2 divisions (default)
4 divisions
8 divisions
Not divide
P11, P10: They are used to change F1 and F2 drive-pattern switching period.
P11
0
0
1
1
P10
0
1
0
1
F1, F2 switching period
8H (default)
4H
16H
Field
P2: It is used to specify the duty of the module on block basis.
Duty
Example: 1/128 duty
Example: 1/160 duty
*
0
0
*
0
0
P25 P24 P23 P22 P21 P20
0
1
1
1
1
1
1
0
0
1
1
1
(Numbers of display lines)/4-1
128/4–1=31
160/4–1=39
P3: It is used to specify number of lines to be inversely highlighted on LCD panel (lines can be inversely highlighted
in the range of 2 to 16)
Inversely highlighted lines
Example: 11H
Example: 13H
*
0
0
*
0
0
P25 P24 P23 P22 P21 P20
0
0
1
0
1
0
0
0
1
1
0
0
Inversely highlighted lines –1
11–1=10
13–1=12
In the default, 11H inverse highlight is selected.
(7) Seep in (SLPIN) Command: 1 Parameter: 0
Entering this command generates LOW at SLP pin.
Command
A0
0
RD WR
1
0
D7
1
D6
0
D5
0
D4
1
D3
0
D2
1
D1
0
D0
1
DOFF (LCD panel blanking control pin) on S1D15G00 is caused to LOW when the sleep in mode is turned on.
The LCD power supply and the boost circuit output is jumpered with GND during Sleep In.
32
EPSON
Rev. 1.0
S1D15G00 Series
(8) Sleep out (SLPOUT) Command: 1 Parameter: 0
Entering this command generates HIGH at SLP pin.
Command
A0
0
RD WR
1
0
D7
1
D6
0
D5
0
D4
1
D3
0
D2
1
D1
0
D0
0
(9) Page address set (PASET) Command: 1 Parameter: 2
When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the
page address area. As the addresses are incremented from the start to the end page in the page-direction scan, the column
address is incremented by 1 and the page address is returned to the start page. Note that the start and end page must
be specified as a pair. Also, the relation “start page < end page” must be maintained.
A0
Command
0
Parameter1 (P1) 1
Parameter2 (P2) 1
RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
1
0
1
0
1
1
0 P17 P16 P15 P14 P13 P12 P11 P10
1
0 P27 P26 P25 P24 P23 P22 P21 P20
Function
Start page
End page
(10) Column address set (CASET) Command: 1 Parameter: 2
When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the
column address area. As the addresses are incremented from the start to the end column in the column-direction scan,
the page address is incremented by 1 and the column address is returned to the start column. Note that the start and end
page must be specified as a pair. Also, the relation “start column < end column” must be maintained.
A0
Command
0
Parameter1 (P1) 1
Parameter2 (P2) 1
RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
1
0
1
0
1
1
0 P17 P16 P15 P14 P13 P12 P11 P10
1
0 P27 P26 P25 P24 P23 P22 P21 P20
Function
Start address
End address
* Note that in the 8- and16-bit access, or 8 and 16 gray-scale, a different approach is employed for specifying the address.
Rev. 1.0
EPSON
33
S1D15G00 Series
(11) Data control (DATCTL) Command: 1 Parameters: 2
This command and succeeding parameters are used to perform various setups needed when MPU operates display data
stored on the built-in RAM.
A0
Command
0
Parameter1 (P1) 1
Parameter2 (P2)
Parameter3 (P3)
1
1
RD WR
1
0
1
0
1
1
0
0
D7
1
*
D6
0
*
D5
1
*
D4
1
*
*
*
*
*
*
*
*
*
D3 D2 D1 D0
Function
1
1
0
0
* P12 P11 P10 Normal/inverse display of page
address and page-address
scan direction.
* P22 P21 P20 RGB arrangement
* P32 P31 P30 Gray-scale setup
P1: It is used to specify the normal or inverse display of the page address and also to specify the page address scanning
direction.
P10: Normal/inverse display of the page address. P10 = 0: Normal and P10 = “1”: Inverse.
P11: Normal/reverse turn of column address. P11 = “0”: Normal rotation and P11 = “1”: Reverse rotation
P12: Address-scan direction. P12 = “0”: In the column direction and P12 = “1”: In the page direction.
P2: RGB arrangement. This parameter allows you to change RGB arrangement of the segment output according to RGB
arrangement on the LCD panel. In this case, writing position of data {R = (D7, D6, D5), G = (D4, D3, D2), B =
(D1, D0)} on the display memory is changed.
P22,P21,P20
line
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
•••
SEG395
000
Even page
Odd page
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
•••
•••
B
B
001
1
2
B
B
G
G
R
R
B
B
G
G
R
R
B
B
G
G
•••
•••
R
R
010
1
2
R
R
G
G
B
B
B
B
G
G
R
R
R
R
G
G
•••
•••
R
R
011
1
2
B
B
G
G
R
R
R
R
G
G
B
B
B
B
G
G
•••
•••
B
B
100
1
2
R
B
G
G
B
R
R
B
G
G
B
R
R
B
G
G
•••
•••
B
R
101
1
2
B
R
G
G
R
B
B
R
G
G
R
B
B
R
G
G
•••
•••
R
B
110
1
2
R
B
G
G
B
R
B
R
G
G
R
B
R
B
G
G
•••
•••
R
B
111
1
2
B
R
G
G
R
B
R
B
G
G
B
R
B
R
G
G
•••
•••
B
R
In the default, (P22, P21, P20) = (0, 0, 0) is selected.
P3: Gray-scale setup. Using this parameter, you can a select desired display colors between the 256 colors (8 gray-scale)
or 4096 colors (16 gray-scale) for the display color. For 16 gray-scale display, you can select the Type-A or Type-B
display mode depending on the difference in RGB data arrangement you use.
P32 P31 P30
Numbers of gray-scale
0
0
1
8 gray-scale
0
1
0
16 gray-scale display
34
EPSON
Rev. 1.0
S1D15G00 Series
(12) 256-color position set (RGBSET8) Command: 1 Parameter: 0
When turning on 256-color display (8 gray-scale), this command allows you to choose colors to represent each of red,
green and blue from 4096 colors.
Command
Parameter1 (P1)
A0
0
1
RD WR
1
0
1
0
D7
1
*
D6
1
*
D5
0
*
Parameter4 (P8)
Parameter9 (P9)
1
1
1
1
Parameter16 (P16)
Parameter17 (P17)
1
1
Parameter20 (P20)
1
D4 D3 D2 D1 D0
Function
0
1
1
1
0
* P13 P12 P11 P10 Intermediate red tone 000
0
0
*
*
*
*
*
*
*
*
P83 P82 P81 P80 Intermediate red tone 111
P93 P92 P91 P90 Intermediate green tone 000
1
1
0
0
*
*
*
*
*
*
*
*
P163 P162 P161 P160 Intermediate green tone 111
P173 P172 P171 P170 Intermediate blue tone 00
1
0
*
*
*
*
P203 P202 P201 P200 Intermediate blue tone 11
Data (Red and Green: 3 bits and Blue: 2 bits) to be written from the MPU to the DDRAM are converted to 4-bit data
before the write operation takes place. When reading data from the DDRAM, data on red and green are converted to
3 bits and that on blue are converted to 2 bits before the output.
(13) Memory write (RAMWR) Command: 1 Parameter: Numbers of data written
When MPU writes data to the display memory, this command turns on the data entry mode. Entering this command
always sets the page and column addresses at the start address. You can rewrite contents of the display data RAM by
entering data succeeding to this command. At the same time, this operation increments the page or column address as
applicable. The write mode is automatically cancelled if any other command is entered.
1 8-bit bus
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
Command
0
1
0
0
1
0
1
1
1
0
0
Parameter 1
1
0
Data to be written
Data to be written
2 16-bit bus
Command name A0 RD WRD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Command 0 1 0 * * * * * * * * 0 1 0 1 1 1 0 0
Data to be written 1 1 0
Data to be written
Function
Memory write
Write data
(14) Memory read (RAMRD) Command: 1 Parameter: Numbers of data read
When MPU reads data from the display memory, this command turns on the data read mode. Entering this command
always sets the page and column addresses at the start address. After entering this command, you can read contents of
the display data RAM. At the same time, this operation increments the page or column address as applicable. The data
read mode is automatically cancelled if any other command is entered.
1 8-bit bus
Command
Parameter
A0
0
1
RD WR
1
0
0
1
D7
0
D6
1
D5 D4 D3 D2
0
1
1
1
Data to be read
D1
0
D0
1
Function
Data to be read
2 16-bit bus
Command name A0 RD WRD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Command 0 1 0 * * * * * * * * 0 1 0 1 1 1 0 1
Data to be read 1 0 1
Data to be read
Rev. 1.0
EPSON
Function
Memory read
Read data
35
S1D15G00 Series
(15) Partial in (PTLIN) Command: 1 Parameter: 2
This command and succeeding parameters specify the partial display area. This command is used to turn on partial
display of the screen (dividing screen by lines) in order to save power. Since S1D15G00 processes the liquid crystal
display signals on 4-line basis (block basis), the display and non-display areas are also specified on 4-bit line (block
basis).
A0
Command
0
Parameter1 (P1) 1
Parameter2 (P2) 1
RD WR
1
0
1
0
1
0
D7
1
*
*
D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0
0
* P15 P14 P13 P12 P11 P10
* P25 P24 P23 P22 P21 P20
Function
Start block address
End block address
*: Invalid bits irrelevant with the operation.
A block address that can be specified for the partial display must be the displayed one (don’t try to specify an address
not to be displayed when scrolled).
When the partial display mode is turned on, following state is introduced to S1D15G00 in the non-display area:
* LOW is output to DOFF pin.
* All COM pins output VC.
* All SEG pins output V1 or MV1.
SEG output is forced to V1 or MV1 depending on state of FR in the last display line. When FR is HIGH, V1 is output
and when FR is LOW, MV1 is output. Phase of FR is constantly reversed at start of a frame.
(16) Partial out (PTLOUT) Command: 1 Parameter: 0
This command is used to exit from the partial display mode.
Command
A0
0
RD WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
1
(17) Read modify write in (RMWIN) Command: 1 Parameter: 0
This command is used along with the column address set command, page address set command and read modify write
out command. This function is used when frequently modifying data to specify a specific display area such as blinking
cursor. First set a specific display area using the column and page address commands. Then, enter this command to
set the column and page addresses at the start address of the specific area. When this operation is complete, the column
(page) address won’t be modified by the display data read command. It is incremented only when the display data write
command is used. You can cancel this mode by entering the read modify write out or any other command.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Page address set
No
Column address set
Is modification
complete?
Yes
Read modify write in
Read modify write out
Dummy read
Data read
Data write
36
EPSON
Rev. 1.0
S1D15G00 Series
(18) Read modify write out (RMWOUT) Command: 1 Parameter: 0
Entering this command cancels the read modify write mode.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
(19) Area scroll set (ASCSET) Command: 1 Parameter: 4
It is used when scrolling only the specified portion of the screen (dividing the screen by lines). This command and
succeeding parameters specify the type of area scroll, FIX area and scroll area.
Command
Parameter1 (P1)
Parameter2 (P2)
Parameter3 (P3)
Parameter4 (P4)
A0
0
1
1
1
1
RD WR
1
0
1
0
1
0
1
0
1
0
D7
1
*
*
*
*
D6 D5 D4 D3
0
1
0
1
* P15 P14 P13
* P25 P24 P23
* P35 P34 P33
*
*
*
*
D2
0
P12
P22
P32
*
D1
1
P11
P21
P31
P41
D0
0
P10
P20
P30
P40
Function
Top block address
Bottom block address
Number of specified blocks
Area scroll mode
*: Invalid bits irrelevant with the operation.
P4: It is used to specify an area scroll mode.
P41
0
0
1
1
P40
0
1
0
1
Types of area scroll
Center screen scroll
Top screen scroll
Bottom screen scroll
Whole screen scroll
Center screen scroll
: Fixed area
Top screen scroll
Bottom screen scroll
Whole screen scroll
: Scroll area
Since S1D15G00 processes the liquid crystal display signals on the four-line basis (block basis), FIX and scroll areas
are also specified on the four-line basis (block basis).
DDRAM address corresponding to the top FIX area is set in the block address incrementing direction starting with 0
block. DDRAM address corresponding to the bottom FIX area is set in the block address decreasing direction starting
with 41st block. Other DDRAM blocks excluding the top and bottom FIX areas are assigned to the scroll + background
areas.
P1: It is used to specify the top block address of the scroll + background areas. Specify the 0th block for the top screen
scroll or whole screen scroll.
The scroll start block address is also set at this top block address until the scroll-start block set command specifies
the address.
P2: It specifies the bottom address of the scroll + background areas. Specify the 41st block for the bottom or whole
screen scroll.
Required relation between the start and end blocks (start block < end block) must be maintained.
P3: It specifies a specific number of blocks {Numbers of (Top FIX area + Scroll area) blocks - 1}. When the bottom
scroll or whole screen scroll, the value is identical with P2.
You can turn on the area scroll function by executing the area scroll set command first and then specifying the display
start block of the scroll area with the scroll start set command.
Rev. 1.0
EPSON
37
S1D15G00 Series
[Area Scroll Setup Example]
In the center screen scroll of 1/128 duty (display range: 128 lines = 32 blocks), if 8 lines = 2 blocks and 8 lines = 2 blocks
are specified for the top and bottom FIX areas, 112 lines = 28 blocks is specified for the scroll areas, respectively, 40
lines = 10 blocks on the DDRAM are usable as the background area. Value of each parameter at this time is as shown
below.
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
P1 1
1
0
*
*
0
0
0
0
1
0 Top block address = 2
P2 1
1
0
*
*
1
0
0
1
1
1 Bottom block address = 39
P3 1
1
0
*
*
0
1
1
1
0
1 Number of specific blocks = 29
P4 1
1
0
*
*
*
*
*
*
0
0 Area scroll mode = Center
*: Invalid bits irrelevant to the operations.
(20) Scroll start address set (SCSTART) Command: 1 Parameter: 1
This command and succeeding parameter are used to specify the start block address of the scroll area. Note that you
must execute this command after executing the area scroll set command. Scroll becomes available by dynamically
changing the start block address.
Command
Parameter1 (P1)
A0
0
1
RD WR
1
0
1
0
D7
1
*
D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
1
* P15 P14 P13 P12 P11 P10
Function
Start block address
*: Invalid bits irrelevant to the operations.
(21) Internal oscillation on (OSCON) Command: 1 Parameter: 0
This command turns on the internal oscillation circuit. It is valid only when the internal oscillation circuit of CLS =
HIGH is used.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
0
D0
1
(22) Internal oscillation off (OSOFF) Command: 1 Parameter: 0
It turns off the internal oscillation circuit. This circuit is turned off in the reset mode.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
1
D0
0
(23) Power control set (PWRCTR) Command: 1 Parameter: 1
This command is used to turn on or off the liquid crystal driving power circuit, booster/step-down circuits and voltage
follower circuit.
A0
Command
0
Parameter1 (P1) 1
RD WR
1
0
1
0
D7
0
*
D6
0
*
D5
1
*
D4 D3 D2 D1 D0
0
0
0
0
0
* P13 P12 P11 P10
Function
LCD drive power
*: Invalid bits irrelevant to the operations.
P10: It turns on or off the Reference voltage generation circuit.
P10 = “1”: ON. P10 = “0”: OFF.
P11: It turns on or off the voltage regulator and circuit voltage follower.
P11 = “1”: ON. P11 = “0”: OFF.
Note: 2 bits of P10 and P11 must be turned on or off simultaneously.
P12: It turns on or off the secondary booster/step-down circuit.
P12 = “1”: ON. P12 = “0”: OFF.
P13: It turns on the primary booster circuit.
38
EPSON
Rev. 1.0
S1D15G00 Series
(24) Electronic volume control (VOLCTR) Command: 1 Parameter: 2
This command is used to specify the voltage regulator circuit’s electronic volume value α and resistance ratio of builtin voltage regulating resistor.
A0
Command
0
Parameter1 (P1) 1
Parameter2 (P2) 1
RD WR
1
0
1
0
1
0
D7
1
*
*
D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
* P15 P14 P13 P12 P11 P10
*
*
*
* P22 P21 P20
Function
V1 volume value α
1 + Rb/Ra
*: Invalid bits irrelevant to the operations.
P1: It is used to specify V2 electronic volume value.
P2: It specifies resistance ratio of the internal resistor.
(25) Increment Electronic Control (VOLUP) Command: 1 Parameter: No
This command increments Electronic Control value α of voltage regulator circuit by 1.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
0
D4
1
D3
0
D2
1
D1
1
D0
0
If you set the Electronic Control value to 111111, the control value is set to 000000 after this command has been
executed.
(26) Decrement Electronic Control (VOLDOWN) Command: 1 Parameter: No
This command decrements Electronic Control value α of voltage regulator circuit by 1.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
0
D4
1
D3
0
D2
1
D1
1
D0
1
If you set the Electronic Control value to 000000, the control value is set to 111111 after this command has been
executed.
(27) Temperature gradient set (TMPGRD) Command: 1 Parameter: 5
This command is used to specify the average temperature gradient of liquid crystal drive voltage as well as the correction
value β of the electronic volume value at the predetermined 10 temperature levels.
Command
Parameter1 (P1)
A0
0
1
P11
0
0
1
1
RD WR
1
0
1
0
P10
0
1
0
1
D7
1
*
D6
0
*
D5
0
*
D4
0
*
D3
0
*
D2 D1 D0
Function
0
1
0
* P11 P10 Average temperature gradien
Average temperature gradient [%/°C]
–0.05
–0.1
–0.15
–0.2
(28) Control EEPROM (EPCTIN) Command: 1 Parameter: 1
This command with its parameter selects the EEPROM (S1F65170) Control mode. The parameter can be set to either
Write or Read.
Command
Parameter1 (P1)
A0
0
1
RD WR
1
0
1
0
D7
1
*
D6
1
*
D5
0
P5
D4
0
*
D3
1
*
D2
1
*
D1
0
*
D0
1
*
Function
Selects Write or Read.
* Invalid bit; it is ignored during operation.
P5: Specifies data writing into or reading from the EEPROM (S1F65170) as follows.
If P5=0: Read; if P5=1: Write
Rev. 1.0
EPSON
39
S1D15G00 Series
(29) Cancel EEPROM Control (EPCOUT) Command: 1 Parameter: 0
This command cancels the EEPROM (S1F65170) Control mode. If data is read from the EEPROM, both of Electronic
Control value and built-in resistance ratio are updated by the read data.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
0
D4
0
D3
1
D2
1
D1
0
D0
0
(30) Write Into EEPROM (EPMWR) Command: 1 Parameter: 0
This command writes the Electronic Control value and built-in resistance ratio into the EEPROM (S1F65170).
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
0
D0
0
(31) Read From EEPROM (EPMRD) Command: 1 Parameter: 0
This command reads the Electronic Control value and built-in resistance ratio from the EEPROM (S1F65170), and
temporarily stores them in S1D15G00 registers.
Command
A0
0
RD WR
1
0
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
0
D0
1
(32) Read Register 1 (EPSRRD1) Command: 1 Parameter: 0
Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the Electronic Control value.
Command
A0
0
RD WR
1
0
D7
0
D6
1
D5
1
D4
1
D3
1
D2
1
D1
0
D0
0
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the
STREAD (Status Read) command.
(33) Read Register 1 (EPSRRD2) Command: 1 Parameter: 0
Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the built-in resistance ratio.
Command
A0
0
RD WR
1
0
D7
0
D6
1
D5
1
D4
1
D3
1
D2
1
D1
0
D0
1
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the
STREAD (Status Read) command.
(34) Non-operating (NOP) Command: 1 Parameter: 0
This command does not affect the operation.
Command
A0
0
RD WR
1
0
D7
0
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
This command, however, has the function of canceling the IC test mode. Thus, it is recommended to enter it periodically
to prevent malfunctioning due to noise and such.
40
EPSON
Rev. 1.0
S1D15G00 Series
(35) Status read (STREAD)
It is the command for the IC chip test. Don’t try to use this command.
Command
A0
0
RD WR
0
1
D7
D6
D5 D4 D3
Status data
D2
D1
D0
1 Status after reset or after NOP operation
D7: Area scroll mode
Refer to P37 (ASCSET).
D6: Area scroll mode
Refer to P37 (ASCSET).
D5: Read modify write
0: In
1: Out
D4: Scan direction
0: Page
1: Column
D3: Display ON/OFF
0: OFF
1: ON
D2: EEPROM access
0: Out of access 1: In access
D1: Display normal/inverse
0: Inverse
1: Normal
D0: Partial display
0: OFF
1: ON
2 Status after EPSRRD1 operation
D7, D6: Undefined (1 or 0)
D5 to D0: Electronic volume control values
3 Status after EPSRRD2 operation
D7 to D3: Undefined (1 or 0)
D2 to D0: Built-in resistance ratio
Rev. 1.0
EPSON
41
S1D15G00 Series
10. ABSOLUTE MAXIMUM RATING
Item
Symbol
Rating
Unit
Source voltage (1)
VDD ,VDD2
–0.3 to 4.0
V
Input source voltage
VDDI
–0.3 to 4.0
V
Source voltage (2)
V3,VOUT
–0.3 to 25.0
V
V2,V1,VC
–0.3 to V3
MV1
–0.3 to VDD2
MV3
–10.0 to +0.5
Input voltage
VIN
–0.3 to VDDI+0.5
V
Output voltage
VO
–0.3 to VDDI+0.5
V
Operating temperature
Topr
–40 to +85
°C
Tstr
–65 to +150
°C
Source voltage (3)
Storage
temperature
Bare chip
V
Potential Relation
V3
VOUT
VDD2,
VDD
VCC
VDDI
GND
GND
V2
V1, VC, MV1
MV2
MV3
System (MPU) side
S1D15G00 side
Notes: 1. Voltages are all indicated relevant to GND = 0V.
2. Voltage of V 3, V 2, V 1, V C, MV1 , MV2 (GND) and MV 3 must constantly meets the requirement V3 ≥
V2 ≥V1 ≥VC≥MV1≥MV2 (GND) ≥MV3.
3. VDD and VOUT1 voltages must constantly meets the requirement V OUT1≥VDD.
4. If LSI is operated beyond the absolute maximum rating, it can be damaged permanently. Normal operating
conditions should conform to the electric characteristics of LSI, otherwise malfunctioning of LSI can result
in addition to deterioration of its reliability.
5. Definition of VDD is applicable to VDD3, VDD4 and V DD5 pins.
6. Definition of GND is applicable to GND2, GND3 and GND4 pins.
42
EPSON
Rev. 1.0
S1D15G00 Series
11. ELECTRIC CHARACTERISTICS
11.1 DC Characteristics
Except where otherwise specified, GND = 0V, VDD = 2.75V, VDDI = 1.8V and Ta = 20°C to 85°C.
Table 11.1
Item
Symbol
Condition
Standard value
Min.
Typ.
Max.
Unit Applicable
pin
Operating Operable
voltage (1)
Operating Operable
voltage (2)
Operating Operable
VDD
2.6
2.75
3.6
V
VDD *1
VDDI
1.7
1.8
VDD
V
VDDI
12.0
–
21.0
V
V3
voltage (3) Operable
V3
8.0
–
14.0
V
V3
Operable
V2
4.0
–
7.0
V
V2
Operable
V1
3.0
–
5.3
V
V1
Operable
VC
2.0
–
3.5
V
VC
Operable
MV1
1.0
–
1.8
V
MV1
Operable
MV2
GND
–
GND
V
MV2
Operable
MV3
–7.0
–
–4.0
V
MV3
VIHC
0.8×VDDI
–
VDDI
V
*2
0.7×VDDI
–
VDDI
V
*3
0.0
–
0.2×VDDI
V
*2
0.0
–
0.3×VDDI
V
*3
High level input voltage
Low level input voltage
V3
V3 to MV3
VILC
High level output voltage
VOH
IOH=–0.6mA
VDDI–0.4
–
VDDI
V
*4
Low level output voltage
VOL
IOL=+0.6mA
0.0
–
0.4
V
*4
–
–
1.0
µA
*3
–
–
1.0
µA
*4
Input leak current
ILI
Output leak current
ILO
VIN=VDDI or GND
Liquid crystal drive
RONseg V2=5.0V, ∆V=0.5V
–
3.5
10
kΩ
SEGn *5
ON resistance
RONcom V3=16.0V, ∆V=0.5V
–
0.4
1.0
kΩ
COMn *5
Static current consumption
Dynamic current consumption
IDDQ
VDD=VDDI=3.6V,Ta=25°C
–
2
10
µA
VDD
I3Q
I2Q
V3–MV3=18.0V,Ta=25°C
V2=6.0V,Ta=25°C
–
–
–
–
1.5
3.0
µA
µA
V3
V2
IDD
During RAM access 3MHz
–
1200
1600
µA
VDD +VDDI
During display
Frame frequency 130Hz
–
500
800
µA
VDD
*8
During display
Frame frequency 180Hz
During display
–
600
900
µA
–
5
20
µA
VDD
*8
VDDI
VDDI
Input terminal capacity
CI
Freq.=1MHz
–
–
15
pF
*3
Output terminal capacity
CO
Ta=25°C, Elemental chip
–
–
15
pF
*4
Oscillated
Internal
fOSC
130Hz device
39.6
41.6
43.7
kHz
*6
frequency
oscillation
180Hz device
54.7
57.6
60.5
S1D15G00D10*000
29.6
31.2
32.8
130Hz device, 1/160duty
–
41.6
–
kHz
CL *6
180Hz device, 1/160duty
–
57.6
–
S1D15G00D10*000
–
31.2
–
External
input
Rev. 1.0
fCL
EPSON
43
S1D15G00 Series
Table 11.2
Built-in power supply circuit
Item
Symbol
Input voltage to primary
booster circuit
Output voltage from
primary booster circuit
Primary booster circuit
output impedance
Reference voltage
Condition
VDD2
VOUT
Unit Applicable
pin
2.6
–
3.6
V
VDD
7.8
–
10.8
V
VOUT
Triple boosting,
no load
Triple boosting,
VDD=2.7V, C=2.2µF
Ta=25°C
–
2600
–
Ω
VOUT
1.16
1.20
1.24
V
*7
no load
4.0
–
7.0
V
V2
V3
8.0
–
14.0
V
V3
MV3
–7.0
–
–4.0
V
MV3
Rout
VREG
Voltage adjusting
circuit output voltage
Secondary boosting
output voltage
Secondary step-down
output voltage
Standard value
Min.
Typ.
Max.
V2
Static current consumption: While the display is in operation and the built-in power supply is turned on.
Current consumed by total IC including the built-in power supply.
1200
Horizontal stripe per 4 dots
1000
IDD [µA]
800
Display RAM all "0"
600
400
200
0
4
5
6
7
8
V2 voltage [V]
Condition: VDD = 2.75V, VDDI = 1.8V, frame frequency 130Hz
During display, built-in power supply and built-in oscillation circuit on, built-in power supply triple
boosting voltage
Typical value when Ta = 25°C
Fig. 11.1 Dynamic current consumption (During display, liquid crystal drive voltage dependent)
44
EPSON
Rev. 1.0
S1D15G00 Series
1400
1200
Horizontal stripe per 4 dots
IDD [µA]
1000
800
600
Display RAM all "0"
400
200
0
50
100
150
200
250
Frame frequency [Hz]
Condition: VDD = 2.75V, VDDI = 1.8V, V2 = 6.0V
During display, built-in power supply and built-in oscillation circuit on, built-in power supply triple
boosting voltage
Typical value when Ta = 25°C
Fig. 11.2 Dynamic current consumption (During display, frame frequency dependent)
Table 11.3 Current Consumption in Power Save Mode GND = 0V, V DD = VDDI = 1.8V, V DD = 2.75V and Ta = 25°C.
Item
Symbol
Condition
Standard value
Min.
Typ.
Max.
IDDS
Sleep mode
–
1.0
10.0
Unit Applicable
pin
µA
VDD, VDDI
4000
IDD [µA]
3000
2000
1000
0
1
2
3
4
5
6
7
8
9
10
Cycle time [MHz]
Condition: VDD = VDDI = 3.0V, built-in power supply and built-in oscillation circuit off
Fig. 11.3 Dynamic current consumption (During display RAM access)
Rev. 1.0
EPSON
45
S1D15G00 Series
Table 11.4 Relation between Oscillated Frequency fOSC, Display Clock Frequency fCL and Frame
Frequency of Liquid Crystal
Item
When built-in oscillation circuit is used
When built-in oscillation circuit
is not used
fCL
41.6kHz (Typ.) *1
57.6kHz (Typ.) *2
31.2kHz (Typ.) *3
External input (fCL)
fFR
fCL/Dividing ratio
2 × Display duty
fCL/Dividing ratio
2 × Display duty
*1: When 130Hz frame frequency device is used.
*2: When 180Hz frame frequency device is used.
*3: When S1D15G00D01*000 is used.
fFR represents cycle of framing, not cycle of FR signal.
Dividing ratio and display duty are set with the display control command.
DC Characteristics - Supplementary Description
*1: Operation is warranted if radical voltage fluctuations occur while MPU is in the process of access.
*2: This applies only to RES.
*3: D15 to D0 (Input mode)
SI, SCL IF1 to IF3, A0, CS, RD (E), WR (R/W), RES, M/S and CLS.
*4: D15 to D0 (Input and Output mode)
CL, FR SYNC, CA, F1, F2 and DOFF.
*5: It represents the resistance value when 0.5V is applied across the output pin SEGn or COMn and respective power
terminals (V3, V2, V1, VC, MV1 and MV2). It is specified within the range of the operating voltage (3).
RON = 0.5V/∆I (∆I is the current conducted when 0.5V is applied across the power supply and output pin).
*6: For the relation between oscillated frequency and frame frequency, refer to Table 11.4. The standard value listed
in relation to the external input is a recommended value.
*7: This is the reference voltage source built into the IC. It is not output to the pin.
*8: It indicates the current consumed by the IC alone when the built-in oscillation circuit is in operation and the display
is turned on. Condition: display RAM all “0”, V2 = 6.0V, triple boosting voltage, no access to the MPU. It does
not include current consumed by the LCD panel capacity and wiring capacity.
46
EPSON
Rev. 1.0
S1D15G00 Series
11.2 AC Characteristics
System Bus
Read/write characteristics I (80 series MPU)
A0
tAW8
tAH8
CS
*1
tCCLW, tCCLR
tCW8
tCCHW, tCCHR
WR, RD
CS
*2
tCYC, tCYC2
WR, RD
D0 to D7
(Read)
tDH8
tDS8
D0 to D7
(Write)
tACC8
tOH8
*1 is when access is made with WR and RD when CS is LOW.
*2 is when access is made with CS when WR and RD are LOW.
Ta=–40 to +85°C, VDD=2.6 to 3.6V, VDDI=2.6 to VDD
Min.
Max.
Unit Measuring conditions
and others
Signal
Symbol
Parameter
A0
tAH8
tAW8
Address hold time
Address setup time
10
0
–
–
ns
ns
–
WR,
RD,CS
tCYC
tCYC2
tCCHW
tCCHR
tCCLW
tCCLR
tCW8
Write cycle
Read cycle
Control pulse HIGH width (write)
Control pulse HIGH width (read)
Control pulse LOW width (write)
Control pulse LOW width (read)
CS–WR, RD time
130
250
90
70
30
170
30
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
–
D0 to D7
tDS8
tDH8
Data setup time
Data hold time
10
20
–
–
ns
ns
–
tACC8
tOH8
Read access time
Output disable time
–
5
170
60
ns
ns
CL=10 to 100pF
* Rise and fall time of input signal (t r, tf) must be 15 ns maximum.
* All timings must be specified using 30% and 70% of VDD-GND as the reference.
* tCCLW and tCCLR are specified by the duration during which CS as well as WR and RD are LOW.
* A0 timing is specified by the duration during which CS as well as WR and RD are LOW.
Rev. 1.0
EPSON
47
S1D15G00 Series
Ta=–40 to +85°C, VDD=2.6 to 3.6V, VDDI=1.7 to 2.6V
Min.
Max.
Unit Measuring conditions
and others
Signal
Symbol
Parameter
A0
tAH8
tAW8
Address hold time
Address setup time
10
0
–
–
ns
ns
–
WR,
RD,CS
tCYC
tCYC2
tCCHW
tCCHR
tCCLW
tCCLR
tCW8
Write cycle
Read cycle
Control pulse HIGH width (write)
Control pulse HIGH width (read)
Control pulse LOW width (write)
Control pulse LOW width (read)
CS–WR, RD time
130
300
90
90
30
200
30
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
–
D0 to D7
tDS8
tDH8
Data setup time
Data hold time
10
20
–
–
ns
ns
–
tACC8
tOH8
Read access time
Output disable time
–
5
200
60
ns
ns
CL=10 to 100pF
* Rise and fall time of input signal (t r, tf) must be 15 ns maximum.
* All timings must be specified using 30% and 70% of VDD-GND as the reference.
* tCCLW and tCCLR are specified by the duration during which CS as well as WR and RD are LOW.
* A0 timing is specified by the duration during which CS as well as WR and RD are LOW.
48
EPSON
Rev. 1.0
S1D15G00 Series
* Read/write characteristics II (68 series MPU)
A0, R/W
tAW6
tAH6
CS
tCCHW, tCCHR
*1
tCW6
tCCLW, tCCLR
E
CS
tCYC, tCYC2
*2
E
tDS6
D0 to D7
(Write)
D0 to D7
(Read)
tDH6
tACC6
tOH6
* 1 is when access is made with E when CS is LOW.
* 2 is when access is made with CS when E is LOW.
Ta =–40 to +85°C, V DD=2.6 to 3.6V, VDDI=2.6 to VDD
Min.
Max.
Unit Measuring conditions
and others
Signal
Symbol
Parameter
A0, R/W
tAH6
tAW6
Address hold time
Address setup time
10
0
–
–
ns
ns
–
E, CS
tCYC
tCYC2
tCCLW
tCCLR
tCCHW
tCCHR
tCW6
Write cycle
Read cycle
Control pulse LOW width (write)
Control pulse LOW width (read)
Control pulse HIGH width (write)
Control pulse HIGH width (read)
CS–E time
130
250
90
70
30
170
30
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
–
D0 to D7
tDS6
tDH6
Data setup time
Data hold time
10
20
–
–
ns
ns
–
tACC6
tOH6
Read access time
Output disable time
–
5
170
60
ns
ns
CL=10 to 100pF
* Rise and fall time of input signal (tr, tf) must be 15 ns maximum.
* All timings must be specified using 30% and 70% of VDD–VSS as the reference.
* tCCHW and tCCHR are specified by the duration during which CS is LOW and E is HIGH.
* A0 and R/W timings are specified by the duration during which CS is LOW and E is HIGH.
Rev. 1.0
EPSON
49
S1D15G00 Series
Ta =–40 to +85°C, VDD=2.6 to 3.6V, VDDI=1.7 to 2.6V
Min.
Max.
Unit Measuring conditions
and others
Signal
Symbol
Parameter
A0, R/W
tAH6
tAW6
Address hold time
Address setup time
10
0
–
–
ns
ns
–
E, CS
tCYC
tCYC2
tCCLW
tCCLR
tCCHW
tCCHR
tCW6
Write cycle
Read cycle
Control pulse LOW width (write)
Control pulse LOW width (read)
Control pulse HIGH width (write)
Control pulse HIGH width (read)
CS–E time
130
280
90
70
30
200
30
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
–
D0 to D7
tDS6
tDH6
Data setup time
Data hold time
10
20
–
–
ns
ns
–
tACC6
tOH6
Read access time
Output disable time
–
5
200
60
ns
ns
CL=10 to 100pF
* Rise and fall time of input signal (tr, tf) must be 15 ns maximum.
* All timings must be specified using 30% and 70% of VDD–VSS as the reference.
* tCCHW and tCCHR are specified by the duration during which CS is LOW and E is HIGH.
* A0 and R/W timings are specified by the duration during which CS is LOW and E is HIGH.
50
EPSON
Rev. 1.0
S1D15G00 Series
* Reset timing
tRW
RES
tRT
Internal control
Reset in operation
Normal operation
Ta =–40 to +85°C, V DD=2.6 to 3.6V, VDDI=1.7 to VDD
Signal
Symbol
Parameter
Min.
Max.
Unit
RES
tRW
Reset pulse width
350
–
ns
tRT
Reset cancel
350
–
ns
Measuring conditions
and others
Rise and fall time of input signal (tr, tf) must be 15 ns maximum.
All timings must be specified using 20% and 80% of VDD–VSS as the reference.
Rev. 1.0
EPSON
51
S1D15G00 Series
* Serial input characteristics
tCSS
tCSH
CS
tSAS
tSAH
A0
tSCYC
tSHW
tSLW
SCL
tf
tSDS
tr
tSDH
SI
Ta =–40 to +85°C, V DD=2.6 to 3.6V, VDDI=1.7 to VDD
Min.
Max.
Unit Measuring conditions
and others
Signal
Symbol
Parameter
CS
tCSS
tCSH
CS setup time
CS hold time
10
30
–
–
ns
ns
A0
*3
tSAS
tSAH
Address setup time
Address hold time
90
20
–
–
ns
ns
SCL
tSCYC
tSLW
tSHW
Clock cycle
LOW width
HIGH width
50
15
15
–
–
–
ns
ns
ns
SI
tSDS
tSDH
Data setup time
Data hold time
10
10
–
–
ns
ns
*1, *2
* 1: Rise and fall time of every input signal (tr , tf ) must be 15 ns maximum.
* 2: All timings must be specified using 30% and 70% of VDDI as the reference.
* 3: tSAS and tSAH are applicable to the 8-bit serial interface alone.
52
EPSON
Rev. 1.0
S1D15G00 Series
12. MPU INTERFACES (EXAMPLES FOR YOUR REFERENCE)
S1D15G00 series can be directly connected to 80 series and 68 series MPU. Using a serial interface allows you to
operate S1D15G00 series with fewer signal lines. In addition to interfaces (1) to (3) given below, using IF1 to IF3 pins
enables to employ the 16-bit interface and 9-bit serial interface.
When initialization with RES is complete, make sure that input pins of S1D15G00 series are correctly controlled.
(1) 80 series MPU – 8-bit interface
VDD
VCC
VDD
A0
A1 to A7
IORQ
MPU
A0
CS
Decoder
D0 to D7
D0 to D7
RD
RD
WR
WR
RES
RES
GND
S1D15G00
IF1
IF2
IF3
VSS
RESET
VSS
(2) 68 series MPU – 8-bit interface
VDD
VCC
VDD
A0
A1 to A15
VMA
MPU
A0
CS
Decoder
D0 to D7
S1D15G00
D0 to D7
E
IF1
IF2
IF3
E
R/W
R/W
RES
RES
VSS
GND
RESET
VSS
(3) 8-bit serial interface
VDD
VCC
A0
A0 to A7
VDD
A0
CS
Decoder
S1D15G00
MPU
GND
Port1
SI
Port2
SCL
RES
RES
IF1
IF2
IF3
VSS
RESET
VSS
Rev. 1.0
EPSON
53
S1D15G00 Series
12.1 Software Setup Examples
12.1.1 When Power is Turned On
Input power (VDDI, VDD).
Be sure to apply POWER-ON RESET (RES = LOW)
<Display Setting>
Display control (DISCTL)
Setting clock dividing ratio and F1/F2 drive selection:
Duty setting:
Setting reverse rotation number of line:
Common scan direction (COMSCN)
Setting scan direction:
2 dividing, 8 h
1/4
11h reverse rotations
Oscillation ON (OSCON)
Oscillation OFF
Sleep-out (SLIPOUT)
Sleep-in
<Power Supply Setting>
Electronic volume control (VOLCTR)
Setting volume value a :
Setting built-in resistance value :
Temperature gradient set (TMPGRD)
Setting mean temperature gradient :
Power control (PWRCTR)
Setting operation of power supply circuit:
<<State after resetting>>
<Display Setting 2>
Normal rotation of display (DISNOR)/Inversion of display (DISINV):
Partial-in (PTLIN)/Partial-out (PTLOUT)
Setting fix area:
Area scroll set (ASSET)
Setting area scroll region:
Setting area scroll type:
Scroll start set (SCSTART)
Setting scroll start address:
<<State after resetting>>
COM1 -> COM80, COM80 -> COM160
0
0 (3.95)
0 (-0.05%/°C)
All OFF
<Display Setting 3>
Data control (DATCTL)
Setting normal rotation/inversion of page address:
Setting normal rotation/inversion of column address:
Setting direction of address scanner:
Setting RGB arrangement:
Setting gradation:
256-color position set (RGBSET8)
Setting color position at 256-color
54
<<State after resetting>>
EPSON
Partial-out
0
0
Full-screen scroll
0
<<State after resetting>>
Normal rotation
Normal rotation
Column direction
RGB
8 gradations
All 0
Rev. 1.0
S1D15G00 Series
<RAM Setting>
Page address set (PASET)
Setting start page address:
Setting end page address:
Column address set (CASET)
Setting start column address:
Setting end column address:
<<State after resetting>>
0
0
0
0
<RAM Write>
Memory write command (RAMWR)
Writing displayed data:
<<State after resetting>>
Repeat as many as the number needed and exit by
entering other command.
<Waiting (approximately 100ms)>
Wait until the power supply voltage has stabilized.
Enter the power supply control command first, then wait at least
100ms before entering the display ON command when the built-in
power supply circuit operates.
If you do not wait, an unwanted display may appear on the
liquid crystal panel.
Display ON (DISON):
Display OFF
*1: When the IC is in Sleep In state, the liquid crystal drive power supply and the boosting power output and GND pin
are jumpered, therefore, the Sleep Out command must be entered to cancel the Sleep state prior to turning on the
built-in circuit.
(Note) If changes are unnecessary after resetting, command input is unnecessary.
Rev. 1.0
EPSON
55
S1D15G00 Series
12.2.2 Command Input Procedure During Power Off
•When power-on reset is not used
<< IC status>>
Display off (DISOFF): display is turned off, and all of the common and segment pins become VC potential.
Liquid crystal drive power supply circuit off (PWRCTR): built-in power supply circuit stops.
Oscillation off (OSCOFF): built-in oscillation circuit stops and all the circuits inside the IC also stop.
Sleep In (SLPIN) *2
Stop the power supply (VDDI, VDD).
*2: In order to discharge the capacitor connected to the liquid crystal drive power supply circuit, execute the Sleep In
command to put the IC in Sleep state prior to stopping the power supply. Stop VDDI and VDD when the output of
the liquid crystal drive power supply circuit has dropped sufficiently.
•When power-on reset is used
Turn on the power-on reset (RES = LOW) *3
Stop the power supply (VDDI , VDD).
*3: Stop VDDI and VDD when the output of the liquid crystal drive power supply circuit has dropped sufficiently.
(Note)
This IC is the logic circuit of the VDD-GND and VDDI-GND power supplies, and it controls the liquid crystal output
driver. If the VDDI-GND and VDD-GND power supplies are stopped with residual voltage in the liquid crystal drive
power supply circuit, the liquid crystal output driver (COM, SEG) may output uncontrolled voltage. Stop VDDI and
VDD when the output of the liquid crystal drive power supply circuit has dropped sufficiently.
12.2.3 Sleep state
This IC goes into Sleep state when the Sleep In command and several other commands are executed. When in the Sleep
state, IC power consumption will be kept to a minimum. Also, internal status including the display RAM will be
maintained, the Sleep Out and several commands will resume the display state.
•Setting the Sleep state
<< IC status>>
1 Display off (DISOFF): display is turned off, and all the common segment and pins become VC potential.
2 Liquid crystal drive power supply circuit off (PWRCTR): built-in power supply circuit stops.
3 Oscillation off (OSCOFF): built-in oscillation circuit stops and all the circuits inside the IC also stop.
Sleep In (SLPIN): commands other than 1 to 3 and display RAM content are maintained. Commands can be entered.
•Releasing the Sleep state
<<IC status>>
Sleep Out (SLPOUT)
Oscillation on (OSCON): built-in power supply circuit operates and liquid crystal drive potential is supplied.
Wait (approx. 100ms): wait until liquid crystal drive power supply boots and stabilizes. Wait until the power supply
voltage stabilizes.
Display on (DISON): display comes on and the display RAM content is output.
56
EPSON
Rev. 1.0
S1D15G00 Series
12.2.4 Refresh Sequence
Refreshing of the state setup is recommended by reentering the command parameters and the display data in order to
recover from improper IC operations due to such reasons as noise.
Reconfigure the following commands and parameters.
Common scan direction (COMSCN)
Oscillation on (OSCON)
Sleep Out (SLPOUT)
Electronic volume control (VOLCTR)
Temperature gradient (TMPGRD)
Power supply control (PWRCTR)
Normal (DISNOR)/Inverted display (DISINV)
Partial in (PTLIN)/Partial out (PTLOUT)
Area scroll set (ASCSET)
Scroll start set (SCSTART)
Data control (DATCTL)
256-color position set (RGBSET8)
NOP instruction (NOP) *1
Page address set (PASET)
Column address set (CASET)
Memory write command (RAMWR): display data write
Display on (DISON)
*1: IC shipment inspection test state can be escaped with NOP instruction. Add this to the refresh sequence.
If display control (DISCTL) is reconfigured during display, noise may occur on the display, so omit this from the refresh
sequence. Reconfigure with the display off.
Rev. 1.0
EPSON
57
S1D15G00 Series
13. PERIPHERAL CONNECTION EXAMPLES
13.1 When EEPROM is used
In the following example, the S1D15G00D00B100 chip is used and the following parameters are set.
Power voltages: VDDI=1.8 V, VDD=2.7 V
Interface: 8-bit parallel interface
Primary boosting: 3 times
Clock: The built-in oscillator circuit is used.
V2 voltages: Set by the peripheral EEPROM
Capacitors: A bypass capacitor is used between VDD and GND pins. A voltage regulator capacitor is used between GND
and each of V2, V1, VC and MV1 pins.
Connect them by observing the current consumption and voltage waveforms.
S1D15G00D00B100
Connected to V3R
Connected to V2R
Connected to V1R
Connected to VCR
Connected to MV1R
Connected to MV3R
+ +
+
+ +
+
1.8V
2.7V
Signals to/from
S1F65170
CS
A0
D0 to D7
Signals from MPU
RD
WR
RES
Connected to MV3L
Connected to MV1L
Connected to VCL
Connected to V1L
Connected to V2L
Connected to V3L
V3L
V2L
V1L
VCL
VCLSL
MV1L
MV3L
TESTA
TESTB
TESTC
TESTD
TESTE
TESTF
TESTG
CAP2+
CAP2–
CAP1+
CAP1–
GND2
GND3
GND
VDD3
VDD4
VDD
VDDI
FR
YSCL
F1
F2
DOFF
CA
SYNC
SLP
SDA
RESET
CLOCK
TEST1
GND
VDDI
CL
CLS
GND
VDDI
CS
A0
GND
VDDI
SCL
S1
GND
VDDI
D0 to D7
GND
VDDI
D8 to D15
GND
VDDI
RD
WR
GND
VDDI
IF1
IF2
IF3
GND
VDDI
RES
TESTH
M/S
VDDI
GND
GND4
VDD
VDD5
VDD2
CAP4+
CAP4–
CAP5+
CAP5–
MV3R
MV1R
VCLSR/VR
VCR
V1R
V2R
V3R
COM160
·
·
·
COM81
SEG1
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
SEG396
LCD Panel
132 RGB × 160 dots
COM80
·
·
·
COM1
+
+
58
EPSON
Rev. 1.0
S1D15G00 Series
13.2 When peripheral split resistor is used
In the following example, the S1D15G00D01B100 chip is used and the following parameters are set.
Power voltages: VDDI=1.8 V, VDD=2.7 V
Interface: 8-bit parallel interface
Primary boosting: 3 times
Clock: The built-in oscillator circuit is used.
V2 voltages: Set by external split resistors
Capacitors: A bypass capacitor is used between VDD and GND pins. A voltage regulator capacitor is used between GND
and each of V2, V1, VC and MV1 pins.
Connect them by observing the current consumption and voltage waveforms.
S1D15G00D01B100
Connected to V3R
Connected to V2R
Connected to V1R
Connected to VCR
Connected to MV1R
Connected to MV3R
+ +
+
+ +
+
1.8V
2.7V
CS
A0
D0 to D7
Signals from MPU
RD
WR
RES
Connected to MV3L
Connected to MV1L
Connected to VCL
Connected to V1L
Connected to V2L
Connected to V3L
V3L
V2L
V1L
VCL
VCLSL
MV1L
MV3L
TESTA
TESTB
TESTC
TESTD
TESTE
TESTF
TESTG
CAP2+
CAP2–
CAP1+
CAP1–
GND2
GND3
GND
VDD3
VDD4
VDD
VDDI
FR
YSCL
F1
F2
DOFF
CA
SYNC
SLP
SDA
RESET
CLOCK
TEST1
GND
VDDI
CL
CLS
GND
VDDI
CS
A0
GND
VDDI
SCL
S1
GND
VDDI
D0 to D7
GND
VDDI
D8 to D15
GND
VDDI
RD
WR
GND
VDDI
IF1
IF2
IF3
GND
VDDI
RES
TESTH
M/S
VDDI
GND
GND4
VDD
VDD5
VDD2
CAP4+
CAP4–
CAP5+
CAP5–
MV3R
MV1R
VCLSR/VR
VCR
V1R
V2R
V3R
COM160
·
·
·
COM81
SEG1
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
SEG396
LCD Panel
132 RGB ´ 160 dots
COM80
·
·
·
COM1
+
+
Rev. 1.0
EPSON
59
S1D15G00 Series
14. EEPROM INTERFACE
The S1D15G00D00* 100 and S1D15G00D05* 100
series chips provide the Write and Read functions to
write the Electronic Control value and built-in resistance
ratio into and read them from the peripheral EEPROM
(S1F65170). Using the Write and Read functions, you
can store these values appropriate to each LCP panel.
Notes: As the EPCTIN, EPCWR and EPCRD
commands require the following processing
times, use a software timer or insert a process
to loop the operation by monitoring the status
read value of D2 (Access to EEPROM). If
these times are insufficient, the Read or Write
operation may fail.
14.1 Conditions when EEPROM read/write
is performed
1 EPCTIN
5
(sec)
fosc / 4
1 The built-in oscillator circuit is already operating.
2 The CL division by 2 and 160 display lines have
been set by the Display Control command.
2 EPCWR
10
(sec)
fosc / 320
3 EPCRD
10
(sec)
fosc / 4
14.2 EEPROM writing instructions
1. Issue the VOLCTR command to set the appropriate
Electronic Control value and built-in resistance
ratio.
2. Issue the EPCTIN command to select the Control
EEPROM mode (for data writing).
3. Issue the EPMWR command to write data into the
EEPROM.
4. Issue the EPCTOUT command to cancel the
EEPROM Control mode.
14.4 Connection example
S1D15G00 and S1F65170 connection example.
VDD for both chips is connected to the same potential.
14.3 EEPROM data reading instructions
1. Issue the EPCTIN command to select the EEPROM
Control mode (for data reading).
2. Issue the EPMRD command to read data from the
EEPROM.
3. Issue the EPCTOUT command to cancel the
EEPROM Control mode and updates the Electronic
Control value and built-in resistance ratio using the
read data.
Miscellaneous:
The MPU can read the Electronic Control value and
built-in resistance ratio by issuing a combination of
EPSRRD1 or EPSRRD2 and STREAD (Status Read)
commands.
60
VDD
GND
SDA
CLOCK
RESET
VDD
GND
SDA
SCK
XRST
S1F65170M0A00
S1D15G00D00B100
EPSON
Rev. 1.0
S1D15G00 Series
15. CAUTIONS
Concerning this development specification, users are
advised to pay attention to the following precautions.
1. This development specification is subject to
modifications without previous notice.
2. This development specification does not grant the
industrial property right or any other right, or
exercising such rights.
Application examples contained in this document are
intended only to help users to understand the product
better. SEIKO EPSON shall not be liable to any circuitrelated problem resulted from using these examples.
Users are requested to pay attention to the following
points when using S1D15G00 series.
Precautions on Light
Characteristics of semiconductor devices can be changed
when exposed to light as described in the operational
principles of solar batteries. Exposing this IC to light,
therefore, can potentially lead to its malfunctioning.
1 Care must be exercised in designing the operation
system and mounting the IC so that it may not be
exposed light during operation
2 Care must be exercised in designing the inspection
process and handling the IC so that it may not be
exposed to light during the process.
3 The IC must be shielded from light in the front, back
and side faces.
Rev. 1.0
Precautions on External Noises
1 Internal state of S1D15G00 can be changed when
exposed to adversely affecting external factors such
as excessive noises though it can maintain the
command-instructed operational status and display
data. Thus, you must make sure when mounting the
IC and designing the operation system that measures
for eliminating noises or measures protecting the IC
from noises are prepared.
2 In order to be prepared against sudden noise, it is
recommended to prepare the software to perform
periodic refreshing of operational state (re-setting
of commands and re-transfer of display data).
Precautions on Mounting COG
When mounting COG, you must take into consideration
of resistance component generated across the driver
chip and externally connected parts (capacitor and
resistor) resulting from ITO wiring. This resistance
component can interfere with high-speed operation of
liquid crystal display or MPU.
When mounting COG, you must take into consideration
of the following three points in the module design:
1. To minimize resistance between the driver chip pin
to the external part.
2. To minimize resistance at the power terminal of the
driver chip.
3. To develop sample COG modules with varying
degrees of ITO sheet resistance in order to select
one with the sheet resistance allowing sufficient
operational margins.
EPSON
61