M52957AFP
Distance Detection Signal Processing for 3V Supply Voltage
REJ03F0069-0100Z
Rev.1.0
Sep.19.2003
Description
M52957AFP is a semiconductor integrated circuit containing distance detection signal processing circuit for 3V supply
voltage.
This device transforms each optical inflow current I1 and I2 from PSD SENSOR into the voltage, and integrates that
output after doing calculation corresponds to I1/(I1+I2), and outputs it as the time data(pulse term).
Features
• Wide supply voltage range Vcc=2.2 to 5.5V
• Includes clamp level switching circuit
(Switch is 16 kinds by outside control)
• Includes STANDBY function
• Includes POWER ON RESET function
Application
Auto focus control for the CAMERA
Sensor for short distance etc
Recommended Operating Condition
Rated supply voltage • • • • • • • • • • • • • • • 3.0V
Supply voltage • • • • • • • • • • • • • • • 2.2 to 5.5V
Rev.1.0, Sep.19.2003, page 1 of 13
M52957AFP
Pin Configuration
1
16
PSDF
CHN
2
15
CHF
Vcc
3
14
GND1
13
(TESTF)
NC
12
GND2
11
CLALV
HOLD
M52957AFP
PSDN
(TESTN)
NC
4
STB
5
CINT
6
RESET
7
10
SOUT
8
9
Outline
INT
16P2E
Note: pin4,13 is connected only engineering sample
Block Diagram
Vcc
NC
CINT
3
4
6
TESTN
CHN 2
PSDN 1
PULSE WIDTH
TRANSFORM
(DOUBLE INTEGRATION)
I1
I/V
TRANSFORM
AMP
STATIONARY
LIGHT
REMOVE
BIAS
RECKON
I1
I1+I2
HOLD
HOLD
REFERENCE
VOLTAGE
I2
PSDF 16
STATIONARY
LIGHT
REMOVE
I/V
TRANSFORM
AMP
CLAMP
CIRCUIT
CLAMP LEVEL
SWITCHING
CHF 15
14
12
GND1 GND2
Note: pin4,13 is connected only engineering sample
Rev.1.0, Sep.19.2003, page 2 of 13
11
CLALV
13 NC
HOLD
TESTF
SEQUENTIAL CONTROL LOGIC
5
7
9
10
8
STB RESET INT HOLD SOUT
M52957AFP
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted.)
Parameter
Symbol
Ratings
Unit
Remark
Supply voltage
VCC
7.0
V
note 1
Power dissipation
Thermal derating
Pd
Kθ
320
−3.2
mW
mW/°C
Ta=25°C
Ta≥25°C
Pin supply voltage
Another pin supply voltage
VIF
VI/O
7.0
−0.3 to VCC + 0.3
V
V
Pin5, 7, 8, 9, 10, 11
note 2
Output pin inflow current
Operating temperature
Isout
Topr
0.5
−10 to 50
mA
°C
NPN open collector
Storage temperature
Tstg
−40 to 125
°C
Notes : 1. As a principle, do not provide a supply voltage reversely.
2. As a principle, do not provide the terminals with the voltage over supply voltage or under ground voltage.
Rev.1.0, Sep.19.2003, page 3 of 13
M52957AFP
Electrical characteristics
(Ta = 25°C, VCC = 5.0V, unless otherwise noted.)
Limits
Classification
Consuming
current
HOLD pin
INT pin
CLALV
pin
RESET
pin
STB
pin
HOLD
C
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating supply voltage
range
Usual consuming current
VCC
2.2
3.0
5.5
V
ICC1
5.9
7.7
mA
While Rapid charge
consuming current 1
ICC2
17.7
23.0
mA
While Rapid charge
consuming current 2
ICC3
19.0
24.7
mA
While STAND BY
consuming current
HOLD "H" input voltage
ICC4
1.0
µA
VHOH
1.1
7.0
V
HOLD "L" input current
HOLD "H" input current
VHOL
IHOH
0
0.3
1.0
V
µA
HOLD "L" input voltage
INT "H" input voltage
IHOL
VINH
−100
1.1
−75
−50
7.0
µA
V
INT "L" input voltage
INT "H" input current
VINL
IINH
0
0.3
1.0
V
µA
INT "L" input current
CLALV "H" input voltage
IINL
VCLH
−100
1.1
−75
−50
7.0
µA
V
CLALV "L" input voltage
CLALV "H" input current
VCLL
ICLH
0
0.3
1.0
V
µA
CLALV "L" input current
RESET "H" input voltage
ICLL
VREH
−100
1.1
−75
−50
7.0
µA
V
RESET "L" input voltage
RESET "H" input current
VREL
IREH
0
0.3
1.0
V
µA
RESET "L" input current
STB "H" input voltage
IREL
VSTH
−100
VCC−0.3
−75
−50
7.0
µA
V
STB "L" input voltage
STB "H" input current
VSTL
ISTH
0
0.3
3.0
V
µA
STB "L" input current
CH rapid charge current
ISTL
ICHQC
−150
−2000
−100
−1000
−50
−500
µA
µA
VIL=0V
IPSD=5µA ,
VCH=0V
*1
CH stationary charge
current
CH stationary discharge
current
ICHC
−30
−20
−10
µA
VCH=0V
*1
ICHD
10
20
30
µA
VCH=1.5V
*1
Rev.1.0, Sep.19.2003, page 4 of 13
Test conditions
Note
While CH rapid
charge consuming
current
While CH and
CINT rapid charge
consuming current
*1
*1
*1
VIH=5.5V
VIL=0V
VIH=5.5V
VIL=0V
VIH=5.5V
VIL=0V
VIH=5.5V
VIL=0V
VIH=5.5V
M52957AFP
Electrical characteristics (cont.)
(Ta = 25°C, VCC = 3.0V, unless otherwise noted.)
Limits
Classification
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test conditions
Note
Double
integration
CINT rapid charge
current
CINT reference voltage
ICINTC
84
120
156
µA
*1
VCINT
1.6
1.8
2.0
V
VCI=1V
(CINT stable period)
GND criterion
*1
The first integration
current
The second integration
current
ICI1
4.06
5.80
7.54
µA
VCINT=1.5V
*1
ICI2
−3.20
−2.46
−1.27
µA
VCHF=2V ,
VCHN=0V
*1
The first integration
current stability
percentage
The second integration
current stability
percentage
∆ICI1
10
%
*2
∆ICI2
10
%
*2
The first and second
integration current ratio
AF output time(9:1)-1
ICI12
2.12
2.36
2.60
D(9:1) - 1
11.78
13.40
15.02
msec
Near side9 : Far side1
*3
AF output time(6:4)-1
AF output time(3:7)-1
D(6:4) - 1
D(3:7) - 1
7.77
3.77
8.95
4.51
10.13
5.25
msec
msec
Near side6 : Far side4
Near side3 : Far side7
*3
*3
AF slope -1
AF linearity-1
∆AF - 1
LAF - 1
6.57
0.9
8.89
1.0
11.21
1.1
msec
AF output time(9:1)-2
AF output time(6:4)-2
D(9:1) - 2
D(6:4) - 2
11.78
7.77
13.40
8.95
15.02
10.13
msec
msec
Near side9 : Far side1
Near side6 : Far side4
*3
*3
AF output time(3:7)-2
AF slope -2
D(3:7) - 2
∆AF - 2
3.77
6.57
4.51
8.89
5.25
11.21
msec
msec
Near side3 : Far side7
*3
*3
AF linearity-2
AF output time(9:1)-3
LAF - 2
D(9:1) - 3
0.9
11.78
1.0
13.40
1.1
15.02
msec
Near side9 : Far side1
*3
*3
AF output time(6:4)-3
AF output time(3:7)-3
D(6:4) - 3
D(3:7) - 3
7.77
3.77
8.95
4.51
10.13
5.25
msec
msec
Near side6 : Far side4
Near side3 : Far side7
*3
*3
AF slope -3
AF linearity-3
∆AF - 3
LAF - 3
6.57
0.9
8.89
1.0
11.21
1.1
msec
∆AF output time(9:1)
∆D(9:1)
280
µsec
∆AF output time(6:4)
∆D(6:4)
280
µsec
∆AF output time(3:7)
∆D(3:7)
280
µsec
SOUT leak current
ISOUTL
1.0
µA
Near side3 : Far side7
(Condition 1-2)
VIN = 5.5V
SOUT saturation
voltage
Signal light saturation
current
VSOUTS
0.3
V
IOUT=500µA
∆INF
3.0
µA
*4
Stationary light remove
current
Clamp level
IPSD
30
µA
*4
ICLAM
−30
30
%
AF input
condition 1
AF input
condition 2
AF input
condition 3
AF input
condition
1 minus 2
Data
Sensor
Rev.1.0, Sep.19.2003, page 5 of 13
| ICI1 | / | ICI2 |
*3
*3
*3
*3
Near side9 : Far side1
(Condition 1-2)
Near side6 : Far side4
(Condition 1-2)
Change quantity for
Typ. current
M52957AFP
• *1 : Set up the logic control terminal, correspond to the parameter.
• *2 : Change ratio between the first integration current and the second integration current at a voltage of CINT that
is {CINT reference voltage(VCINT)-0.1V} and 1V.
∆I CI 1=( 1 ∆I CI 2=( 1 -
The first integration current (CINT=1V)
) X 100%
The first integration current (CINT=VCINT-0.1V)
The second integration current (CINT=1V)
) X 100%
The second integration current (CINT=VCINT-0.1V)
• *3 : Connect the resistance of 120ΚΩ instead of PSD and establish current output from PHOTO COUPLER
correspond to the parameter. And input the varied resistance ratio. And measure the pulse width of SOUT output at
that time, obtain AFslope and AF linearity from the equations below.
Input condition1: IPSD (Stationary light current)=0 I1+I2=100nA
Input condition2: IPSD (Stationary light current)=0 I1+I2=50nA
Input condition3: IPSD (Stationary light current)=10µA I1+I2=100nA
D(9 : 1) • • • The pulse width of SOUT output at input with I1:I2=9:1
D(6 : 4) • • • The pulse width of SOUT output at input with I1:I2=6:4
D(3 : 7) • • • The pulse width of SOUT output at input with I1:I2=3:7
AF slope : DAF = D(9 : 1) - D(7 : 3)
AF linearity : L(AF) = (D(9 : 1) - D(6 : 4)) / (D(6 : 4) - D(7 : 3))
PSD quite resistance : 120KΩ
• *4 : The input current of one side channel when stationary light remove circuit and I/V transform AMP is not
saturated.
Rev.1.0, Sep.19.2003, page 6 of 13
M52957AFP
Description of Pin
Limits
Pin name
Circuit diagram
Unit
Parameter
Min. Typ. Max.
HOLD
INT
CLALV
RESET
"H"input
voltage
"L"input
voltage
1.1
Test
conditions
and note
7.0
V
0
"H"input
current
0.3
VIH=5.5V
1.0
µA
"L"input
current
"H"input
voltage
-100 -75
-50
VCC
-0.3
7.0
VIL=0V
V
"L"input
voltage
0
0.3
STB
"H"input
current
VIH=5.5V
3.0
µA
"L"input
current
-150 -100 -50
"L"output
voltage
0.3
V
IOL=500µA
1.0
µA
VIN=5.5V
VIL=0V
SOUT
"H"leak
current
Rev.1.0, Sep.19.2003, page 7 of 13
M52957AFP
Application Example
0.068µF
Vcc
4
3
CHN
6
TESTN
PULSE WIDTH
TRANSFORM
(DOUBLE INTEGRATION)
2
1.0µF
1
PSDN
STATIONARY
LIGHT
REMOVE
I1
I/V
TRANSFORM
AMP
BIAS
RECKON
I1
I1+I2
HOLD
HOLD
PSD PSDF
I2
16
CHF
1.0µF
CINT
NC
STATIONARY
LIGHT
REMOVE
I/V
TRANSFORM
AMP
CLAMP
CIRCUIT
13 NC
GND1
14
12
TESTF
HOLD
CLAMP LEVEL
SWITCHING
15
REFERENCE
VOLTAGE
11
5
GND2
CLALV
SEQUENTIAL CONTROL LOGIC
7
STB RESET
9
10
8
PVcc
INT HOLD SOUT
MICROCOMPUTER
IRED
Controls
(1) STB
This terminal enables IC to operate. IC is Standby at HIGH in this terminal. IC can operate at LOW in this terminal.
(2) RESET
This terminal resets the whole IC including a logic. This terminal resets IC at HIGH.
This terminal cancel resetting IC at the edge from HIGH to LOW.
IC includes power on reset function. The control from external is also possible.
The reset term in IC takes OR between power on reset and control signal from external.
H
L
Indefiniteness
Reset
Reset canceled
While this terminal is HIGH,dielectric divide pole countermeasures circuit of
integration condenser is active.
Rev.1.0, Sep.19.2003, page 8 of 13
M52957AFP
(3)CLALV
This terminal sets up clamp level.
As including D/A of 4bit, 16way clamp level setting is possible by inputting clock after reset is canceled(include none
clamp).
Set up current value of each bit is on
the right table.
The number of input clock and set up
clamp level is as follows.
Clock value
0
1
2
3
4
5
6
7
8
9
10
11
Clamp level(Typ.)
None clamp
0.125 nA
0.250 nA
0.375 nA
0.500 nA
0.625 nA
0.750 nA
0.875 nA
1.000 nA
1.125 nA
1.250 nA
1.375 nA
bit
1
2
3
4
Set up current (Typ.)
0.125 nA
0.25 nA
0.5 nA
1.0 nA
Clock value
12
13
14
15
16
17
18
19
20
Clamp level(Typ.)
1.500 nA
1.625 nA
1.750 nA
1.875 nA
None clamp
0.125 nA
0.250 nA
0.375 nA
0.500 nA
Clamp level is established with fall edge of input clock.
It repeats the same value after 16 clock.
(4) HOLD INT
These terminals implement the following controls by inputting HIGH/LOW.
a. CINT rapid charge ON , OFF
b. CHrapid charge ON , OFF
c. Stationary light hold ON , OFF
d. The first integration ON , OFF
e. The second integration ON , OFF
Stationary light hold
HOLD
The first
integration
CINT
rapid charge
INT
CH
rapid charge
Reset canceled
Rev.1.0, Sep.19.2003, page 9 of 13
The second
integration
M52957AFP
a. CINT rapid charge
After reset is canceled, the capacity of CINT is charged rapidly until INT terminal first falls.
b. CH rapid charge
After reset is canceled, the capacity of CH is charged rapidly until INT terminal first rises and falls.
c. Stationary light hold
After reset is canceled, holds the stationary light while HOLD terminal is HIGH.
d. The first integration
After reset is canceled, as HOLD terminal is HIGH and INT terminal is HIGH, the first integration is
implemented while INT terminal is HIGH. Therefore, the first integration must be finished(INT terminal
from HIGH to LOW) until stationary light hold will be completed (HOLD terminal from HIGH to LOW)
e. The second integration
After reset is canceled, the second integration is implemented as HOLD terminal is LOW and INT terminal
is HIGH. And, the second integration is completed by exceeding judgment level of CINT terminal although
INT terminal is HIGH.
(5)SOUT
When the second integration starts, This terminal becomes from HIGH to LOW.
If CINT terminal exceeds judge level or INT terminal becomes from HIGH to LOW, this terminal becomes from LOW
to HIGH.
(notice)As the signal from microcomputer, the signal that controls IRED ON/OFF is required except for above
mentioned control signals. But applying the timing of HOLD is available.
Rev.1.0, Sep.19.2003, page 10 of 13
M52957AFP
Sequential Time Chart Example
Rev.1.0, Sep.19.2003, page 11 of 13
M52957AFP
Mask Option
(1) The second integration current value can be doubled.( 2.5µ
5.0µA)
(2) Control terminal variation
1
Full spec (typical)
C
L
A
L
V
11
S
T
B
R
E
S
E
T
I
N
T
H
O
L
D
S
O
U
T
5
7
9
10
8
This type uses
CLALV,STB,RESET,INT,HOLD,SOUT terminal as
I/F terminal to the microcomputer.
This is the typical type at M52957AFP.
MICROCOMPUTER
2
Most simplified type
I
N
T
H
O
L
D
S
O
U
T
9
10
8
This type does not connect CLALV,STB,RESET terminals
to the microcomputer.
When above mentioned terminals are not connected to the
microcomputer without changing mask,connect each
terminal to the ground. In this case,clamp level becomes 0
and standby function is lost. Power on reset in IC is used as
reset.
MICROCOMPUTER
3
Explanation of the terminal that can be simplified.
(a)CLALV
In the typical type,16way clamp levels can be set by the external control,but also the
terminal can be simplified by mask option as follows.
(I) Clamp level fixation
Selects 1 point from 16 steps of clamp level and fixes it.
(II) Clamp level 2 step changeover
0.125nA
0.25nA
0.5nA
1.0nA
Selects 2 points from clamp level and switches it by
changing CLALV terminal HIGH/LOW. However,as
selecting 2 points,there is a following constraint.
Fixes 3 parts of 4 switches correspond to each bit in figure to
ON or OFF,controls another part by CLALV terminal .
(b)STB
When no standby function required such as VCC is suitched ON/OFF,
STB terminal can be eliminated.
(c)RESET
Since IC include power on reset circuit, RESET terminal can be
eliminated, As merit of controlling RESET terminal from outside,
distance detection time can be shortened because there is no need
to switch VCC to STB terminal ON/OFF at consecutive distance detection.
Rev.1.0, Sep.19.2003, page 12 of 13
Rev.1.0, Sep.19.2003, page 13 of 13
G
e
Z1
E
HE
1
16
z
D
b
8
9
Detail G
y
JEDEC Code
—
x
M
Weight(g)
0.06
Detail F
A2
A
Lead Material
Alloy 42
L1
EIAJ Package Code
SSOP16-P-225-0.65
c
A1
F
L
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
Symbol
e1
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
—
—
1.45
0
0.1
0.2
—
1.15
—
0.17
0.22
0.32
0.13
0.15
0.2
4.9
5.0
5.1
4.3
4.4
4.5
—
0.65
—
6.2
6.4
6.6
0.3
0.5
0.7
—
1.0
—
—
0.225
—
—
0.375
—
—
0.13
—
—
—
0.1
0˚
—
10˚
—
0.35
—
—
5.8
—
—
1.0
—
Recommended Mount Pad
e
Plastic 16pin 225mil SSOP
I2
16P2E-A
M52957AFP
Package Dimensions
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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