S PLC100A2 SP 40-Channel SEG/COM LCD Driver JUL. 09, 2002 Version 1.4 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. SPLC100A2 Table of Contents PAGE 1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3. FEATURES.................................................................................................................................................................................................. 3 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6 5.1. SEGMENT DRIVER .................................................................................................................................................................................. 6 5.2. COMMON DRIVER .................................................................................................................................................................................. 6 5.3. BOTH CHANNEL 1 AND CHANNEL 2 USED AS COMMON DRIVERS (FCS = VSS) ........................................................................................ 7 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 8 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 8 6.2. DC CHARACTERISTICS........................................................................................................................................................................... 8 6.3. AC CHARACTERISTICS ........................................................................................................................................................................... 8 7. APPLICATION CIRCUITS......................................................................................................................................................................... 10 7.1. SEGMENT DRIVER ................................................................................................................................................................................ 10 7.2. COMMON DRIVER ................................................................................................................................................................................ 10 7.3. SEGMENT / COMMON DRIVER ................................................................................................................................................................11 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 12 8.1. PAD ASSIGNMENT ............................................................................................................................................................................... 12 8.2. ORDERING INFORMATION ..................................................................................................................................................................... 12 8.3. PAD LOCATIONS .................................................................................................................................................................................. 13 8.4. PACKAGE CONFIGURATION ................................................................................................................................................................... 14 8.5. PACKAGE INFORMATION ....................................................................................................................................................................... 15 9. DISCLAIMER............................................................................................................................................................................................. 16 10. REVISION HISTORY ................................................................................................................................................................................. 17 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 JUL. 09, 2002 Version: 1.4 SPLC100A2 40-CHANNEL SEG/COM LCD DRIVER 1. GENERAL DESCRIPTION 3. FEATURES The SPLC100A2 is a Liquid Crystal Display driver that contains ! Liquid Crystal Display driver with serial/parallel conversion function. two sets of 20-bit bi-directional shift registers, 20 data latch flip-flops and 20 Liquid Crystal Display drivers. ! Serial transfer facilitates board design. It also features ! Capable of interfacing to liquid crystal display controllers: 40-channel outputs that can be applied as common or segment driver. HD43160AH, HD61830, HD44780, HD44790, SPLC780 The SPLC100A2 receives serial display data from a display control LSI, converts it into parallel data and supplies liquid ! 40 internal LCD drivers. crystal display waveforms to the liquid crystal. ! Internal serial/parallel conversion circuits: — 20-bit shift register × 2 — 20-bit latch × 2 2. BLOCK DIAGRAM ! Power supply: Y1 — Liquid crystal display driver circuit: 3.0V - 11V V1,V2 V3,V4 CL1 DL1 CL2 DL2 FCS — Internal logic: 2.7V - 5.5V Y20 LCD Drivers ! CMOS process. Latch signal Shift direction 20-bit latch Data Shift signal 20-bit bidirectional shift register Switching circuit 20-bit bidirectional shift register Data 20-bit latch M V1,V2 V5,V6 Data Data Shift direction ! Package form: 64 QFP or bare chip available SHL1 DR1 DR2 SHL2 LCD Drivers Y21 © Sunplus Technology Co., Ltd. Proprietary & Confidential Y40 3 JUL. 09, 2002 Version: 1.4 SPLC100A2 4. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description VDD 22 I Positive power supply voltage input VSS 32 I Ground input VEE 29 I Power supply voltage for liquid crystal display drive Y1 - Y6 28 - 23 O Liquid crystal driver output (Channel 1) Y7 - Y20 21 - 8 O Liquid crystal driver output (Channel 2) Y21 - Y27 7-1 Y28 - Y40 59 - 47 V1, V2 41, 42 I Power supply for liquid crystal display drive (Select level) V3, V4 43, 44 I Power supply for liquid crystal display drive (Non-select level for channel 1) V5, V6 45, 46 I Power supply for liquid crystal display drive (Non-select level for channel 2) SHL1 38 I Selection of the shift direction of channel 1 shift register SHL2 39 I SHL1 DL1 DR1 VDD Out In GND In Out Selection of the shift direction of channel 2 shift register SHL2 DL2 DR2 VDD Out In GND In Out DL1, DR1 33, 34 I/O Data Input / Output of channel 1 shift register DL2, DR2 35, 36 I/O Data Input / Output of channel 2 shift register M 37 I Alternated signal for liquid crystal driver output CL1 30 I Latch signal for channel 1 ( ) *1 Used for channel 2 when FCS is GND CL2 31 I Shift signal for channel 1 ( ) *1 Used for channel 2 when FCS is GND FCS 40 I Mode select signal of channel 2. FCS signal exchanges the latch signal and the shift of channel 2 and inverts M for channel 2.Thus, this signal exchanges the function of channel 2. FCS Level Channel 2 Latch signal and M Polarity Function VDD CL2 CL1 M For common drive GND CL1 CL2 M For segment drive *1 Note: *1. Shift signal *1 *2 indicate the latches at rise and fall times, respectively. Note: *2. The output level relationship between channel 1 and channel 2 based on the FCS signal level as follows: © Sunplus Technology Co., Ltd. Proprietary & Confidential 4 JUL. 09, 2002 Version: 1.4 SPLC100A2 Output Level FCS Data M H H V1 V2 VDD (Select) L V2 V1 L (H) GND (L) Channel 2(Y21 - Y40) H V3 V6 (Non-select) L V4 V5 H H V1 V1 (Select) L V2 V2 L H V3 V5 (Non-select) L V4 V6 © Sunplus Technology Co., Ltd. Proprietary & Confidential Channel 1(Y1 - Y20) 5 JUL. 09, 2002 Version: 1.4 SPLC100A2 5. FUNCTIONAL DESCRIPTIONS 5.1. Segment Driver When SPLC100A2 is used as a segment driver, FCS is connected and V5, V4 and V6 of the liquid crystal display driver power supply to VSS. are short-circuited, respectively. In this case, both channel 1 and channel 2 shift data at the falling edge of CL2 and latch it at the falling edge of CL1. 7 8 1 V3 2 3 4 5 6 7 8 1 2 (FLM) M CL1 Output of latch (Y1 - Y40) Enlarged view M Latch Shift CL1 CL2 DL1/DR1 DL2/DR2 Segment data waveforms (A type waveforms, 1/8 duty cycle) 5.2. Common Driver In this case, channel 1 is used as a segment driver and channel 2 2 shifts data at the rising edge of CL1 and latches it at the rising as common driver. edge of CL2. When channel 2 of SPLC100A2 is used as common driver, FCS is connected to VDD. D L 2 /D R 2 (F L M ) CL1 Y 21 (Y 40 ) Y 22 (Y 39 ) to Y 28 (Y 33 ) E n la rge d vie w In this case, channel 8 1 2 3 4 5 6 7 8 1 2 S h ift N o n -S e le ct S e le ct N o n -S e le ct S e le ct S e le ct S e le ct N o n -S e le ct S e le ct S e le ct D L 2 /D R 2 (F L M ) M CL1 CL2 Y 21 (Y 40 ) S h ift L a tch Common data waveforms (A type waveforms of channel 2, 1/8 duty cycle) © Sunplus Technology Co., Ltd. Proprietary & Confidential 6 JUL. 09, 2002 Version: 1.4 SPLC100A2 5.3. Both Channel 1 and Channel 2 Used as Common Drivers (FCS = VSS) 5.3.1. Common drivers (FCS = VSS) When both of channel 1 and channel 2 are used common drives, In this case, connection of the Liquid Crystal Display driver power FCS is connected to VSS and the signals (CL1, CL2, FLM) from supply is different from that of segment driver, the controller are connected as following. 1). V1, V2: Select level of segment and common 2). V3, V4: Non-select level of segment CL1 CL2 FLM CL2 CL1 DL1 Common DR1 driver DL2 DR2 Y1-Y40 LCD PANEL V V V V V V 1 2 3 4 5 6 Controller FCS SHL1 SHL2 3). V5, V6: Non-select level of common 7 Y1-Y40 SPLC100A2 Segment driver SPLC100A2 Segment driver V1 V2 V3 V4 V5 V6 V1 V2 V3 V4 V5 V6 © Sunplus Technology Co., Ltd. Proprietary & Confidential Y1-Y40 V1 V2 V3 V4 V5 V6 Drive voltage of liquid crystal display SPLC100A2 JUL. 09, 2002 Version: 1.4 SPLC100A2 6. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Characteristics Symbol Ratings Operating Voltage VDD *1 -0.3V to + 7.0V LCD Driver Supply Voltage VEE *2 VDD - 13.5V to VDD+ 0.3V VIN1 -0.3V to VDD + 0.3V Input Voltage 2 (V1 - V6) VIN2 VDD + 0.3V to VEE -0.3V Operating Temperature TOPR -20℃ to + 75℃ Storage Temperature TSTG -55℃ to + 125℃ Input Voltage 1 Note1: It will cause damage to IC if the supply voltage is greater than above. Note2: Connect a protection resistor of 220Ω±5% to VEE. Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 6.2. DC Characteristics (VDD = 2.7V - 5.5V, VDD - VEE = 3.0V - 11V , VSS = 0V, TA = +25℃) Symbol Min. Typ. Max. Unit Input Voltage Characteristics VIH 0.7VDD - VDD V (CL1, CL2, DL1, DL2, DR1, DR2, M, SHL1, SHL2, FCS) VIL 0 - 0.3VDD V Output Voltage VOH VDD-0.4 - - V Test Condition IOH = -0.1mA (DL1, DL2, DR1, DR2) VOL - - 0.4 V IOL = +0.1mA LCD Driver Voltage VLCD 3.0 - 11 V VDD - V5 Vi-Yj Voltage Descending VD1 - - 1.1 V ION = 0.1mA for one of Yj V(V1 - V6)-Y(Y1 - Y40) VD2 - - 1.5 V ION = 0.05mA for each Yj IIL -5.0 - 5.0 µA VIN = 0 to VDD IVL -10 - 10 µA ICC - - 1.0 mA FCL2 = 400KHz IEE - - 10 µA FCL1 = 1.0KHz Input Leakage Current (CL1, CL2, DL1, DL2, DR1, DR2, M, SHL1, SHL2, FCS) Vi Leakage Current V1 - V6 Power Supply Current VIN = VDD - VEE (Output Y1 - Y40: floating) 6.3. AC Characteristics Symbol Min. Typ. Max. Unit Data Shift Frequency (CL2) Characteristics FCL - - 400 KHz Clock High Level (CL1, CL2) tCWH 800 - - ns Width Low Level (CL2) Test Condition tCWL 800 - - ns Data Set-up Time (DL1, DL2, DR1, DR2, FLM) tSU 300 - - ns Clock Set-up Time (CL1, CL2) tSL 500 - - ns (CL2→CL1) Clock Set-up Time (CL1, CL2) tLS 500 - - ns (CL1→CL2) Date Delay Time (DL1, DL2, DR1, DR2) tPD - - 500 ns CL = 15pF Clock Rise/Fall Time (CL1, CL2) tCT - - 200 ns Date Hold Time (DL1, DL2, DR1, DR2, FLM) tDH 300 - - ns © Sunplus Technology Co., Ltd. Proprietary & Confidential 8 JUL. 09, 2002 Version: 1.4 SPLC100A2 CL2 VIH VIL VIH tCWL tCWH tCT Data in (DL1,DL2,DR1,DR2) VIH VIL tCT tSU tDH tSL tpd Data out (DL1,DL2,DR1,DR2) VOH VOL tLS tCWH tCT FLM © Sunplus Technology Co., Ltd. Proprietary & Confidential tLS VIH VIL CL1 VIH VIL tCT tSU 9 JUL. 09, 2002 Version: 1.4 SPLC100A2 7. APPLICATION CIRCUITS 7.1. Segment Driver COM1-COM16 Controller CL2 CL1 D Common signal 40 Y1-Y40 DR 1 DL 2 DR 2 CL 1 CL 2 M DL 1 FCS SPLC100A2 SHL 1 (segment SHL 2 driver) Segment signal 40 Y1-Y40 DL 1 FCS SPLC100A2 SHL 1 (segment SHL 2 driver) DR 1 DL 2 DR 2 CL 1 CL 2 M M LCD PANEL 7.2. Common Driver CL2 FLM Controller CL2 CL1 DL1 SPLC100A2 DR1 DL2 DR2 FCS SHL1 SHL2 CL1 Y1-Y40 LCD PANEL Common driver Y1-Y40 SPLC100A2 Segment driver © Sunplus Technology Co., Ltd. Proprietary & Confidential 10 Y1-Y40 SPLC100A2 Segment driver JUL. 09, 2002 Version: 1.4 SPLC100A2 7.3. Segment / Common Driver Controller D M CL2 CL1 FLM VDD Common signal LCD PANEL 20 20 Y1-Y20 DL1 Y21-Y40 SPLC100A2 DL2 DR1 (segment/ FCS common SHL 1 driver) CL1 SHL 2 CL2 M V1 V2 V3 V4 V5 V6 Segment signal 40 Y1-Y40 DR 1 DL 1 FCS SPLC100A2 DL 2 SHL 1 (segment DR 2 SHL 2 driver) CL1 CL2 M V1 V2 V3 V4 V5 V6 V1 V2 V3 V4 V5 V6 © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 JUL. 09, 2002 Version: 1.4 SPLC100A2 8. PACKAGE/PAD LOCATIONS 8.1. PAD Assignment Chip Size: 2180µm x 2410µm PAD Size: 96µm X 96µm This IC substrate should be connected to VDD Note1: Chip size included scribe line. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 8.2. Ordering Information Product Number Package Type SPLC100A2-nnnnV-C Chip form SPLC100A2-nnnnV-PQ04 Package form - QFP 64L Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z). © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 JUL. 09, 2002 Version: 1.4 SPLC100A2 8.3. PAD Locations PAD No. PAD Name X Y PAD No. Pad Name X Y 1 Y27 -888 837 31 CL2 883 -817 2 Y26 -888 716 32 VSS 883 -690 3 Y25 -888 595 33 DL1 883 -566 4 Y24 -888 474 34 DR1 883 -442 5 Y23 -888 352 35 DL2 883 -319 6 Y22 -888 231 36 DR2 883 -195 7 Y21 -888 110 37 M 883 -72 8 Y20 -888 -10 38 SHL1 883 51 9 Y19 -888 -132 39 SHL2 883 175 10 Y18 -888 -253 40 FCS 883 298 11 Y17 -888 -374 41 V1 883 422 12 Y16 -888 -495 42 V2 883 546 13 Y15 -888 -616 43 V3 883 669 14 Y14 -888 -738 44 V4 883 798 15 Y13 -888 -859 45 V5 883 934 16 Y12 -888 -992 46 V6 754 998 17 Y9 -748 -1000 47 Y40 621 998 18 Y10 -622 -1000 48 Y39 489 998 19 Y11 -496 -1000 49 Y38 366 998 20 Y8 -370 -1000 50 Y37 242 998 21 Y7 -244 -1000 51 Y36 118 998 22 VDD -111 -1023 52 Y35 -4 998 23 Y6 18 -1000 53 Y30 -128 998 24 Y5 138 -1000 54 Y31 -252 998 25 Y4 258 -1000 55 Y32 -375 998 26 Y3 378 -1000 56 Y33 -499 998 27 Y2 498 -1000 57 Y34 -622 998 28 Y1 618 -1000 58 Y29 -746 998 29 VEE 751 -1023 59 Y28 -888 998 30 CL1 883 -944 © Sunplus Technology Co., Ltd. Proprietary & Confidential 13 JUL. 09, 2002 Version: 1.4 SPLC100A2 8.4. Package Configuration NC Y34 Y33 Y32 Y31 Y30 NC Y35 Y36 Y37 Y38 Y39 Y40 64 63 62 61 60 59 58 57 56 55 54 53 52 QFP 64L Top View NC 1 51 V6 Y29 2 50 V5 Y28 3 49 V4 Y27 4 48 V3 Y26 5 47 V2 Y25 6 46 V1 Y24 7 45 FCS Y23 8 44 SHL2 Y22 9 43 SHL1 Y21 10 42 M Y20 11 41 NC Y19 12 40 DR2 Y18 13 39 DL2 Y17 14 38 DR1 Y16 15 37 DL1 Y15 16 36 VSS Y14 17 35 CL2 Y13 18 34 CL1 Y12 19 33 VEE © Sunplus Technology Co., Ltd. Proprietary & Confidential 14 27 28 29 30 31 32 Y6 Y5 Y4 Y3 Y2 Y1 26 NC 24 Y7 VDD 25 23 Y8 Y11 22 Y10 21 Y9 20 SPLC100 JUL. 09, 2002 Version: 1.4 SPLC100A2 8.5. Package Information QFP 64L Outline Dimensions Unit: Millimeter D D1 SUNPLUS SPLC100A2 YYWW E E1 e b A2 A c L1 Symbol Min. A1 Nom. Max. Unit D 23.20 REF Millimeter D1 20.00 REF Millimeter E 17.20 REF Millimeter E1 14.00 REF Millimeter e 1.00 REF Millimeter b 0.35 0.40 0.50 Millimeter A - - 3.40 Millimeter A1 0.25 - - Millimeter A2 2.50 2.72 2.90 Millimeter c 0.11 0.15 0.23 Millimeter L1 © Sunplus Technology Co., Ltd. Proprietary & Confidential 1.60 REF 15 Millimeter JUL. 09, 2002 Version: 1.4 SPLC100A2 9. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. FURTHER, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Sunplus Technology Co., Ltd. Proprietary & Confidential 16 JUL. 09, 2002 Version: 1.4 SPLC100A2 10. REVISION HISTORY Date Revision # Description MAY. 05, 2000 0.1 Original OCT. 25, 2000 1.0 1. Delete “PRELIMINARY” Page 2. Modify Operating Current 3. Modify the pin sequence of COM/SEG in application circuit to the same as the LCD panel sequence 4. Add PAD size description MAY. 03, 2001 1.1 1. Correct chip size and PAD size in the “8.1 PAD Assignment” 12 2. Correct “8.2 Ordering Information” 12 3. Renew to a new document format JAN. 30, 2002 MAY. 27, 2002 JUL. 09, 2002 1.2 1.3 1.4 © Sunplus Technology Co., Ltd. Proprietary & Confidential 1. Correct FCS signal in the “5.3 Both Channel 1 and Channel 2 Used as Common Drivers” 7 2. Correct FCS signal in the “7.2 Common Driver Application Circuit” 10 3. Redefine “Product Number” in the “8.2 Ordering Information” 12 1. Correct “5.2 Common Driver” 6 2. Add description of controller’s signal for “5.3.1 Common drivers” 7 3. Correct controller’s CL1 and CL2 signal for “7.2 Common Driver” 10 4. Renew application circuit for “7.3 Segment / Common Driver” 11 Update “8.5 Package Information” 15 17 JUL. 09, 2002 Version: 1.4