IRF9540S, SiHF9540S

IRF9540S, SiHF9540S
PRODUCT SUMMARY
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• P-Channel
• 175 °C Operating Temperature
• Fast Switching
• Compliant to RoHS Directive 2002/95/EC
VDS (V)
- 100
RDS(on) ()
VGS = - 10 V
Qg (Max.) (nC)
0.20
61
Qgs (nC)
14
Qgd (nC)
29
Configuration
Single
S
DESCRIPTION
D2PAK (TO-263)
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on-resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application.
G
G D
D
S
P-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
SiHF9540S-GE3
IRF9540SPbF
SiHF9540S-E3
D2PAK (TO-263)
SiHF9540STRL-GE3a
IRF9540STRLPbFa
SiHF9540STL-E3a
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
SYMBOL
VDS
VGS
VGS at - 10 V
Currenta
TC = 25 °C
TC = 100 °C
ID
Pulsed Drain
IDM
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
EAS
IAR
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
EAR
Maximum Power Dissipation
TC = 25 °C
PD
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
dV/dt
Operating Junction and Storage Temperature Range
TJ, Tstg
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 25 V, starting TJ = 25 °C, L = 2.7 mH, Rg = 25 , IAS = - 19 A (see fig. 12).
c. ISD  - 19 A, dI/dt  200 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material)
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LIMIT
- 100
± 20
- 19
- 13
- 72
1.0
0.025
640
- 19
15
150
3.7
- 5.5
- 55 to + 175
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
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IRF9540S, SiHF9540S
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mount)a
PARAMETER
RthJA
-
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
-
1.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0, ID = - 250 μA
- 100
-
-
V
VDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.087
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 μA
- 2.0
-
- 4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = - 100 V, VGS = 0 V
-
-
- 100
VDS = - 80 V, VGS = 0 V, TJ = 150 °C
-
-
- 500
-
-
0.20

6.2
-
-
S
-
1400
-
-
590
-
-
140
-
-
-
61
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
ID = - 11 Ab
VGS = - 10 V
VDS = - 50 V, ID = - 11 A
gfs
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
14
Gate-Drain Charge
Qgd
-
-
29
Turn-On Delay Time
td(on)
-
16
-
-
73
-
-
34
-
-
57
-
-
4.5
-
-
7.5
-
-
-
- 19
S
-
-
- 72
TJ = 25 °C, IS = - 19 A, VGS = 0 Vb
-
-
- 5.0
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VGS = - 10 V
ID = - 19 A, VDS = - 80 V,
see fig. 6 and 13b
VDD = - 50 V, ID = - 19 A,
RG = 9.1 , RD = 2.4 , see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = - 19 A, dI/dt = 100 A/μsb
V
-
130
260
ns
-
0.35
0.70
nC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
2014-8-28
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IRF9540S, SiHF9540S
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
102
VGS
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom - 4.5 V
- ID, Drain Current (A)
- ID, Drain Current (A)
Top
101
- 4.5 V
25 °C
175 °C
101
20 µs Pulse Width
TC = 25 °C
100
20 µs Pulse Width
VDS = - 50 V
4
101
- VDS, Drain-to-Source Voltage (V)
91079_01
Fig. 1 - Typical Output Characteristics, TC = 25 °C
RDS(on), Drain-to-Source On Resistance
(Normalized)
- ID, Drain Current (A)
101
- 4.5 V
20 µs Pulse Width
TC = 175 °C
91079_02
3.0
7
8
9
10
- VDS, Drain-to-Source Voltage (V)
ID = - 19 A
VGS = - 10 V
2.5
2.0
1.5
1.0
0.5
0.0
- 60- 40 - 20 0
101
91079_04
Fig. 2 - Typical Output Characteristics, TC = 175 °C
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Fig. 3 - Typical Transfer Characteristics
VGS
Top
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom - 4.5 V
100
5
- VGS, Gate-to-Source Voltage (V)
91079_03
20 40 60 80 100 120 140 160 180
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
3
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IRF9540S, SiHF9540S
3000
Capacitance (pF)
2500
- ISD, Reverse Drain Current (A)
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
2000
Ciss
1500
1000
Coss
500
Crss
101
175 °C
25 °C
100
VGS = 0 V
0
100
101
0.0
- VDS, Drain-to-Source Voltage (V)
91079_05
1.0
2.0
3.0
5.0
4.0
- VSD, Source-to-Drain Voltage (V)
91079_07
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
103
ID = - 19 A
16
2
VDS = - 50 V
VDS = - 20 V
12
8
4
0
5
100 µs
2
1 ms
10
5
10 ms
2
1
TC = 25 °C
TJ = 175 °C
Single Pulse
10
20
30
40
50
2
0.1
60
0.1
QG, Total Gate Charge (nC)
91079_08
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
2014-8-28
102
5
For test circuit
see figure 13
0
91079_06
Operation in this area limited
by RDS(on)
5
VDS = - 80 V
- ID, Drain Current (A)
- VGS, Gate-to-Source Voltage (V)
20
2
5
1
2
5
10
2
5
102
2
5
103
- VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
4
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IRF9540S, SiHF9540S
+ VDD
D.U.T.
Rg
16
- ID, Drain Current (A)
L
VDS
20
IAS
- 10 V
12
0.01 Ω
tp
8
Fig. 10a - Switching Time Test Circuit
4
td(on)
0
25
50
75
100
125
150
10 %
TC, Case Temperature (°C)
91079_09
td(off) tf
tr
VGS
175
Fig. 9 - Maximum Drain Current vs. Case Temperature
90 %
VDS
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
D = 0.5
PDM
0.2
0.1
0.1
t1
t2
0.05
0.02
0.01
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
10-2
10-5
91079_11
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF9540S, SiHF9540S
IAS
RD
VDS
VGS
VDS
D.U.T.
Rg
+VDD
VDD
- 10 V
tp
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
VDS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Energy (mJ)
2000
ID
- 7.8 A
- 13 A
Bottom - 19 A
Top
1600
1200
800
400
VDD = - 25 V
0
25
91079_12c
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
2014-8-28
Fig. 13b - Gate Charge Test Circuit
6
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IRF9540S, SiHF9540S
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
+
• dV/dt controlled by Rg
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Note
• Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
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IRF9540S, SiHF9540S
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
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