IS31AP2110 20W STEREO CLASS-D AUDIO AMPLIFIER WITH POWER LIMIT AND DYNAMIC TEMPERATURE CONTROL September 2014 GENERAL DESCRIPTION FEATURES The IS31AP2110 is a high efficiency stereo Class-D audio amplifier with adjustable power limit function and dynamic temperature control. The loudspeaker driver operates from 8~26V supply voltage and analog circuit operates at 3.3V supply voltage. It can deliver 20W/CH output power into 8 loudspeaker within 0.2% THD+N and without external heat sink when playing music. IS31AP2110 provides parallel BTL (Mono) application, and it can deliver 40W into 4 loudspeaker within 0.11% THD+N. The adjustable power limit function allows user to set a voltage rail lower than half of 3.3V to limit the amount of current through the speaker. Output DC detection prevents speaker damage from long-time current stress. The dynamic temperature control is a gain control system. As chip junction temperature higher than a warning level, the gain level will decrease until junction temperature lower than the warning level. The output short circuit and over temperature protection include auto-recovery feature. The IS31AP2110 is available in a thermally enhanced eTSSOP-28 package. Single supply voltage - 8V ~ 26V for loudspeaker driver - Built-in LDO output 3.3V for others Loudspeaker power from 24V supply - BTL Mode: 20W/CH into 8Ω @0.2% THD+N - PBTL Mode: 40W/CH into 4Ω @0.11% THD+N Loudspeaker power from 13V supply - BTL Mode: 10W/CH into 8Ω @10% THD+N 87% efficient Class-D operation eliminates need for heat sink Differential inputs Four selectable, fixed gain settings Internal oscillator Short-Circuit protection with auto recovery option Under-voltage detection Over-voltage protection Pop noise and click noise reduction Adjustable power limit function for speaker protection Output DC detection for speaker protection Filter-Free operation Over temperature protection with auto recovery Dynamic temperature control prevents chip from over heating APPLICATIONS Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 TV audio Bluetooth speaker system Docking speaker system Consumer audio equipment 1 IS31AP2110 TYPICAL APPLICATION CIRCUIT VCC 100k 1 Micro Controller 2 1k SDB VCCL FAULTB VCC 27,28 1nF 100 F 0.1 F CINL+ 1 F Left Channel Input 3 4 CINL1 F 5 6 8 1 F 9 INL+ OUTL+ INL- PGND GAIN0 OUTL- GAIN1 AGND IS31AP2110 AVDD RPL1 RPL2 10 PGND PLIM 1 F CINR1 F 11 12 Right Channel Input CINR+ 1 F OUTR- INRINR+ OUTR+ VCCR 25 FB 1nF FB 1nF FB 1nF FB 1nF 24 23 20 19 18 VCC 15,16 1nF 14 100 F 0.1 F PBTL Figure 1 Typical Application Circuit (for BTL Stereo, Single-ended Input) VCC 100k 1 Micro Controller 2 1k SDB VCCL FAULTB VCC 27,28 1nF 100 F 0.1 F 3 4 5 6 8 1 F 9 INL+ INL- OUTL+ GAIN0 PGND GAIN1 AGND AVDD OUTL- IS31AP2110 OUTR- RPL1 RPL2 10 PLIM 1 F CINR1 F 11 12 Audio Input CINR+ 1 F VCC PGND OUTR+ 24 23 20 FB 1000pF FB 1000pF 19 18 INRINR+ VCCR 14 25 VCC 15,16 1nF PBTL 100 F 0.1 F Figure 2 Typical Application Circuit (for Parallel BTL Mono, Single-ended Input) Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 2 IS31AP2110 PIN CONFIGURATION Package Pin Configuration (Top View) eTSSOP-28 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 3 IS31AP2110 PIN DESCRIPTION No. Pin Description SDB Shutdown signal for IC (Low = disabled, output Hi-Z; High = operational). Voltage compliance to 26V. 2 FAULTB Open drain output used to display short circuit or dc detect fault. Voltage compliant to 26V. Short circuit faults can be set to autorecovery by connecting FAULTB pin to SDB pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling VCC. 3 INL+ Positive audio input for left channel. Biased at 1.65V. 4 INL- Negative audio input for left channel. Biased at 1.65V. 5 GAIN0 Gain select least significant bit. Voltage compliance to 26V. 6 GAIN1 Gain select most significant bit. Voltage compliance to 26V. NC Not connected. 8 AGND Analog signal ground. Connect to the thermal pad. 9 AVDD 3.3V regulated output. 10 PLIM Power limit level adjustment. Connect a resistor divider from AVDD to GND to set power limit. Give VPLIMIT <1.55V to set power limit level. Connect to both of AVDD (>1.55V) and GND are all without power limit feature. 11 INR- Negative audio input for right channel. Biased at 1.65V. 12 INR+ Positive audio input for right channel. Biased at 1.65V. 14 PBTL Parallel BTL mode switch, high for parallel BTL output. Voltage compliance to 26V. 15, 16 VCCR High-voltage power supply for right-channel. Right channel and left channel power supply inputs are connect internal. 18 OUTR+ Class-D H-bridge positive output for right channel. 19 PGND Power ground for the H-bridges. 20 OUTR- Class-D H-bridge negative output for right channel. 23 OUTL- Class-D H-bridge negative output for left channel. 24 PGND Power ground for the H-bridges. 25 OUTL+ Class-D H-bridge positive output for left channel. 27, 28 VCCL High-voltage power supply for left-channel. Right channel and left channel power supply inputs are connect internal. Thermal Pad Connect to GND. 1 7,13,17, 21,22,26 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 4 IS31AP2110 ORDERING INFORMATION INDUSTRIAL RANGE: -40°C TO +85°C Order Part No. Package QTY IS31AP2110-ZLS2-TR IS31AP2110-ZLS2 eTSSOP-28, Lead-free 2500/Reel 50/Tube Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 5 IS31AP2110 ABSOLUTE MAXIMUM RATINGS Supply voltage (VCCR, VCCL), VCC Interface pin voltage, (SDB, GAIN0, GAIN1, PBTL, FAULTB) (PLIM, INL+, INL-, INR+, INR-) Minimum load resistance, RL, (BTL: VCC > 15V) (BTL: VCC ≤ 15V) PBTL Thermal resistance, θJA Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA ESD (HBM) ESD (CDM) -0.3V ~ +30V -0.3V ~ +26V -0.3V ~ +3.6V 4.8Ω 3.2Ω 3.2Ω 28°C/W 150°C -65°C ~ +150°C −40°C ~ +85°C 2kV 500V Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VCC=24V, TA=25°C, RL=8Ω (unless otherwise noted). Symbol Parameter VCC Supply voltage to VCCL, VCCR ICC Quiescent current ISD Shutdown current RDS(ON) VOS G Drain-source on-state resistance-High side PMOS Drain-source on-state resistance-Low side NMOS Class-D output offset voltage (measured differentially) Gain Condition Min. Typ. 8 Max. Unit 26 V VSDB = 2V, no load 32 50 VSDB = 2V, no load, VCC = 12V 20 35 VSDB = 0.8V, no load <10 25 VSDB = 0.8V, no load, VCC = 12V <10 25 mA µA 300 VCC=12V, Id=500mA, TJ=25°C mΩ 200 VI = 0, Gain= 36dB 10 mV Gain1= 0.8V, Gain0=0.8V 18 20 22 Gain1= 0.8V, Gain0= 2V 24 26 28 Gain1= 2V, Gain0= 0.8V 30 32 34 Gain1= 2V, Gain0= 2V 34 36 38 dB tON Turn-on time VSDB = 2V 51 ms tOFF Turn-off time VSDB = 0.8V 4 µs Internal regulated output IAVDD = 0.1mA AVDD 3.0 3.3 3.6 V Logic Electrical Characteristics VIH High level input voltage SDB, GAIN0, GAIN1, PBTL VIL Low level input voltage SDB, GAIN0, GAIN1, PBTL 0.8 V VOL Low level output voltage FAULTB,RPU=100kΩ, VCC=26V 0.8 V IIH High level input current SDB,GAIN0,GAIN1,PBTL, VI=2V, VCC=18V 50 µA IIL Low level input current SDB,GAIN0,GAIN1,PBTL, VI=0.8V, VCC=18V 5 µA Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 2 V 6 IS31AP2110 AC ELECTRICAL CHARACTERISTICS VCC=24V, TA=25°C, RL=8Ω (unless otherwise noted). Symbol Parameter Condition Min. Typ. Max. Unit THD+N = 10%, f = 1kHz, VCC = 13V 10 THD+N = 10%, f = 1kHz, VCC = 16V 15 VCC=24V, RL=8Ω, f=1kHz, PO=15W (half-power) 0.1 VCC=12V, RL=8Ω, f=1kHz, PO=5W (half-power) 0.11 Output integrated noise 20Hz to 22kHz, A-weighted filter, Gain = 20dB, RL=8Ω 130 µV SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1kHz, Gain = 20dB, A-weighted 102 dB PSRR Power supply ripple rejection 200mVP-P ripple at 1kHz, Gain = 20dB, Inputs ac-coupled to AGND -62 dB XTALK Crosstalk f=1kHz, VO=1Vrms, Gain=20dB -83 dB fOSC Oscillator frequency 310 kHz TSD Thermal trip point 170 °C Thermal hysteresis 20 °C PO THD+N VN TSD_HY Output power Total harmonic distortion + noise Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 W % 250 7 IS31AP2110 TYPICAL PERFORMANCE CHARACTERISTICS 20 20 RL = 4Ω+33µH Gain = 20dB f = 1kHz VCC = 10V 1 VCC = 15V 0.1 . 50m 100m 500m 1 2 5 10 VCC = 15V 1 20 VCC = 18V 0.01 10m 20m 80 50m 100m Output Power(W) 500m 1 Figure 3 THD+N vs. Output Power 10 20 80 Figure 4 THD+N vs. Output Power RL = 8Ω+66µH Gain = 20dB f = 1kHz THD+N(%) 1 VCC = 15V VCC = 24V VCC = 18V 0.01 10m 20m 50m 100m 500m 1 2 5 VCC = 24V Gain = 20dB RL = 8Ω+66µH 5 VCC = 12V 0.1 . 10 20 Po = 1W Po = 5W 1 0.1 Po = 10W 0.01 . 0.001 20 50 50 100 200 100 VCC = 12V VCC = 15V 90 1k 2k 20k 5k Figure 6 THD+N vs. Frequency Figure 5 THD+N vs. Output Power 100 500 Frequency(Hz) Output Power(W) VCC = 12V 90 80 80 VCC = 18V 70 Efficiency(%） Efficiency(%） 5 20 10 60 50 40 VCC = 18V 70 VCC = 24V VCC = 15V 60 50 40 30 30 20 20 RL = 6Ω+47μH Gain = 20dB 10 0 2 VCC = 24V Output Power(W) 20 THD+N(%) VCC = 12V 0.1 . VCC = 12V 0.01 10m 20m RL = 6Ω+47µH Gain = 20dB f = 1kHz 10 VCC = 8V THD+N(%) THD+N(%) 10 0 5 10 15 20 25 30 35 40 Output Power(W) Figure 7 Efficiency vs. Output Power Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 45 RL = 8Ω+66μH Gain = 20dB 10 50 0 0 5 10 15 20 25 30 35 40 45 50 55 60 Output Power(W) Figure 8 Efficiency vs. Output Power 8 IS31AP2110 +0 RL = 8Ω+66μH Gain = 20dB VRipple = 0.2VPP PSRR(dB) -20 -40 VCC = 24V VCC = 18V -60 -80 VCC = 12V -100 20 50 100 200 500 1k 2k 5k 10k 20k Frequency(H z) Figure 9 PSRR Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 9 IS31AP2110 FUNCTIONAL BLOCK DIAGRAM VCCL INL+ INL- Gain Gontrol Amplifier PLIMIT Modulator PWM Logic OUTL+ Power Stage OUTLPGND Dynamic Thermal Temperature Warning Control DC Detect Ramp Generator Short-Circuit Protection PBTL Select VCCR INR+ INR- Gain Gontrol Amplifier PLIMIT Modulator PWM Logic OUTR+ Power Stage OUTRPGND GAIN0 GAIN1 Gain Select Short Circuit Error PLIMIT Reference DC Detect Error PLIM Control Logic SDB PBTL I/O Buffer PBTL Select Regulator Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 Bias & Reference FAULTB Logic Thermal Detect Under-Voltage Protection FAULTB Thermal Warning AGND AVDD 10 IS31AP2110 APPLICATIONS INFORMATION Table 2 DC Detect Threshold GAIN SETTINGS The gain of the IS31AP2110 is set by two input pins, GAIN0 and GAIN1. By varying input resistance in IS31AP2110, the various volume gains are achieved. The respective volume gain and input resistance are listed in Table 1. However, there is 20% variation in input resistance from production variation. Table 1 Volume gain and input impedance Volume Gain Input Resistance, GAIN1 GAIN0 (dB) RIN (kΩ) 0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9 AV (dB) VIN (mV, differential) 20 104 26 52 32 26 36 16 Table 3 Output DC Detect Duty (for Either Channel) VCC (V) Output Duty Exceeds 8 13% 12 8.7% 16 6.5% 24 4.3% SHUTDOWN (SDB) CONTROL Pulling SDB pin low will let IS31AP2110 operate in low-current state for power conservation. The IS31AP2110 outputs will enter mute once SDB pin is pulled low, and regulator will also disable to save power. If let SDB pin floating, the chip will enter shutdown mode because of the internal pull low resistor. For the best power-off performance, place the chip in the shutdown mode in advance of removing the power supply. THERMAL PROTECTION DC DETECTION To protect loudspeaker drivers from over-current damage, IS31AP2110 has built-in short-circuit protection circuit. When the wires connected to loudspeakers are shorted to each other or shorted to GND or to VCC, overload detectors may activate. Once one of right and left channel overload detectors are active, the amplifier outputs will enter a Hi-Z state and the protection latch is engaged. The short protection fault is reported on FAULTB pin as a low state. The latch can be cleared by reset SDB or power supply cycling. IS31AP2110 has dc detection circuit to protect the speakers from DC current which might be occurred as input capacitor defect or inputs short on printed circuit board. The detection circuit detects first volume amplifier stage output, when both differential outputs’ voltage become higher than a determined voltage or lower than a determined voltage for more than 420ms, the dc detect error will occur and report to FAULTB pin. At the same time, loudspeaker drivers of right/left channel will disable and enter HiZ. This fault can’t be cleared by cycling SDB, it is necessary to cycle the VCC supply. The minimum differential input voltages required to trigger the DC detect function are shown in table2. The input voltage must keep above the voltage listed in the table for more than 420msec to trigger the DC detect fault. The equivalent class-D output duty of the DC detect threshold is listed in table3. For 8V supply, DC detect fault will occur as output duty exceed 13% for more than 420msec. Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 If the internal junction temperature is higher than 170oC, the outputs of loudspeaker drivers will be disabled and at low state. The temperature for IS31AP2110 returning to normal operation is about 150oC. The variation of protected temperature is about 10%. Thermal protection faults are not reported on the FAULTB pin. SHORT-CIRCUIT PROTECTION The short circuit protection latch can have autorecovery function by connect the FAULTB pin directly to SDB pin. The latch state will be released after 420ms, and the short protection latch will recycle if output overload is detected again. UNDER-VOLTAGE DETECTION When the AVDD voltage is lower than 2.7V or the VCC voltage is lower than 7.5V, loudspeaker drivers of right/left channel will be disabled and kept at low state. Otherwise, IS31AP2110 return to normal operation. 11 IS31AP2110 OVER-VOLTAGE PROTECTION When the VCC is higher than 30V, loudspeaker will be disabled kept at low state. The protection status will be released as VCC lower than 28.7V. POWER LIMIT FUNCTION The voltage at PLIM pin (pin 10) can used to limit the power of first gain control amplifier output. Add a resistor divider from AVDD to ground to set the voltage VPLIMIT at the PLIMIT pin. The voltage VPLIM sets a limit on the output peak-to-peak voltage. The maximum BTL output voltage of the gain control amplifier is limited to 2×(1.55V–VPLIM). The Class-D BTL output voltage on loudspeaker is amplified by 9.95 of 2×(1.55V–VPLIM). For normal BTL operation (Stereo) and PBTL (Mono) operation: POUT 2 VP 9.95 2 RL 2 for unclipped power (1) Where: - VP is the peak voltage of gain control amplifier output, if (VIN×Gv /2) < (1.55V–VPLIM), then VP = (VIN×Gv /2). If (VIN×Gv /2) > (1.55V–VPLIM), then VP = (1.55V– VPLIM). - VIN is the input peak voltage. - Gv is the gain of gain control amplifier, the four gain levels are 1V/V, 2V/V, 4V/V, 6.34V/V, corresponding to 20dB, 26dB, 32dB, 36dB overall gain. - AVDD is the regulator output at pin 9, typical 3.3V. - RL is the load resistance. - POUT (10% THD) = 1.25 x POUT (unclipped). Table 4 PLIM Typical Operation VPLIM(V) VPLIM(V) Output Test Output @ @ Voltage Conditions PO (W) THD+N=1 THD+N=1 (VP-P) % 0% 25 0.54 0.65 40 VCC=24V RL=8Ω 20 0.65 0.75 35.6 15 0.77 0.85 30.8 10 0.91 0.98 25.2 5 1.1 1.15 17.8 Note: Connect PLIM pin to AVDD (>1.55V) or GND (either one) to disable power limit function. PBTL (MONO) FUNCTION IS31AP2110 provides the application of parallel BTL operation with two outputs of each channel connected directly. If the PBTL pin is tied high, the positive and negative outputs of left and right channel are synchronized and in phase. Apply the input signal to the RIGHT channel input in PBTL mode and let the LEFT channel input grounded, and place the speaker between the LEFT and RIGHT outputs. The output current capability is doubled of that in normal mode. See the application circuit example for PBTL (Mono) mode operation. For normal BTL (Stereo) operation, connect the PBTL pin to ground. DYNAMIC TEMPERATURE CONTROL (DTC) The DTC function is designed to protect the loudspeaker from over heating. As the junction temperature is higher than OT_W, the gain of amplifier will decrease step by step every 0.25s. Finally, as the junction temperature is lower than OT_R, the attenuated gain steps will be released step by step every 0.5s. If DTC can’t suppress the temperature and the temperature reach to the OT trip point (170oC), the amplifier will be shutdown. The OT hysteresis temperature equals to OT_R. Typically, OT_W is 160oC and OT_R is 145oC. Figure 10 Gain Contribution of the Two Gain Stages Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 12 IS31AP2110 Figure 11 Dynamic Temperature Control Function Input Capacitors (CIN) The performance at low frequency (bass) is affected by the corner frequency (fC) of the high-pass filter composed of input resistor (RIN) and input capacitor (CIN), determined in Equation (2). Typically, a 0.1µF or 1µF ceramic capacitor is suggested for CIN. The resistance of input resistors is different at different gain setting. The respective gain and input resistance are listed in Table 1 (shown at GAIN SETTING). However, there is 20% variation in input resistance from production variation. fC 1 Hz (2) 2π R IN C IN Figure 13 Typical Ferrite Bead Filter Output LC Filter If the traces from the IS31AP2110 to speaker are not short, it is recommended to add the output LC filter to eliminate the high frequency emissions. Figure 14 shows the typical output filter for 8Ω speaker with a cut-off frequency of 27kHz and Figure 15 shows the typical output filter for 4Ω speaker with a cut-off frequency of 27kHz. Figure 12 Corner Frequency Ferrite Bead Selection If the traces from the IS31AP2110 to speaker are short, the ferrite bead filters can reduce the high frequency emissions to meet FCC requirements. A ferrite bead that has very low impedance at low frequency and high impedance at high frequency (above 1MHz) is recommended. The impedance of the ferrite bead can be used along with a small capacitor with a value around 1000pF to reduce the frequency spectrum of the signal to an acceptable level. Figure 14 Typical LC Output Filter for 8Ω Speaker Figure 15 Typical LC Output Filter for 4Ω Speaker Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 13 IS31AP2110 Power Supply Decoupling Capacitor (CS) Because of the power loss on the trace between the device and decoupling capacitor, the decoupling capacitor should be placed close to VCCR/L and PGND to reduce any parasitic resistor or inductor. A low ESR ceramic capacitor, typically 1000pF, is suggested for high frequency noise rejection. For mid-frequency noise filtering, place a capacitor typically 0.1µF or 1µF as close as possible to the device VCCR/L leads works best. For low frequency noise filtering, a 100µF or greater capacitor (tantalum or electrolytic type) is suggested. Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 Figure 16 Recommended Power Supply Decoupling Capacitors. 14 IS31AP2110 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 17 Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 15 IS31AP2110 PACKAGE INFORMATION eTSSOP-28 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 09/01/2014 16