APA2615 Mono/Stereo High-Power Class-D Amplifier Features • • • • • • • • • • • • • • • • General Description Operating Voltage: 8.0V-16.5V The APA2615 is a stereo, high efficiency, Class-D audio High Efficiency 90% at PO=10W, 8Ω Speaker, amplifier available in a QFN5.2x6.2-32 package. The filter-free Class-D architecture eliminates the exter- VDD=12V nal low pass filters, and save the PCB space and BOM costs. The APA2615 also has a spread clock function that Low Shutdown Current –IDD=5µA at VDD=16.5V reduces the high frequency radiation and low the EMI noise. The Zero-crossing-change function changes the Power Limit Function Switchable Non-Clip Function /DRC (Dynamic gain when both output (VOUTP and VOUTN) crossing together can minimum the pop noise. The power limit function can Range Control) Function Build-In Oscillator protect the speaker when output signal excess the speaker limit rating. The non-clip and DRC functions are Spread Clock Function eliminate the distortion at large input signal, and can fit the high dynamic input signal to a small dynamic speaker. The operating voltage is from 8V to 16.5V. The APA2615 External Synchronization Function Master/Slaver Synchronization Function DC Detection Function is capable of driving 10W at 12V or 18W at 16V into 8Ω speaker and provides thermal and over-current Stereo/Monaural Function Shutdown and Mute Function protections. It also can detect the DC that prevents the speaker voice coil from being destroyed. Thermal and Over-Current Protections with AutoRecovery Efficiency vs. Output Power (8Ω) Pin-to-Pin Compatible YDA148 100 Space Saving Package QFN5.2x6.2-32 90 Lead Free and Green Devices Available 80 (RoHS Compliant) Efficiency (%) 70 Applications • LCD TV 60 50 40 20 Simplified Application Circuit 10 0 Left Channel Input LOUTP LINP LINN LOUTN VDD=12V RL=8Ω+33µH fin=1kHz AUX-0025 AES-17(20kHz) 30 Left Channel Speaker 0 1 2 3 4 5 6 7 Output Power (W) 8 9 10 APA2615 Right Channel Input RINN RINP ROUTN ROUTP Right Channel Speaker ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 1 www.anpec.com.tw APA2615 26 LPVDD 27 LOUTN 28 LOUTN 29 LPGND 30 LOUTP 31 LOUTP 32 LPVDD Pin Configuration AVDD 1 25 GAIN1 3V3REG 2 24 GAIN0 LINP 3 23 DRC1 LINN 4 22 DRC0 APA2615 (Top View) VREF 5 21 OSCIN RPVDD 16 ROUTN 15 ROUTN 14 17 SD RPGND 13 18 PFLAG PMAX 9 ROUTP 12 19 MUTE AGND 8 ROUTP 11 20 OSCO RINP 7 RPVDD 10 RINN 6 Ordering and Marking Information Package Code QA : QFN5.2x6.2-32 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2615 Assembly Material Handling Code Temperature Range Package Code APA2615 QA : XXXXX - Date Code APA2615 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter Rating VDD Supply Voltage (RPVDD to RPGND, LPVDD to LPGND, AVDD to AGND) -0.3 to 20 VSD Input Voltage (SD to AGND) -0.3 to 20 Vin Input Voltage (LINN, LINP, RINN and RINP to AGND) -0.3 to 4 Input Voltage (MUTE, PMAX, DRC0, DRC1, GAIN0 and GAIN1 to AGND) -0.3 to 4 Vcontrol VPGND_AGND Input Voltage (LPGND, RPGND to AGND) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 Unit V -0.3 to +0.3 2 www.anpec.com.tw APA2615 Absolute Maximum Ratings (Cont.) (Note 1) Symbol TJ Parameter Rating Maximum Junction Temperature TSTG Storage Temperature Range TSDR Soldering Temperature Range, 10 Seconds PD Power Dissipation Unit 150 ο -65 to +150 ο 260 ο C C C Internally Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) Unit o 22 QFN5.2x6.2-32 C/W Junction-to-Case Resistance in Free Air (Note 3) o 4 C/W QFN5.2x6.2-32 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of QFN5.2X6.2-32 is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the QFN5.2X6.2-32 package. Recommended Operating Conditions (Note 4) Symbol Range Parameter VDD Supply Voltage VIH High Level Threshold Voltage Unit Min. Max. 8.0 16.5 SD 2.5 16.5 MUTE, PMAX, DRC0, DRC1, GAIN0, GAIN1 2.5 3.6 SD 0 1 MUTE, PMAX, DRC0, DRC1, GAIN0, GAIN1 0 1 0 3 V VIL Low Level Threshold Voltage VIC Common Mode Input Voltage TA Ambient Temperature Range -40 85 TJ Junction Temperature Range -40 125 ο C Ω RL Speaker Resistance 3.5 Note 4: At stereo mode, if the RL=4Ω, the VDD should not excess 12V or it may trigger the Over-Current Protection. Electrical Characteristics VDD=12V, GND=0V, TA= 25oC, A =22dB (unless otherwise noted) V Symbol Parameter V3V3REG IO=2mA VVREF VDET The DC Detection Active Voltage at Output Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 APA2615 Test Conditions DC detection (>0.5s) 3 Unit Min. Typ. Max. 2.85 3.3 3.75 - V3V3REG /2 - - 2 2.5 V www.anpec.com.tw APA2615 Electrical Characteristics (Cont.) VDD=12V, GND=0V, TA= 25oC, A =22dB (unless otherwise noted) V Symbol VFLAG Parameter APA2615 Test Conditions Unit Min. Typ. Max. - - 0.4 2.2 - - Protection Flag Output Voltage ISOURCING=0.4mA VOSCOH Oscillator Output Voltage ISOURCING=4mA VOSCOL Oscillator Output Voltage ISINKING=4mA - - 0.6 Recovery Time from Shutdown C5=0.1µF - 1 1.5 - - 0.001 - 18 36 - 2 10 TSD TMUTE IDD IMUTE ISD II Recovery Time from Mute Supply Current No Load Mute Current Shutdown Current SD = 0V - 5 100 Input Current SD, MUTE, DRC0, DRC1, GAIN0, GAIN1 - - 5 FOSC Internal Oscillator Frequency 400 500 600 FOSCI External Clock at OSCI Pin 400 500 600 DCOSCI Duty Cycle of External Clock 40 - 60 RDSON Static Drain-Source On-State Resistance (P-channel and N channel Power MOSFET) VDD=8V, IL=0.8A - 530 - VDD=12V, IL=1A - 480 - VDD=16V, IL=1.4A - 440 - Ri Input Resistor RINN, RINP, LINN, LINP (Gain independent) 8 10 12 RO Output Resistor ROUTN, ROUTP, LOUTN, LOUTP - 300 - η Efficiency Stereo, RL=8Ω, PO=9W - 89 - Stereo, RL=4Ω, PO=15W - 85 - AV Closed-Loop Gain Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 s mA µA kHz % mΩ kΩ DRC[1:0] (0,0), GAIN (0,0) - 22 - DRC (0,0), GAIN (0,1) - 28 - DRC (0,0), GAIN (1,0) - 34 - DRC (0,0), GAIN (1,1) - 16 - DRC (0,1), GAIN (0,0) - 34 - DRC (0,1), GAIN (0,1) - 40 - DRC (0,1), GAIN (1,0) - 46 - DRC (0,1), GAIN (1,1) - 28 - DRC (1,0), GAIN (0,0) - 34 - DRC (1,0), GAIN (0,1) - 40 - DRC (1,0), GAIN (1,0) - 46 - DRC (1,0), GAIN (1,1) - 28 - DRC (1,1), GAIN (0,0) - 34 - DRC (1,1), GAIN (0,1) - 40 - DRC (1,1), GAIN (1,0) - 46 - DRC (1,1), GAIN (1,1) - 28 - 4 V % dB www.anpec.com.tw APA2615 Electrical Characteristics (Cont.) VDD=12V, GND=0V, TA= 25oC, A =22dB (unless otherwise noted) V STEREO MODE Symbol Parameter APA2615 Test Conditions Unit Min. Typ. Max. VDD=16V,TA=25oC THD+N=1% fIn=1kHz RL=8Ω - 14 - THD+N=10% fIn=1kHz RL=8Ω - 18 - Total Harmonic Distortion Plus Noise fIn=1kHz RL=8Ω PO=10W - 0.05 0.1 Channel Separation PO=1W,RL=8Ω, fin=1kHz - -70 -60 PSRR Power Supply Rejection Ratio fin=100Hz - -65 -55 RL= 8Ω fin=1kHz - -65 -55 CMRR Common Mode Rejection Ration fin=1kHz, RL=8Ω, Vin=0.1Vpp, AV=22dB - -65 -55 AttMute Mute Attenuation fin=1kHz, RL=8Ω, Vin=1Vpp - -115 -100 Attshutdown Shutdown Attenuation fin=1kHz, RL=8Ω, Vin=1Vpp - -115 -100 Offset Voltage No load, A V=22dB - - 20 mV Noise Output Voltage With A-weighting Filter (AV=22dB) - 250 500 µVrms PO THD+N Crosstalk VOS Vn Output Power W % dB o VDD=12V,TA=25 C PO THD+N Crosstalk PSRR CMRR THD+N=1% fin=1kHz RL=4Ω - 14 - RL=8Ω - 8 - THD+N=10% fin=1kHz RL=4Ω - 17 - Output Power RL=8Ω - 10 - RL=4Ω PO=10W - 0.07 0.1 RL=8Ω PO=6W - 0.07 0.1 Total Harmonic Distortion Plus Noise fin=1kHz Channel Separation PO=0.5W, RL=8Ω, fin=1kHz Power Supply Rejection Ratio Common Mode Rejection Ration RL=8Ω, % - -70 -60 fin=100Hz - -65 -55 fin=1kHz - -65 -55 - -65 -55 fin=1kHz, RL=8Ω, Vin=0.1Vpp, AV=22dB W dB AttMute Mute Attenuation fin=1kHz, RL=8Ω, Vin=1Vpp - -115 -100 Attshutdown Shutdown Attenuation fin=1kHz, RL=8Ω, Vin=1Vpp - -115 -100 Offset Voltage No load, A V=22dB - - 20 mV Noise Output Voltage With A-weighting Filter (AV=22dB) - 230 500 µVrms - 6 - VOS Vn o VDD=8V,TA=25 C PO THD+N=1% fin=1kHz RL=4Ω RL=8Ω - 3.5 - THD+N=10% fin=1kHz RL=4Ω - 7.5 - RL=8Ω - 4.5 - Output Power Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 5 W www.anpec.com.tw APA2615 Electrical Characteristics (Cont.) VDD=12V, GND=0V, TA= 25oC (unless otherwise noted) STEREO MODE Symbol Parameter APA2615 Test Conditions Unit Min. Typ. Max. RL=4Ω PO=4.5W - 0.1 0.2 RL=8Ω PO=2.5W - 0.1 0.2 VDD=8V,TA=25oC (CONT.) THD+N Crosstalk PSRR CMRR AttMute Attshutdown VOS Vn Total Harmonic Distortion Plus Noise fin=1kHz Channel Separation PO=0.5W, RL=8Ω, fin=1kHz Power Supply Rejection Ratio Common Mode Rejection Ration RL=8Ω % - -60 -60 fin=100Hz - -65 -55 fin=1kHz - -65 -55 - -70 -55 fin=1kHz, RL=8Ω, Vin=0.1Vpp, AV=22dB dB Mute Attenuation fin=1kHz, RL=8Ω, Vin=1Vpp - -115 -100 Shutdown Attenuation fin=1kHz, RL=8Ω, Vin=1Vpp - -115 -100 Offset Voltage No load, A V=22dB - - 20 mV Noise Output Voltage With A-weighting Filter (AV=22dB) - 200 400 µVrms MONO MODE Symbol Parameter APA2615 Test Conditions Unit Min. Typ. Max. - 16 - VDD=12V,TA=25oC PO THD+N PSRR THD+N=1% fin=1kHz RL=4Ω RL=8Ω - 8.5 - THD+N=10% fin=1kHz RL=4Ω - 20 - RL=8Ω - 11 - RL=4Ω PO=12W - 0.08 0.2 RL=8Ω PO=6W - 0.1 0.2 fin=100Hz - -65 -55 fin=1kHz - -65 -55 Output Power Total Harmonic Distortion Plus Noise fin=1kHz Power Supply Rejection Ratio RL=8Ω, W % CMRR Common Mode Rejection Ration fin=1kHz, RL=8Ω, Vin=0.1Vpp, AV=22dB - -60 -55 AttMute Mute Attenuation fin=1kHz, RL=8Ω, Vin=1Vrms - -115 -100 Shutdown Attenuation fin=1kHz, RL=8Ω, Vin=1Vrms - -115 -100 Offset Voltage No load, A V=22dB - - 20 mV Noise Output Voltage With A-weighting Filter (AV=22dB) - 200 400 µVrms Attshutdown VOS Vn Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 6 dB www.anpec.com.tw APA2615 Typical Operating Characteristics Efficiency vs. Output Power (4Ω) Efficiency vs. Output Power (8Ω) 100 100 90 90 VDD=8V 80 VDD=12V 70 VDD=8V 60 50 RL=4Ω+33µH fin=1kHz Ci=1µf AV=22dB THD+N≦10% AUX-0025 AES-17(20KHz) 40 30 20 10 0 0 100 2 4 6 8 10 12 14 16 Output Power (W) Output Power (W) Efficiency (%) 70 60 RL=4Ω+33µH fin=1kHz Ci=1µf AV=22dB THD+N≦10% AUX-0025 AES-17(20KHz) MONO Mode 10 0 0 5 10 15 20 25 Output Power (W) 30 Output Power (W) 15 4 6 8 10 12 14 16 18 20 Output Power (W) RL=4Ω fin=1kHz 16 Ci=1µF AV=22dB AUX-0025 14 AES-17(20kHz) THD+N=10% 12 10 6 35 THD+N=1% 8 20 18 THD+N=10% Output Power (W) RL=8Ω fin=1kHz Ci=1µF AV=22dB AUX-0025 AES-17(20kHz) 2 8 Output power vs. Supply Voltage 20 0 Output power vs. Supply Voltage VDD=16V 20 30 18 VDD=12V 30 RL=8Ω+33µH fin=1kHz Ci=1µf AV=22dB THD+N≦10% AUX-0025 AES-17(20KHz) 40 0 18 20 90 40 50 10 VDD=8V 50 60 20 Efficiency vs. Output Power (4Ω_Mono mode) 80 VDD=16V 80 Efficiency (%) Efficiency (%) 70 VDD=12V 10 THD+N=1% 5 16 14 9 10 11 Supply Voltage (V) 12 Output power vs. Supply Voltage (Mono Mode) RL=4Ω fin=1kHz Ci=1µF AV=22dB AUX-0025 AES-17(20kHz) Mono Mode THD+N=10% 12 THD+N=1% 10 8 0 8 10 12 14 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 6 16 7 8 9 10 11 Supply Voltage (V) 12 www.anpec.com.tw APA2615 Typical Operating Characteristics (Cont.) THD+N vs. Output Power 10 VDD=8V 5 2 1 THD+N (%) THD+N (%) VDD=12V RL=4Ω fin=1kHz Ci=1µF AV=22dB AUX-0025 AES-17(20kHz) Single Channel 1 THD+N vs. Output Power 10 0.1 VDD=8V VDD=12V VDD=16V 0.5 0.2 RL=8Ω fin=1kHz Ci=1µF AV=22dB AUX-0025 AES-17(20kHz) Single Channel 0.1 0.05 0.02 0.01 0.01 0 0 1 2 3 4 5 6 7 8 9 101112131415161718 Output Power (W) THD+N vs. Output Power R THD+N (%) THD+N (%) 1 RL=4Ω fin=1kHz Ci=1µF AV=22dB AUX-0025 AES-17(20kHz) Mono Mode 0.1 0.01 0 5 10 15 20 25 30 35 PO=10W AV=34dB 0.1 0.006 20 100 Output Power (W) THD+N vs. Frequency THD+N (%) VDD=12V RL=8Ω Ci=1µF AUX-0025 AES-17(20kHz) PO=6W AV=34dB 0.1 0.01 0.006 20 PO=1W AV=34dB 100 1 PO=6W AV=22dB THD+N (%) 1 PO=1W AV=22dB 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 0.006 20 10k 20k 8 PO=1W AV=22dB 1k Frequency (Hz) 10k 20k THD+N vs. Frequency VDD=12V RL=4Ω Ci=1µF AUX-0025 AES-17(20kHz) Mono Mode 0.1 0.01 PO=10W AV=22dB PO=1W AV=34dB 0.01 40 45 6 8 10 12 14 16 18 20 22 Output Power (W) VDD=12V RL=4Ω Ci=1µF AUX-0025 AES-17(20kHz) VDD=16V VDD=12V 4 THD+N vs. Frequency 1 10 VDD=8V 2 PO=11W AV=34dB 100 PO=11W AV=22dB PO=1W AV=34dB PO=1W AV=22dB 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2615 Typical Operating Characteristics (Cont.) -30 1k Frequency (Hz) Output Noise Voltage (µV) Output Noise Voltage (µV) Right channel to Left channel 20 VDD=12V RL=8Ω Ci=1µF AUX-0025 AES-17(20kHz) A-Weighting 1k Frequency (Hz) VDD=12V RL=4Ω Ci=1µF AUX-0025 AES-17(20kHz) A-Weighting Mono Mode 20 +22 +19.5 +17 +14.5 +12 20 VDD=12V RL=8Ω PO=0.6W Ci=1µF AUX-0025 100 Gain, AV=22dB +0 -20 Gain (dB) Gain (dB) Phase, AV=34dB +29.5 Phase, AV=34dB +22 Gain, AV=22dB +17 -60 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 Phase, AV=22dB +24.5 +19.5 -40 1k 10k Frequency (Hz) +27 +14.5 +12 20 -80 100k 9 100 VDD=12V RL=4Ω PO=1.1W Ci=1µF AUX-0025 Mono Mode 1k 10k Frequency (Hz) +80 +60 +40 +20 +0 -20 -40 -60 -80 -100 -120 -140 -160 -180 100k Phase (Degree) +24.5 +20 Phase (Degree) +27 10k 20k Gain, AV=34dB +32 +40 Phase, AV=22dB 1k Frequency (Hz) +34.5 +60 +29.5 100 Frequency Response Gain, AV=34dB +32 AV=16dB +37 +80 +34.5 10k 20k AV=34dB AV=22dB 100µ Frequency Response +37 1k Frequency (Hz) AV=28dB 10µ 10k 20k 100 Output Noise Voltage vs. Frequency 1m AV=16dB AV=22dB 100 Left channel to Right channel AV=34dB AV=28dB 20 -80 -120 10k 20k Output Noise Voltage vs. Frequency 10µ -60 -70 -110 1m 100µ -40 -50 -90 -100 Right channel to Left channel 100 VDD=12V RL=8Ω PO=0.6W Ci=1µF Av=22dB AUX-0025 AES-17(20kHz) -20 Left channel to Right channel -120 20 Crosstalk vs. Frequency +0 -10 VDD=12V RL=4Ω PO=1W Ci=1µF Av=22dB AUX-0025 AES-17(20kHz) Crosstalk (dB) Crosstalk (dB) Crosstalk vs. Frequency +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 www.anpec.com.tw APA2615 Typical Operating Characteristics (Cont.) Inter-Modulation Performance Inter-Modulation Performance +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 VDD=12V RL=8Ω PO=1W Ci=1µF AV=22dB fin=19kHz&20kHz, 1:1 BW=22~22kHz AUX-0025 60 100 200 VDD=12V RL=4Ω PO=1W Ci=1µF AV=22dB fin=19kHz&20kHz, 1:1 BW=22~22kHz AUX-0025 Mono Mode FFT (dBr) FFT (dBr) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 500 1k 2k 5k 10k 20k Frequency (Hz) 60 100 -20 -30 -10 -20 -30 -40 CMRR (dB) CMRR (dB) +0 VDD=12V RL=8Ω Ci=1µF VO=1Vrms AUX-0025 AES-17(20kHz) -10 -50 -60 AV=34dB -70 AV=22dB -80 -50 -60 AV=34dB -70 AV=22dB -90 -10 -20 -30 -40 -50 100 1k Frequency (Hz) -10020 10k 20k +0 VDD=12V RL=8Ω Ci=1µF AV=22dB Vrr=0.2Vrms Input AC short to GND AUX-0025 AES-17(20kHz) -10 -20 -30 -60 -40 -50 -70 -80 -80 -90 -90 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 1k Frequency (Hz) 10k 20k -100 20 10k 20k 10 VDD=12V RL=4Ω Ci=1µF AV=22dB Vrr=0.2Vrms Input AC short to GND AUX-0025 AES-17(20kHz) Mono Mode -60 -70 -100 20 100 PSRR vs. Frequency PSRR vs. Frequency PSRR (dB) 20 +0 PSRR (dB) -40 VDD=12V RL=4Ω Ci=1µF VO=1Vrms AUX-0025 AES-17(20kHz) Mono Mode -80 -90 -100 10k 20k CMRR vs. Frequency CMRR vs. Frequency +0 1k Frequency (Hz) 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2615 Typical Operating Characteristics (Cont.) Shutdown Attenuation vs. Frequency Shutdown Attenuation (dB) Mute Attenuation (dB) Mute Attenuation vs. Frequency +0 -10 VDD=12V R =8Ω -20 CL=1µF i -30 AV=22dB V -40 O=2Vrms AUX-0025 -50 AES-17(20kHz) -60 -70 -80 -90 -100 Left Channel Right Channel -110 -120 -130 20 100 1k Frequency (Hz) 10k 20k +0 VDD=12V -10 RL=8Ω -20 Ci=1µF -30 AV=22dB VO=2Vrms -40 AUX-0025 -50 AES-17(20kHz) -60 -70 -80 -90 -100 Left Channel -110 Right Channel -120 -130 20 100 1k 10k 20k Frequency (Hz) Supply Current vs. Output Power Supply Current vs. Output Power 1.4 1 0.8 Supply Current (A) Supply Current (A) 1.0 VDD=8V 0.8 0.6 RL=4Ω+33µH fin=1kHz Ci=1µF AV=22dB THD+N≦1% AUX-0025 AES-17(20kHz) 0.4 0.2 0 0 12 4 6 8 10 2 Each Channel Output Power (W) VDD=8V 0.5 0.4 RL=8Ω+33µH fin=1kHz Ci=1µF AV=22dB THD+N≦1% AUX-0025 AES-17(20kHz) 0.3 0 14 0 1.6 Supply Current (mA) RL=4Ω+33µH fin=1kHz Ci=1µF AV=22dB THD+N≦1% Mono Mode AUX-0025 AES-17(20kHz) 0.4 5 10 15 10 12 14 20 VDD=8V 0.2 8 No Load 1.2 0.6 6 Supply Current vs. Supply Voltage VDD=12V 0.8 4 25 1.4 1.0 2 Each Channel Output Power (W) VDD=5V 1.8 Supply Current (A) VDD=12V 0.6 0.2 Supply current vs. Output power 0 0.7 0.1 2.0 0 VDD=16V 0.9 VDD=12V 1.2 20 25 10 5 0 30 l Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 15 11 0 2 4 6 8 10 12 14 Supply Voltage (V) 16 18 www.anpec.com.tw APA2615 Typical Operating Characteristics (Cont.) Mute Current vs. Supply Voltage Shutdown Current vs. Supply Voltage 5 1.5 No Load No Load 4 Supply Current (µA) Supply Current (mA) 1.2 0.9 0.6 3 2 1 0.3 0 0 2 4 6 8 10 12 Supply Voltage (V) 14 16 0 18 0 4 6 8 10 12 14 16 18 Supply Voltage (V) Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage 20 20 DRC 2 Mode Non-Clip Mode 10 10 DRC 1 Mode DRC 2 Mode 5 Output Voltage (V) Output Voltage (V) 2 2 1 VDD=12V VPMAX=0.5V Ci=1µF AV=46dB AUX-0025 AES-17(20kHz) 500m 200m 1m 10m 100m Input Voltage (V) Non-Clip Mode 5 DRC 1 Mode 2 1 VDD=12V VPMAX=1V Ci=1µF AV=46dB AUX-0025 AES-17(20kHz) 500m 200m 1 1m 10m 100m Input Voltage (V) 1 Input Voltage vs. Output Voltage 20 DRC 2 Mode Output Voltage (V) 10 5 Non-Clip Mode 2 DRC 1 Mode 1 VDD=12V VPMAX=1.3V Ci=1µF AV=46dB AUX-0025 AES-17(20kHz) 500m 200m 1m 10m 100m 1 Input Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 12 www.anpec.com.tw APA2615 Typical Operating Characteristics (Cont.) Power On Power Off VDD VDD 1 1 OUTP & OUTN OUTP & OUTN 2&3 2&3 M1 OUTPUT OUTPUT M1 CH1: VDD, 10V/Div, DC CH2: OUTP, 5V/Div, DC CH3: OUTN, 5V/Div, DC CHM1: OUTPUT, 5V/Div, DC TIME: 200ms/Div CH1: VDD, 10V/Div, DC CH2: OUTP, 5V/Div, DC CH3: OUTN, 5V/Div, DC CHM1: OUTPUT, 5V/Div, DC TIME: 100ms/Div Shutdown Shutdown Release SD SD 1 1 OUTP & OUTN OUTP & OUTN 2&3 2&3 OUTPUT OUTPUT M1 M1 CH1: SD, 2V/Div, DC CH2: OUTP, 5V/Div, DC CH3: OUTN, 5V/Div, DC CHM1: OUTPUT, 5V/Div, DC TIME: 200ms/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 CH1: SD, 2V/Div, DC CH2: OUTP, 5V/Div, DC CH3: OUTN, 5V/Div, DC CHM1: OUTPUT, 5V/Div, DC TIME: 200ms/Div 13 www.anpec.com.tw APA2615 Pin Description PIN NO. NAME I/O/P FUNCTION 1 AVDD P Power supply for control block. 2 3V3REG O Regulator output, 3.3V. Only for internal used. 3 LINP I The positive input of left channel amplifier. 4 LINN I The negative input of left channel amplifier. 5 VREF P The reference voltage output. 6 RINN I The negative input of right channel amplifier. 7 RINP I The positive input of right channel amplifier. 8 AGND P Ground connection for control block. 9 PMAX I Input for set the power limit function. Enable: PO(MAX)=(1.65-VPMAX)x11.23, Disable: GND. 10,16 RPVDD P The power supply for right channel Class-D amplifier. 11,12 ROUTP O The positive output of right channel Class-D amplifier. 13 RPGND P Ground connection for right channel Class-D amplifier. 14,15 ROUTN O The negative output of right channel Class-D amplifier. 17 SD I Shutdown mode control input, place entire IC in shutdown mode when held low. 18 PFLAG O Protection flag output (open drain). 19 MUTE I Mute mode control input; pull low to mute the Class-D amplifier’s output. 20 OSCO O The internal oscillator’s output, for synchronization other APA2615s. 21 OSCIN I External clock input. 22 DRC0 I Non-clip and DRC (Dynamic Range Compress) control; LSB bit 0. 23 DRC1 I Non-clip and DRC (Dynamic Range Compress) control; MSB bit 1. 24 GAIN0 I Control pin for internal gain setting, LSB, bit0. 25 GAIN1 I Control pin for internal gain setting, MSB, bit1. 26,32 LPVDD P The power supply for left channel Class-D amplifier. 27,28 LOUTN O The negative output of left channel Class-D amplifier. 29 LPGND P Ground connection for left channel Class-D amplifier. 30,31 LOUTP O The positive output of left channel Class-D amplifier. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 14 www.anpec.com.tw APA2615 Block Diagram RPVDD VINT VINT Gate Drive VINT ROUTN RINN Power Limit RPGND VINT RINP Gate Drive PMAX AGND ROUTP RPVDD VREF Biases & Reference MUTE VINT Mute Control AVDD 3V3REG DRC0 DRC1 3.3V regulator DRC/NonClip Control Protection Function GAIN Control OSCIN Oscillator OSCO GAIN0 Shutdown Control GAIN1 PFLAG SD PMAX LPVDD VINT PMAX MUTE VINT Gate Drive VINT LOUTN LINN Power Limit LPGND VINT LINP Gate Drive LOUTP LPVDD Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 15 www.anpec.com.tw APA2615 Typical Application Circuits VDD VDD VDD 26 LPVDD 27 LOUTN 28 LOUTN CS4 1µF 29 LPGND 30 LOUTP 31 LOUTP 32 LPVDD CS3 1µF CS1 220µF VDD CS2 0.1µF Left Channel Input Signal Left Channel Input Signal Ci1 1µF AVDD 1 25 GAIN1 C1 3V3REG 2 1µF 24 GAIN0 LINP 3 23 DRC1 Ci2 1µF LINN 4 22 DRC0 CB 0.1µF VREF 5 RINN 6 20 OSCO Ci3 1µF RINP 7 19 MUTE AGND 8 18 PFLAG PMAX 9 17 SD Ci4 1µF APA2615 No Clip and DRC Control 21 OSCIN RPVDD 16 ROUTN 15 ROUTN 14 RPGND 13 ROUTP 11 ROUTP 12 RPVDD 10 VDD CS6 1µF Clock Output Mute Control 3V3REG 120K PFLAG CS5 1µF External Clock Shutdown Control R1 R2 Gain Setting Protection Flag VDD Stereo Operation Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 16 www.anpec.com.tw APA2615 Typical Application Circuits (Cont.) VDD VDD 26 LPVDD 28 LOUTN 29 LPGND 31 LOUTP 220µF 32 LPVDD CS1 30 LOUTP CS3 1µF VDD 27 LOUTN CS4 1µF VDD CS2 AVDD 1 0.1µF 3V3REG 2 C1 1µF 24 GAIN0 LINP 3 23 DRC1 Ci2 1µF LINN 4 22 DRC0 CB 0.1µF VREF 5 Ci1 1µF Input Signal 25 GAIN1 21 OSCIN APA2615 RINN 6 20 OSCO RINP 7 19 MUTE AGND 8 18 PFLAG PMAX 9 17 SD CS5 1µF 120K PFLAG Protection Flag VDD No Clip and DRC Control External Clock Clock Output Mute Control Shutdown Control RPVDD 16 ROUTN 15 ROUTN 14 RPGND 13 ROUTP 12 3V3REG ROUTP 11 R2 RPVDD 10 R1 Gain Setting CS6 1µF VDD Monaural Operation Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 17 www.anpec.com.tw APA2615 Function Description 3.3V Regulator Operation Class D Operation Output = 0V VOUTP The 3V3REG regulates the voltage at 3.3V and only for internal circuit used. And connect a capacitor from 1µF to VOUTN 4.7µF (X5R or above) for stable. (0.8µF or more should be secured including its variation and temperature change.) VOUT (VOUTP-VOUTN) Reference Voltage The voltage output of VREF pin is equal to V3V3REG/2 and needs to connect a capacitor of 0.1µF for voltage IOUT Output > 0V stabilization. VOUTP Gain Setting Operation VOUTN Table 1. The gain setting VOUT (VOUTP-VOUTN) IOUT Output < 0V VOUTP VOUTN VOUT (VOUTP-VOUTN) IOUT GAIN1 GAIN0 DRC1 DRC0 Gain 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 X X X X 1 1 1 1 0 0 0 0 1 1 1 1 X X X X 22dB 28dB 34dB 16dB 34dB 40dB 46dB 28dB 34dB 40dB 46dB 28dB The APA2615’s gain can be set by GAIN0, GAIN1. The Figure 1. The APA2615 Output Waveform (Voltage& detail gain setting value is list at table 1. Current) Mute Operation The APA2615 power amplifier modulation scheme is shown in figure 1. The outputs VOUTP and VOUTN are in phase At mute state, the Class-D output will be forced at 50% duty at OUTP and OUTN, so differential is zero, and output signals have be disabled. The recovery time of mute with each other when no input signals. When output > 0V, the duty cycle of VOUTP is greater than 50% and VOUTN is state to normal operation is about 1ms (max.). less than 50%; when Output <0V, the duty cycle of VOUTP is less than 50% and VOUTN is greater than 50%. This method Shutdown Operation reduces the switching current across the load and reduces the I 2R losses in the load that improves the In order to reduce power consumption while not in use, the APA2615 contains a shutdown function to externally amplifier’s efficiency. This modulation scheme has very short pulses across turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD the load, this making the small ripple current and very little loss on the load, and the LC filter can be eliminated pin for APA2615. The trigger point between a logic high and logic low level is typically 1.5V. It is the best to switch in most applications. Added the LC filter can increase the efficiency by filter the ripple current. between the ground and the supply voltage VDD to provide maximum device performance. By switching the SD pin to low level, the amplifier enters a low-consumption- Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 18 www.anpec.com.tw APA2615 Function Description (Cont.) Shutdown Operation (Cont.) seconds to release the non-clip function from -12dB to 0dB. current state, IDD for APA2615 is in the shutdown mode. The Non-clip operation should be switched under poweroff or shut down mode to prevent the pop noise between On normal operating, APA2615’s SD pin should pull to a high level to keep the IC out of the shutdown mode. The the mode switching. SD pin should be tied to a definite voltage to avoid unwanted state change. DRC Operation Oscillator Operation OSCI PIN Mode OSCO 0 fixed Internal fixed clock mode Internal fixed clock output 1 fixed Internal spread clock mode (5) Internal spread clock output External clock mode External clock buffer output Clock in DRC1 DRC0 Mode 0 0 Normal mode (DRC mode off , Non-clip mode off) 0 1 Non-Clip mode 1 0 DRC 1 mode 1 1 DRC 2 mode DR C 1 m o d e : DR C [ 1 : 0 ] = 1 0 ( DR C 1 = H i g h , an d DRC0=Low), the DRC 1 mode is active. The gain is in- When the OSCI pin pulls low, the APA2615 works at internal fixed clock mode, and OSCO pin is output that fixed creasing by 12dB compared to the normal mode. The power limit value is the point that active the Dynamic Range clock (500kHz); when the OSCI pin pulls high, the APA2615 works at internal spread clock mode, and the clock range Compression function, and the maximum attenuation is -12dB. The attack time is zero second and needs 3.9 is from 400kHz to 600kHz; the OSCO pin is the buffer for output these spread clock. seconds to release the non-clip function from -12dB to 0dB. Apply the external clock to the OSCI pin, the APA2615 will work at external clock mode, and the external clock should DRC2 mode: DRC [1:0]=11(DRC1=High, and DRC0=High), similar to the DRC 1 mode, but not perform the power at the range from 400kHz to 600kHz and the duty cycle should be at range from 40% to 60%, and the OSCO is the external clock’s output buffer. limit function. The DRC operation should be switched under power-off Power Limit Operation or shut down mode to prevent the pop noise between the mode switching. This function limits the maximum output power of APA2615 for prevent exceeding the maximum power of speaker. Stereo/Mono Switching Operation When connects the RINN and RINP to 3V3REG before Except DRC 2 mode, this function is always enabled. The setting value can be a voltage divider by resistor that power-on, the APA2615 will enter the monaural operational when power-on. In this operation, the output of connects 3V3REG and GND. The maximum power limit value (peak voltage) = (1.65VPMAX)x11.23. ROUTP should connect to LOUTP for positive output, and the ROUN should connect to LOUTN for negative output, Non-Clip Operation the input signal will via LINN and LINP to input the APA2615. This mode can increase more output power compared to the stereo mode single channel’s output power. When the DRC [1:0]=01(DRC1=Low, and DRC0=High), the non-clip mode is active. The gain is increasing by 12dB compared to the normal mode. The output peak Multi-APA2615 Synchronization Operation voltage becomes the power limit value. If the peak voltage excesses the power limit value, it will be attenuated The external clock synchronization function and the clock output function are prepared and the use of master/slave to the power limit value, and the maximum attenuation is -12dB. The attack time is zero second and needs 7.7 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 configuration realizes carrier clock synchronization. 19 www.anpec.com.tw APA2615 Function Description (Cont.) Multi-APA2615 Synchronization Operation (Cont.) Thermal Protection When using it with multi chips synchronized, one is used The thermal protection has two modes to prevent the APA2615 from being destroyed by over temperature. as a master chip and the other is used as a slave chip. At this time, connect OSCO pin of a master chip to OSCI pin When the junction temperature exceeds 155°C and under the 165°C, the APA2615 will limit the output power by of a slave chip. When using 3 pieces of APA2615 (master/ slave1/slave2), connect OSCO terminal of a slave1 chip to OSCI pin of a slave2 chip. 6dB to lower the temperature. This calls thermal limit mode. When the junction temperature falls down to Protection Flag Operation 130°C, the thermal limit state will be cancelled. When junction temperature exceeds 165°C, the Class-D Protection Function PFLAG Class-D Latch Output Output State Cancellation output would turn-off, and the PFLAG pin will pull-low. This calls thermal mute mode. All the state will be can- DC Detection Low Yes Weak low Shutdown or Power-Off celled when junction lower than 130°C. Some conditions, like VDD=5V, RL=4Ω, can’t meet spec P O=14W because IC UVLO High-Z - Weak low - Over Current Protection into thermal shutdown. Output power curve use dot line to indicate thermal limit. Low Yes Weak low Shutdown or Power-Off Thermal protection (power limit) - No Power limit (-6dB) Thermal protection (class-D off) Low No Weak low Shutdown or Power-Off or Lower temperature Shutdown or Power-Off or Low temperature DC Detection Operation When a DC signal applies to the input of APA2615 and the time excesses 0.5s, APA2615 will turn-off the Class-D output, and the PFLAG pin will pull low. This function protects the speaker to be destroyed by large DC offset. At mute mode, the DC detection function will be disabled. The DC detection state will latch and need power-off or shut down to release the protection. Connect PFLAG to SD pin, the DC detection will be auto recovery. Over-Current Protection The APA2615 monitors the output current. When the current exceeds the current-limit threshold, the APA2615 turnoff the output to prevent the IC from being damaged in over-current or short-circuit condition, and the APA2615 will latch at this state until shutdown or power-off to release the over-current protection. PFLAG will pull-high when the protection occurs. Connect PFLAG to SD pin, the over-current protection will be auto recovery. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 20 www.anpec.com.tw APA2615 Application Information Square Wave into the Speaker Output Low-Pass Filter Apply the square wave into the speaker may cause the If the traces form APA2615 to speaker are short, it doesn’t require output filter for FCC & CE standard. voice coil of speaker jump out the air gap and deface the voice coil. However, it depends on the amplitude of square A ferrite bead may need if it’s failing the test for FCC or CE tested without the LC filter. The figure 2 is the sample for wave is high enough and the bandwidth of speaker is higher than the square wave’s frequency. For 500kHz added ferrite bead; the ferrite shows choosing high impedance in high frequency. switching frequency, this is not issue for the speaker because the frequency is beyond the audio band, and can’t significantly move the voice coil, as cone movement is proportional to 1/f2 for frequency out of audio band. Ferrite VOUTP Bead Input Resistance, Ri 1nF The APA2615’s input resistor is fixed and the value is 18.8kΩ. The input resistance has wide variation (+/-15%) which is being caused by manufacture. Ferrite Bead VOUTN Input Capacitor, Ci 4Ω 1nF In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the Figure 2. Ferrite bead output filter input impedance Ri form a high-pass filter with the corner Figure 3 and Figure 4 are examples for added the LC filter frequency determined in the following equation: fC(highpass ) = 1 2πRiCi (Butterworth), it’s recommended for the situation that the trace form amplifier to speaker is too long, and needs to (1) eliminate the radiated emission or EMI. The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Where Ri is 18.8kΩ and the specification calls for a flat bass response down to 40Hz. The equation is reconfigured OUTP 33µH as below: 1 Ci = 2πRifc (2) 1µF When the input resistance variation is considered, the Ci is 0.22µF, so a value in the range of 0.22µF to 1.0µF OUTN would be chosen. A further consideration for this capacitor is the leakage path from the input source through the 33µH 8Ω 1µF input network (Ri + Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low- Figure 3. LC output filter for 8Ω speaker Inductor :TOKO 11RHBP A7503AY-330M leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifiers’ inputs in most applications because the DC level of the ampliers’inputs is held at V3V3REG/2. Please note that it is important to confirm the capacitor polarity in the application. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 21 www.anpec.com.tw APA2615 Application Information (Cont.) Output Low-Pass Filter (Cont.) Layout Recommendation In high power Class-D power amplifier, a correct layout is important to ensure proper operation of the amplifier and avoid the switch noise radiation. In general, interconnect- OUTP 22µH ing impedance should be minimized by using short and wide printed circuit traces. Especial for the high slew rate 2.2µF OUTN 22µH output PWM signal to speaker, these loops should be as small as possible. 4Ω 1.All components should be placed close to the APA2615. For example, the input capacitor (Ci) should be close to 2.2µF APA2615’s input pins to avoid causing noise coupling to APA2615’s high impedance inputs; the decoupling capacitor (CS) should be placed by the APA2615’s power pin to decouple the power rail noise. Figure 4. LC output filter for 4Ω speaker Inductor :TOKO 11RHBP A7503AY-220M 2.The output traces should be short, wide, (>50mil) and symmetric, and this loop like the figure 5, should be as Figure 3 and 4’s low pass filter cut-off frequency are 25kHz (FC). Power-Supply Decoupling Capacitor, CS VDD VDD tween the amplifier and the speaker. The optimum decoupling is achieved by using two differ- 1µF 28 LOUTN 32 LPVDD low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length be- 31 LOUTP 1µF fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as 27 LOUTN The APA2615 is a high-performance CMOS audio ampli- 26 LPVDD (3) 29 LPGND 2π LC small as possible, (this loop is high slew rate and high current path). 30 LOUTP fC(lowpass) = 1 APA2615 ent types of capacitors that target on different types of noise on the power supply leads. For higher frequency Figure 5. APA2615 Output Topology transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, 3. The input trace should be short and symmetric. typically 0.1µF placed as close as possible to the device AVDD pin and 1mF placed to the LPVDD and RPVDD leads 4. The power trace width should greater than 50mil. 5. The QFN5.2x6.2-32 Thermal PAD should be soldered for works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 220µF or greater on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area. placed near the audio power amplifier is recommended. Like the figure 6 illustrate. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 22 www.anpec.com.tw APA2615 Application Information (Cont.) Layout Recommendation (Cont.) 4.0mm Thermal Via Diameter 0.3mm X 12 1.15mm 4.3mm 0.5mm 5.0mm 0.25mm 3.3mm Solder Mask to Prevent Short Circuit Ground Plane for ThermalPAD Figure 6. QFN5.2x6.2-32 Land Pattern Recommendation Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 23 www.anpec.com.tw APA2615 Package Information QFN5.2x6.2-32 A E D b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e S Y M B O L A A1 QFN5.2x6.2-32 MILLIMETERS INCHES MIN. MAX. MIN. MAX. 0.80 1.00 0.031 0.039 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 6.10 6.30 0.240 0.248 D2 4.20 4.60 0.165 0.181 0.209 0.142 E 5.10 5.30 0.201 E2 3.20 3.60 0.126 0.70 0.020 e 0.50 BSC L 0.50 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 0.020 BSC 0.028 0.008 24 www.anpec.com.tw APA2615 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.0±2.00 50 MIN. QFN5.2x6.2-32 P0 4.0±0.10 T1 P1 8.0±0.10 C d D W E1 12.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 P2 D0 2.0±0.10 1.5+0.10 -0.00 D1 1.5 MIN. T A0 B0 F 5.5±0.10 K0 0.6+0.00 -0.40 5.60±0.20 6.6±0.20 1.30±0.20 (mm) Devices Per Unit Package Type Unit Quantity QFN5.2x6.2-32 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 25 www.anpec.com.tw APA2615 Taping Direction Information QFN5.2x6.2-32 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 26 www.anpec.com.tw APA2615 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 27 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2615 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2011 28 www.anpec.com.tw