Application Note, V1.0, Nov. 2007 AP90000 CIC310 Design Guideline for CIC310 Board Layout Microcontrollers Edition 2008-02-15 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2008. All Rights Reserved. LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. AP90000 Design Guideline for CIC310 Board Layout AP90000 Revision History: 2007-10 Previous Version: none Page V1.0 Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Application Note 3 V1.0, 2007-10 AP90000 Design Guideline for CIC310 Board Layout Table of Contents Page 1 1.1 1.2 Overview ........................................................................................................................................5 General Informations:......................................................................................................................5 Pinout of CIC310 .............................................................................................................................5 2 2.1 2.2 PCB Design Recommendations ..................................................................................................6 Decoupling ......................................................................................................................................7 Decoupling Capacitor List: ............................................................................................................11 Application Note 4 V1.0, 2007-10 AP90000 Design Guideline for CIC310 Board Layout Overview 1 Overview The CIC310 is a communication controller IC in PG-TQFP-64 pin package This ApNote gives recommendations concerning electromagnetic compatibility and the power supply system which can lead to a successful PCB design. In additional to the Infineon PCB Design Guidelines for Microcontrollers (AP24026), which gives general design rule information for PCB design, some product-specific recommendations and guidelines for CIC310 are discussed here. 1.1 General Informations: The communication controller CIC310 has two supply voltage domains of 3.3V (VDDP) for Ports and 1.5V (VDD) for the logic. The two supply domains VDD and VDDP should be decoupled individually. 1.2 Pinout of CIC310 Figure 1 Pin-out of CIC310 Application Note 5 V1.0, 2007-10 AP90000 Design Guideline for CIC310 Board Layout PCB Design Recommendations 2 PCB Design Recommendations ! To minimize the EMI radiation on the PCB the following signals have to be considered as critical: - Clock signals (especially for ERAY interface). - Supply pins Route these signals with adjacent ground reference and avoid signal and reference layer changes. Route them as short as possible. Routing ground on each side can help to reduce coupling to the other signals. ! For unused “Output, Supply, Input and I/O “ pins following points must be considered: 1. Supply Pins (Modules) : - See product specification 2. I/O-Pins: - should be configured as output and driven to static low in the weakest driver mode. - solderpad should be left open and not be connected to any other net (layout isolated PCB-pad only for soldering) 3. Output Pins : - should be driven static in the weakest driver mode. - If static output level is not possible, the output driver should be disabled. - solderpad should be left open and not be connected to any other net (layout isolated PCB-pad only for soldering) 4.Input Pins without internal pull device: - For pins with alternate function see product target specification to define the necessary logic level - must be connected with high-ohmic resistor to GND (range 10k – 1Meg) - groups of 8 pins can be used to reduce number of external pullup/down devices (keep in mind leakage current) 5. Input Pins with internal pull device: - For pins with alternate function see product specification to define the necessary logic level - should be configured as Pull-down (exception: if the product specification requires high level for alternate functions) - solderpad should not be connected to any other net (isolated PCB-pad only for soldering) ! The ground system must be designed as follows: - Separate digital and oscillator grounds. 1. Ground for OSC (VSSOSC Island), 2. Ground for digital (GND) ! To reduce the radiation / coupling from oscillator circuit, a separated ground island on the GND layer should be made. This ground island can be connected at one point to the GND layer. This helps to keep noise generated by the oscillator circuit isolated on this separated island. The ground connections of the load capacitors and VSSOSC should also be connected to this island. Traces for load capacitors and Crystal should be as short as possible. ! The power distribution from the regulator to each power plane should be made over filters (EMI filter using ferrite beads). Application Note 6 V1.0, 2007-10 AP90000 Design Guideline for CIC310 Board Layout PCB Design Recommendations ! A low inductance/resistance decoupling capacitors to the supply pins is required. ! Inductance/ferrite beads in the range L ~ 5-10µH should be inserted in the supply paths at the regulator output. ! Select weakest possible driver strengths and slew rates for all I/Os. ! Use lowest possible frequency for the CLK driver. ! Avoid cutting the GND plane by via groups. A solid GND plane must be designed. 2.1 Decoupling ! All supply domains of CIC310 should be decoupled separately (see decoupling layout example in Figure 2 and 3). ! Type of capacitors: – Values: 10 nF, 47 nF, 100 nF, 2.2 µF – X7R Ceramic Multilayer (Low ESR and low ESL) ! All power pins (supplied from Voltage Regulator) should be connected first to the dedicated decoupling capacitor and then from the capacitors over vias to the power planes. ! All VSS pins should be connected to the GND layer (see layout example in Figure 2 and 3). ! Multiple vias can be used at capacitors to get a low impedance connection between capacitors and power/GND planes or pins. ! All capacitors must be placed as close as possible to the related supply pin group. ! Two decaps (2.2µF //100nF and 5.11 Ohm resistor should be connected to the VDDAPLL / VSSAPLL pins (see Fig. 5) ! Keep in mind the specification regarding the VDDAPLL pin to limit the maximum peak-to-peak noise to 10mV and to a frequency of 200 kHz. A power-plane/grounding concept example for a CIC310 microcontroller can be seen in Figure 2 and 3. Application Note 7 V1.0, 2007-10 Figure 2 Application Note 8 VDDC Plane on Bottom layer See Fig. 4 for Oscillator layout VDD from VR VDDP from VR Resistor on top layer Decaps on Top layer Via to VDD Vias to GND VDDP Decaps on Bottom layer VDDP Plane on Bottom layer GND Plane on Top Layer Via Capacitor VDDAPLL VSSAPLL VSSOSC VDDPOSC VDD VDDP GND AP90000 Design Guideline for CIC310 Board Layout PCB Design Recommendations Layout Example for Decoupling of CIC310 for double side placement V1.0, 2007-10 Figure 3 Application Note 9 VDD Plane on Bottom layer See Fig. 4 for Oscillator layout VDD from VR VDDP from VR Resistor on top layer GND VDDP Plane on Bottom layer GND Plane on Top Layer Via Capacitor VDDAPLL VSSAPLL VSSOSC VDDPOSC VDD VDDP AP90000 Design Guideline for CIC310 Board Layout PCB Design Recommendations Layout Example for Decoupling of CIC310 for single side placement V1.0, 2007-10 AP90000 Design Guideline for CIC310 Board Layout PCB Design Recommendations GND Plane Crystal Separated GND island on toplayer (carved out from global GND layer) Load capacitors Vias to GND island XTALin/out Via to global GND layer Figure 4 VSSosc µC Layout Example for Oscillator Circuit 5.11 OHM VDDAPLL (Pin 10) VDDC 100nF 2.2µF VSSAPLL (Pin 9) Figure 5 Circuit at VDDAPLL and VSSAPLL pins Application Note 10 V1.0, 2007-10 AP90000 Design Guideline for CIC310 Board Layout PCB Design Recommendations 2.2 Decoupling Capacitor List: Capacitor 100 nF // 10 nF 100 nF // 10 nF 100 nF // 10 nF 100 nF // 10 nF 100 nF // 47 nF // 10nF 100 nF // 47 nF // 10nF 2.2 µF // 100 nF 100 nF Application Note Supply VDDP VDDP VDDP VDDP VDD VDD VDDAPLL / VSSAPLL VDDPOSC / VSSOSC 11 CIC310 Pin (P-TQFP-64) 7 26 41 55 24 57 10 / 9 14 / 11 V1.0, 2007-10 http://www. inf ineon.com Published by Infineon Technologies AG