HT32F1755/HT32F1765/HT32F2755 User Manual

Holtek 32-bit Microcontroller with ARM® Cortex™-M3 Core
HT32F1755/HT32F1765/HT32F2755
User Manual
Revision: V1.00
Date: ���������������
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table of Contents
1 Introduction............................................................................................................ 22
Overview............................................................................................................................... 22
Features................................................................................................................................ 23
Block Diagram...................................................................................................................... 27
2 Document Conventions........................................................................................ 28
3 System Architecture.............................................................................................. 29
ARM® CortexTM-M3 Processor.............................................................................................. 29
Bus Architecture.................................................................................................................... 31
Memory Organization........................................................................................................... 31
Memory Map.................................................................................................................................... 32
Embedded Flash Memory................................................................................................................ 34
Embedded SRAM Memory.............................................................................................................. 34
AHB Peripherals.............................................................................................................................. 35
APB Peripherals.............................................................................................................................. 35
4 Flash Memory Controller (FMC)........................................................................... 36
Introduction........................................................................................................................... 36
Features................................................................................................................................ 36
Function Descriptions........................................................................................................... 37
Flash Memory Map.......................................................................................................................... 37
Flash Memory Architecture.............................................................................................................. 38
Wait State Setting............................................................................................................................ 38
Booting Configuration...................................................................................................................... 39
Page Erase...................................................................................................................................... 40
Mass Erase...................................................................................................................................... 41
Word Programming.......................................................................................................................... 42
Option Byte Description................................................................................................................... 43
Page Erase/Program Protection...................................................................................................... 44
Security Protection........................................................................................................................... 45
Register Map........................................................................................................................ 46
Register Descriptions............................................................................................................ 47
Flash Target Address Register – TADR........................................................................................... 47
Flash Write Data Register – WRDR................................................................................................ 48
Flash Operation Command Register – OCMR................................................................................ 49
Flash Operation Control Register – OPCR...................................................................................... 50
Flash Operation Interrupt Enable Register – OIER......................................................................... 51
Flash Operation Interrupt and Status Register – OISR................................................................... 52
Flash Page Erase/Program Protection Status Register – PPSR..................................................... 54
Flash Security Protection Status Register – CPSR......................................................................... 55
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Device Information................................................................................................................ 26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Vector Mapping Control Register – VMCR............................................................................ 56
Flash Cache and Pre-fetch Control Register – CFCR..................................................................... 57
SRAM Booting Vector Register n – SBVTn, n=0~3......................................................................... 59
5 Power Control Unit (PWRCU)............................................................................... 60
Introduction........................................................................................................................... 60
Function Descriptions........................................................................................................... 61
Backup Domain............................................................................................................................... 61
3.3V Power Domain......................................................................................................................... 62
1.8V Power Domain......................................................................................................................... 63
Operation Modes............................................................................................................................. 63
Register Map........................................................................................................................ 66
Register Descriptions............................................................................................................ 67
Backup Domain Status Register – BAKSR...................................................................................... 67
Backup Domain Control Register – BAKCR.................................................................................... 68
Backup Domain Test Register – BAKTEST..................................................................................... 70
HSI Ready Counter Control Register – HSIRCR............................................................................. 71
Low Voltage/Brown Out Detect Control and Status Register – LVDCSR........................................ 72
Backup Register n – BAKREGn, n=0~9.......................................................................................... 74
6 Clock Control Unit (CKCU)................................................................................... 75
Introduction........................................................................................................................... 75
Features................................................................................................................................ 76
Functional Descriptions........................................................................................................ 76
High Speed External Crystal Oscillator – HSE................................................................................ 76
Phase Locked Loop – PLL............................................................................................................... 78
Low Speed External Crystal Oscillator – LSE.................................................................................. 80
Low Speed Internal RC Oscillator – LSI.......................................................................................... 80
Clock Ready Flag............................................................................................................................ 81
System Clock Selection – CK_SYS................................................................................................. 81
HSE Clock Monitor.......................................................................................................................... 81
Clock Output Capability................................................................................................................... 81
Register Map........................................................................................................................ 82
Register Descriptions............................................................................................................ 83
Global Clock Configuration Register – GCFGR............................................................................... 83
Global Clock Control Register – GCCR........................................................................................... 85
Global Clock Status Register – GCSR............................................................................................ 87
Global Clock Interrupt Register – GCIR........................................................................................... 88
PLL Configuration Register – PLLCFGR......................................................................................... 90
PLL Control Register – PLLCR........................................................................................................ 91
AHB Configuration Register – AHBCFGR....................................................................................... 92
AHB Clock Control Register – AHBCCR......................................................................................... 93
APB Configuration Register – APBCFGR........................................................................................ 95
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Features................................................................................................................................ 61
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
APB Clock Control Register 0 – APBCCR0..................................................................................... 96
APB Clock Control Register 1 – APBCCR1..................................................................................... 98
Clock Source Status Register – CKST.......................................................................................... 100
Low Power Control Register – LPCR............................................................................................ 101
MCU Debug Control Register – MCUDBGCR............................................................................... 102
Introduction......................................................................................................................... 104
Functional Descriptons....................................................................................................... 104
Power On Rest.............................................................................................................................. 104
System Reset................................................................................................................................ 105
AHB and APB Unit Reset............................................................................................................... 105
Register Map...................................................................................................................... 105
Register Descriptions.......................................................................................................... 106
Global Reset Status Register – GRSR.......................................................................................... 106
AHB Peripheral Reset Register – AHBPRSTR.............................................................................. 107
APB Peripheral Reset Register 0 – APBPRSTR0......................................................................... 108
APB Peripheral Reset Register 1 – APBPRSTR1..........................................................................110
8 General Purpose I/O (GPIO)................................................................................ 112
Introduction......................................................................................................................... 112
Features.............................................................................................................................. 113
Functional Descriptions...................................................................................................... 113
Default GPIO Pin Configuration......................................................................................................113
General Purpose I/O – GPIO..........................................................................................................113
GPIO Locking Mechanism..............................................................................................................115
Register Map...................................................................................................................... 115
Register Descriptions.......................................................................................................... 117
Port A Data Direction Control Register – PADIRCR.......................................................................117
Port A Input Function Enable Control Register – PAINER..............................................................118
Port A Pull-Up Selection Register – PAPUR...................................................................................119
Port A Pull-Down Selection Register – PAPDR............................................................................. 120
Port A Open Drain Selection Register – PAODR........................................................................... 121
Port A Output Current Drive Selection Register – PADRVR.......................................................... 122
Port A Lock Register – PALOCKR................................................................................................. 123
Port A Data Input Register – PADINR............................................................................................ 124
Port A Output Data Register – PADOUTR..................................................................................... 125
Port A Output Set/Reset Control Register – PASRR..................................................................... 126
Port A Output Reset Register – PARR........................................................................................... 127
Port B Data Direction Control Register – PBDIRCR...................................................................... 128
Port B Input Function Enable Control Register – PBINER............................................................ 129
Port B Pull-Up Selection Register – PBPUR................................................................................. 130
Port B Pull-Down Selection Register – PBPDR............................................................................. 131
Port B Open Drain Selection Register – PBODR.......................................................................... 132
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7 Reset Control Unit (RSTCU)............................................................................... 104
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
9 Alternate Function I/O Control Unit (AFIO)........................................................ 169
Introduction......................................................................................................................... 169
Features.............................................................................................................................. 170
Functional Descriptions...................................................................................................... 170
External Interrupt Pin Selection..................................................................................................... 170
Alternate Function.......................................................................................................................... 171
Register Map...................................................................................................................... 171
Register Descriptions.......................................................................................................... 172
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Port B Lock Register – PBLOCKR................................................................................................. 133
Port B Data Input Register – PBDINR........................................................................................... 134
Port B Output Data Register – PBDOUTR.................................................................................... 135
Port B Output Set/Reset Control Register – PBSRR..................................................................... 136
Port B Output Reset Register – PBRR.......................................................................................... 137
Port C Data Direction Control Register – PCDIRCR..................................................................... 138
Port C Input Function Enable Control Register – PCINER............................................................ 139
Port C Pull-Up Selection Register – PCPUR................................................................................. 140
Port C Pull-Down Selection Register – PCPDR............................................................................ 141
Port C Open Drain Selection Register – PCODR.......................................................................... 142
Port C Lock Register – PCLOCKR................................................................................................ 143
Port C Data Input Register – PCDINR........................................................................................... 144
Port C Output Data Register – PCDOUTR.................................................................................... 145
Port C Output Set/Reset Control Register – PCSRR.................................................................... 146
Port C Output Reset Register – PCRR.......................................................................................... 147
Port D Data Direction Control Register – PDDIRCR..................................................................... 148
Port D Input Function Enable Control Register – PDINER............................................................ 149
Port D Pull-Up Selection Register – PDPUR................................................................................. 150
Port D Pull-Down Selection Register – PDPDR............................................................................ 151
Port D Open Drain Selection Register – PDODR.......................................................................... 152
Port D Lock Register – PDLOCKR................................................................................................ 153
Port D Data Input Register – PDDINR........................................................................................... 154
Port D Output Data Register – PDDOUTR.................................................................................... 155
Port D Output Set/Reset Control Register – PDSRR.................................................................... 156
Port D Output Reset Register – PDRR.......................................................................................... 157
Port E Data Direction Control Register – PEDIRCR...................................................................... 158
Port E Input Function Enable Control Register – PEINER............................................................ 159
Port E Pull-Up Selection Register – PEPUR................................................................................. 160
Port E Pull-Down Selection Register – PEPDR............................................................................. 161
Port E Open Drain Selection Register – PEODR.......................................................................... 162
Port E Output Current Drive Selection Register – PEDRVR......................................................... 163
Port E Lock Register – PELOCKR................................................................................................. 164
Port E Data Input Register – PEDINR........................................................................................... 165
Port E Output Data Register – PEDOUTR.................................................................................... 166
Port E Output Set/Reset Control Register – PESRR..................................................................... 167
Port E Output Reset Register – PERR.......................................................................................... 168
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
10 Nested Vectored Interrupt Controller (NVIC)................................................... 194
Introduction......................................................................................................................... 194
Features.............................................................................................................................. 197
Functional Descriptions...................................................................................................... 197
SysTick Calibration........................................................................................................................ 197
Register Map...................................................................................................................... 197
11 External Interrupt/Event Controller (EXTI)....................................................... 199
Introduction......................................................................................................................... 199
Features.............................................................................................................................. 199
Functional Descriptions...................................................................................................... 200
Wake-up Event Management........................................................................................................ 200
External Interrupt/Event Line Mapping.......................................................................................... 200
Interrupt and Debounce................................................................................................................. 200
Register Map...................................................................................................................... 201
Register Descriptions.......................................................................................................... 202
EXTI Interrupt Configuration Register n – EXTICFGRn, n=0~15.................................................. 202
EXTI Interrupt Control Register – EXTICR.................................................................................... 203
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR................................................................. 204
EXTI Interrupt Edge Status Register – EXTIEDGESR.................................................................. 205
EXTI Interrupt Software Set Command Register – EXTISSCR..................................................... 206
EXTI Interrupt Wake-up Control Register – EXTIWAKUPCR........................................................ 207
EXTI Interrupt Wake-up Polarity Register – EXTIWAKUPPOLR................................................... 208
EXTI Interrupt Wake-up Flag Register – EXTIWAKUPFLG........................................................... 209
12 Analog to Digital Converter (ADC)................................................................... 210
Introduction......................................................................................................................... 210
Features.............................................................................................................................. 211
Functional Description........................................................................................................ 212
ADC Clock Setup........................................................................................................................... 212
Channel Selection.......................................................................................................................... 212
Conversion Mode........................................................................................................................... 212
Start Conversion Trigger Sources.................................................................................................. 216
Sampling Time Setting................................................................................................................... 216
Data Alignment.............................................................................................................................. 216
Analog Watchdog.......................................................................................................................... 217
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EXTI Source Selection Register 0 – ESSR0................................................................................. 172
EXTI Source Selection Register 1 – ESSR1................................................................................. 173
GPIO A Configuration Register – GPACFGR................................................................................ 174
GPIO B Configuration Register – GPBCFGR................................................................................ 178
GPIO C Configuration Register – GPCCFGR............................................................................... 182
GPIO D Configuration Register – GPDCFGR............................................................................... 186
GPIO E Configuration Register – GPECFGR................................................................................ 190
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Interrupts........................................................................................................................................ 217
PDMA Request.............................................................................................................................. 218
Register Map...................................................................................................................... 218
Register Descriptions.......................................................................................................... 220
13 Operational Amplifier/Comparator (OPA/CMP)............................................... 241
Introduction......................................................................................................................... 241
Features.............................................................................................................................. 241
Functional Descriptions...................................................................................................... 242
Functional Diagram........................................................................................................................ 242
Interrupts and Status..................................................................................................................... 242
Offset Cancellation Procedures..................................................................................................... 243
Register Map...................................................................................................................... 243
Register Descriptions.......................................................................................................... 244
Operational Amplifier Control Register n – OPACRn, n=0 or 1...................................................... 244
Comparator Input Offset Voltage Cancellation Register n – OFVCRn, n=0 or 1........................... 245
Comparator Interrupt Enable Register n – CMPIERn, n=0 or 1.................................................... 246
Comparator Raw Status Register n – CMPRSRn, n=0 or 1.......................................................... 247
Comparator Masked Interrupt Status Register n – CMPISRn, n=0 or 1........................................ 248
Comparator Interrupt Clear Register n – CMPICLRn, n=0 or 1..................................................... 249
14 General-Purpose Timers (GPTM0 & GPTM1).................................................. 250
Introduction......................................................................................................................... 250
Features.............................................................................................................................. 251
Functional Descriptions...................................................................................................... 252
Counter Mode................................................................................................................................ 252
Clock Controller............................................................................................................................. 255
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ADC Reset Register – ADCRST.................................................................................................... 220
ADC Regular Conversion Mode Register – ADCCONV................................................................ 221
ADC Regular Conversion List Register 0 – ADCLST0.................................................................. 222
ADC Regular Conversion List Register 1 – ADCLST1.................................................................. 224
ADC Input n Offset Register – ADCOFRn, n=0~7......................................................................... 226
ADC Input Sampling Time Register n – ADCSTRn, n=0~7........................................................... 227
ADC Regular Conversion Data Register n – ADCDRn, n=0~7...................................................... 228
ADC Regular Trigger Control Register – ADCTCR........................................................................ 229
ADC Regular Trigger Source Register – ADCTSR........................................................................ 230
ADC Watchdog Control Register – ADCWCR............................................................................... 231
ADC Watchdog Lower Threshold Register – ADCLTR.................................................................. 233
ADC Watchdog Upper Threshold Register – ADCUTR................................................................. 234
ADC Interrupt Mask Enable Register – ADCIMR........................................................................... 235
ADC Interrupt Raw Status Register – ADCIRAW.......................................................................... 236
ADC Interrupt Masked Status Register – ADCIMASK................................................................... 237
ADC Interrupt Clear Register – ADCICLR..................................................................................... 239
ADC PDMA Request Register – ADCDMAR................................................................................. 240
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Map...................................................................................................................... 279
Register Descriptions.......................................................................................................... 280
Timer Counter Configuration Register – CNTCFR........................................................................ 280
Timer Mode Configuration Register – MDCFR.............................................................................. 282
Timer Trigger Configuration Register – TRCFR............................................................................. 285
Timer Counter Register – CTR...................................................................................................... 287
Channel 0 Input Configuration Register – CH0ICFR..................................................................... 288
Channel 1 Input Configuration Register – CH1ICFR..................................................................... 290
Channel 2 Input Configuration Register – CH2ICFR..................................................................... 292
Channel 3 Input Configuration Register – CH3ICFR..................................................................... 294
Channel 0 Output Configuration Register – CH0OCFR................................................................ 296
Channel 1 Output Configuration Register – CH1OCFR................................................................ 298
Channel 2 Output Configuration Register – CH2OCFR................................................................ 300
Channel 3 Output Configuration Register – CH3OCFR................................................................ 302
Channel Control Register – CHCTR.............................................................................................. 304
Channel Polarity Configuration Register – CHPOLR..................................................................... 305
Timer PDMA/Interrupt Control Register – DICTR.......................................................................... 306
Timer Event Generator Register – EVGR...................................................................................... 308
Timer Interrupt Status Register – INTSR....................................................................................... 310
Timer Counter Register – CNTR................................................................................................... 312
Timer Prescaler Register – PSCR................................................................................................. 313
Timer Counter Reload Register – CRR......................................................................................... 314
Channel 0 Capture/Compare Register – CH0CCR....................................................................... 315
Channel 1 Capture/Compare Register – CH1CCR....................................................................... 316
Channel 2 Capture/Compare Register – CH2CCR....................................................................... 317
Channel 3 Capture/Compare Register – CH3CCR....................................................................... 318
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Trigger Controller........................................................................................................................... 256
Slave Controller............................................................................................................................. 258
Restart Mode................................................................................................................................. 258
Master Controller........................................................................................................................... 261
Channel Controller......................................................................................................................... 262
Capture Counter Value Transferred to CHxCCR........................................................................... 263
Pulse Width Measurement............................................................................................................. 264
Input Stage.................................................................................................................................... 265
Output Stage.................................................................................................................................. 266
Update Management..................................................................................................................... 269
Quadrature Decoder...................................................................................................................... 270
Digital Filter.................................................................................................................................... 272
Clearing CHxOREF when ETIF is high.......................................................................................... 272
Single Pulse Mode......................................................................................................................... 273
Timer Interconnection.................................................................................................................... 275
Trigger ADC Start.......................................................................................................................... 278
PDMA Request.............................................................................................................................. 278
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
15 Basic Function Timer (BFTM)........................................................................... 319
Introduction......................................................................................................................... 319
Features.............................................................................................................................. 319
Functional Description........................................................................................................ 320
Register Map...................................................................................................................... 322
Register Descriptions.......................................................................................................... 323
BFTMn Control Register – BFTMnCR, n=0~1............................................................................... 323
BFTMn Status Register – BFTMnSR, n=0~1................................................................................ 324
BFTMn Counter Register – BFTMnCNTR, n=0~1......................................................................... 325
BFTMn Compare Value Register – BFTMnCMPR, n=0~1............................................................ 326
16 Motor Control Timer (MCTM)............................................................................ 327
Introduction......................................................................................................................... 327
Features.............................................................................................................................. 328
Function Descriptions......................................................................................................... 329
Counter Mode................................................................................................................................ 329
Center-Align Counting................................................................................................................... 331
Repetition Down-counter Operation.............................................................................................. 332
Clock Controller............................................................................................................................. 333
Trigger Controller........................................................................................................................... 334
Slave Controller............................................................................................................................. 336
Master Controller........................................................................................................................... 338
Channel Controller......................................................................................................................... 339
Input Stage.................................................................................................................................... 342
Output Stage.................................................................................................................................. 343
Update Management..................................................................................................................... 351
Quadrature Decoder...................................................................................................................... 353
Digital Filter.................................................................................................................................... 355
Clearing CHxOREF when ETIF is high.......................................................................................... 355
Single Pulse Mode......................................................................................................................... 356
Timer Interconnection.................................................................................................................... 358
Trigger ADC Start.......................................................................................................................... 362
Lock Level Table............................................................................................................................ 362
PDMA Request.............................................................................................................................. 363
Register Map...................................................................................................................... 364
Register Description........................................................................................................... 365
Timer Counter Configuration Register – CNTCFR........................................................................ 365
Timer Mode Configuration Register – MDCFR.............................................................................. 367
Timer Trigger Configuration Register – TRCFR............................................................................. 370
Timer Counter Register – CTR...................................................................................................... 372
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Repetitive Mode............................................................................................................................. 320
One Shot Mode.............................................................................................................................. 321
Trigger ADC Start.......................................................................................................................... 322
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
17 Real Time Clock (RTC)...................................................................................... 411
Introduction......................................................................................................................... 411
Features.............................................................................................................................. 411
Functional Descriptions...................................................................................................... 412
RTC Related Register Reset......................................................................................................... 412
Reading RTC Register................................................................................................................... 412
Low Speed Clock Configuration.................................................................................................... 412
RTC Counter Operation................................................................................................................. 413
Interrupt and Wakeup Control........................................................................................................ 413
RTCOUT Output Pin Configuration............................................................................................... 414
Register Map...................................................................................................................... 415
Register Descriptions.......................................................................................................... 415
RTC Counter Register – RTCCNT................................................................................................. 415
RTC Compare Register – RTCCMP.............................................................................................. 416
RTC Control Register – RTCCR.................................................................................................... 417
RTC Status Register – RTCSR..................................................................................................... 419
RTC Interrupt and Wakeup Enable Register – RTCIWEN............................................................. 420
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Channel 0 Input Configuration Register – CH0ICFR..................................................................... 373
Channel 1 Input Configuration Register – CH1ICFR..................................................................... 375
Channel 2 Input Configuration Register – CH2ICFR..................................................................... 377
Channel 3 Input Configuration Register – CH3ICFR..................................................................... 379
Channel 0 Output Configuration Register – CH0OCFR................................................................ 381
Channel 1 Output Configuration Register – CH1OCFR................................................................ 383
Channel 2 Output Configuration Register – CH2OCFR................................................................ 385
Channel 3 Output Configuration Register – CH3OCFR................................................................ 387
Channel Control Register – CHCTR.............................................................................................. 389
Channel Polarity Configuration Register – CHPOLR..................................................................... 391
Channel Break Configuration Register – CHBRKCFR.................................................................. 393
Channel Break Control Register – CHBRKCTR............................................................................ 394
Timer PDMA/Interrupt Control Register – DICTR.......................................................................... 396
Timer Event Generator Register – EVGR...................................................................................... 398
Timer Interrupt Status Register – INTSR....................................................................................... 400
Timer Counter Register – CNTR................................................................................................... 403
Timer Prescaler Register – PSCR................................................................................................. 404
Timer Counter Reload Register – CRR......................................................................................... 405
Timer Repetition Register – REPR................................................................................................ 406
Channel 0 Capture/Compare Register – CH0CCR....................................................................... 407
Channel 1 Capture/Compare Register – CH1CCR....................................................................... 408
Channel 2 Capture/Compare Register – CH2CCR....................................................................... 409
Channel 3 Capture/Compare Register – CH3CCR....................................................................... 410
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
18 Watchdog Timer (WDT)..................................................................................... 421
Introduction......................................................................................................................... 421
Features.............................................................................................................................. 422
Functional Description........................................................................................................ 422
Register Map...................................................................................................................... 424
Watchdog Timer Control Register – WDTCR................................................................................ 424
Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 425
Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 426
Watchdog Timer Status Register – WDTSR.................................................................................. 427
Watchdog Timer Protection Register – WDTPR............................................................................ 428
2
2
19 Inter-Integrated Circuit (I C0 & I C1)................................................................ 429
Introduction......................................................................................................................... 429
Features.............................................................................................................................. 430
Functional Description........................................................................................................ 430
Two Wire Serial Interface............................................................................................................... 430
START and STOP Conditions........................................................................................................ 430
Data Validity................................................................................................................................... 431
Addressing Format........................................................................................................................ 432
Data Transfer and Acknowledge.................................................................................................... 434
Clock Synchronization................................................................................................................... 435
Arbitration...................................................................................................................................... 435
General Call Addressing................................................................................................................ 436
Bus Error........................................................................................................................................ 436
Address Mask................................................................................................................................ 436
Address Snoop.............................................................................................................................. 436
Operation Mode............................................................................................................................. 437
Holding SCL Line Conditions......................................................................................................... 442
I2C Timeout Function..................................................................................................................... 443
PDMA Interface.............................................................................................................................. 443
Register Map...................................................................................................................... 444
Register Description........................................................................................................... 445
I2Cn Control Register – I2CnCR, n=0 or 1..................................................................................... 445
I2Cn Interrupt Enable Register – I2CnIER, n=0 or 1...................................................................... 447
I2Cn Address Register – I2CnADDR, n=0 or 1.............................................................................. 449
I2Cn Status Register – I2CnSR, n=0 or 1...................................................................................... 450
I2Cn SCL High Period Generation Register – I2CnSHPGR, n=0 or 1........................................... 453
I2Cn SCL Low Period Generation Register – I2CnSLPGR, n=0 or 1............................................. 454
I2Cn Data Register – I2CnDR, n=0 or 1......................................................................................... 455
I2Cn Target Address Register – I2CnTAR, n=0 or 1....................................................................... 456
I2Cn Address Mask Register – I2CnADDMR, n=0 or 1.................................................................. 457
I2Cn Address Snoop Register – I2CnADDSR, n=0 or 1................................................................. 458
I2Cn Timeout Register – I2CnTOUT, n=0 or 1................................................................................ 459
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Register Descriptions.......................................................................................................... 424
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
20 Serial Peripheral Interface (SPI0 & SPI1)......................................................... 460
Introduction......................................................................................................................... 460
Features.............................................................................................................................. 461
Functional Description........................................................................................................ 461
Register Map...................................................................................................................... 470
Register Description........................................................................................................... 471
SPIn Control Register 0 – SPInCR0, n=0 or 1............................................................................... 471
SPIn Control Register 1 – SPInCR1, n=0 or 1............................................................................... 472
SPIn Interrupt Enable Register – SPInIER, n=0 or 1..................................................................... 474
SPIn Clock Prescaler Register – SPInCPR, n=0 or 1.................................................................... 476
SPIn Data Register – SPInDR, n=0 or 1........................................................................................ 477
SPIn Status Register – SPInSR, n=0 or 1..................................................................................... 478
SPIn FIFO Control Register – SPInFCR, n=0 or 1........................................................................ 480
SPIn FIFO Status Register – SPInFSR, n=0 or 1.......................................................................... 482
SPIn FIFO Time Out Counter Register – SPInFTOCR, n=0 or 1................................................... 483
21 Universal Synchronous Asynchronous Receiver Transmitter (USART0 &
USART1)................................................................................................................... 484
Introduction......................................................................................................................... 484
Features.............................................................................................................................. 485
Functional Descriptions...................................................................................................... 486
Serial Data Format......................................................................................................................... 486
Baud Rate Generation................................................................................................................... 487
IrDA Mode...................................................................................................................................... 488
RS485 Mode.................................................................................................................................. 490
Synchronous Mode........................................................................................................................ 492
Hardware Flow Control.................................................................................................................. 494
Interrupts and Status..................................................................................................................... 495
PDMA Interface.............................................................................................................................. 495
Register Map...................................................................................................................... 496
Register Descriptions.......................................................................................................... 497
USARTn Receiver Buffer Register – RBRn, n=0 or 1.................................................................... 497
USARTn Transmitter Buffer Register – TBRn, n=0 or 1................................................................ 498
USARTn Interrupt Enable Register – IERn, n=0 or 1.................................................................... 499
USARTn Interrupt Identification Register – IIRn, n=0 or 1............................................................. 500
USARTn FIFO Control Register – FCRn, n=0 or 1........................................................................ 502
USARTn Line Control Register – LCRn, n=0 or 1......................................................................... 504
USARTn Modem Control Register – MODCRn, n=0 or 1.............................................................. 506
USARTn Line Status Register – LSRn, n=0 or 1........................................................................... 507
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Master Mode.................................................................................................................................. 461
Slave Mode.................................................................................................................................... 462
SPI Serial Frame Format............................................................................................................... 462
Status Flags................................................................................................................................... 467
PDMA Interface.............................................................................................................................. 470
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
22 Smart Card Interface (SCI)................................................................................ 519
Introduction......................................................................................................................... 519
Features.............................................................................................................................. 519
Function Descriptions......................................................................................................... 520
Elementary Time Unit Counter....................................................................................................... 520
Guard Time Counter...................................................................................................................... 523
Waiting Time Counter.................................................................................................................... 523
Card Clock and Data Selection...................................................................................................... 524
SCI Data Transfer Mode................................................................................................................ 525
Interrupt Generator........................................................................................................................ 527
PDMA Interface.............................................................................................................................. 528
Register Map...................................................................................................................... 528
Register Descriptions.......................................................................................................... 529
SCI Control Register – CR............................................................................................................. 529
SCI Status Register – SR.............................................................................................................. 531
SCI Contact Control Register – CCR............................................................................................. 533
SCI Elementary Time Unit Register – ETUR................................................................................. 534
SCI Guard Time Register – GTR................................................................................................... 535
SCI Waiting Time Register – WTR................................................................................................ 536
SCI Interrupt Enable Register – IER.............................................................................................. 537
SCI Interrupt Pending Register – IPR............................................................................................ 539
SCI Transmit Buffer – TXB............................................................................................................ 541
SCI Receive Buffer – RXB............................................................................................................. 542
SCI Prescaler Register – PSCR.................................................................................................... 543
23 USB Device Controller...................................................................................... 544
Introduction......................................................................................................................... 544
Features.............................................................................................................................. 544
Functional Description........................................................................................................ 545
Endpoints....................................................................................................................................... 545
EP-SRAM...................................................................................................................................... 545
Serial Interface Engine – SIE......................................................................................................... 546
Double-Buffering............................................................................................................................ 547
Suspend Mode and Wake-Up........................................................................................................ 548
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USARTn Modem Status Register – MODSRn, n=0 or 1............................................................... 509
USARTn Timing Parameter Register – TPRn, n=0 or 1................................................................ 510
USARTn Mode Register – MDRn, n=0 or 1....................................................................................511
USARTn IrDA Control Register – IrDACRn, n=0 or 1.................................................................... 512
USARTn RS485 Control Register – RS485CRn, n=0 or 1............................................................ 514
USARTn Synchronous Control Register – SYNCRn, n=0 or 1...................................................... 515
USARTn FIFO Status Register – FSRn, n=0 or 1......................................................................... 516
USARTn Divider Latch Register – DLRn, n=0 or 1........................................................................ 517
USARTn Debug/Test Register – DEGTSTRn, n=0 or 1................................................................. 518
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Map...................................................................................................................... 548
Register Descriptions.......................................................................................................... 550
24 Peripheral Direct Memory Access (PDMA)...................................................... 579
Introduction......................................................................................................................... 579
Features.............................................................................................................................. 579
Functional Description........................................................................................................ 580
AHB Master................................................................................................................................... 580
PDMA Channel.............................................................................................................................. 580
Channel transfer............................................................................................................................ 580
Channel Priority............................................................................................................................. 581
Transfer Request........................................................................................................................... 582
Address Mode................................................................................................................................ 582
Auto-Reload................................................................................................................................... 582
Transfer Interrupt........................................................................................................................... 583
Register Descriptions.......................................................................................................... 586
PDMA Channel n Control Register – PDMACHnCR, n=0~11....................................................... 586
PDMA Channel n Source Address Register – PDMACHnSADR, n=0~11..................................... 588
PDMA Channel n Destination Address Register – PDMACHnDADR, n=0~11.............................. 589
PDMA Channel n Current Address Register – PDMACHnCADR, n=0~11.................................... 590
PDMA Channel n Transfer Size Register – PDMACHnTSR, n=0~11............................................ 591
PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n=0~11............................ 592
PDMA Interrupt Status Register 0 – PDMAISR0........................................................................... 593
PDMA Interrupt Status Register 1 – PDMAISR1........................................................................... 595
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USB Control and Status Register – USBCSR............................................................................... 550
USB Interrupt Enable Register – USBIER..................................................................................... 552
USB Interrupt Status Register – USBISR...................................................................................... 554
USB Frame Count Register – USBFCR........................................................................................ 556
USB Device Address Register – USBDEVA.................................................................................. 557
USB Endpoint 0 Control and Status Register – USBEP0CSR...................................................... 558
USB Endpoint 0 Interrupt Enable Register – USBEP0IER............................................................ 560
USB Endpoint 0 Interrupt Status Register – USBEP0ISR............................................................. 562
USB Endpoint 0 Transfer Count Register – USBEP0TCR............................................................ 564
USB Endpoint 0 Configuration Register – USBEP0CFGR............................................................ 565
USB xth Type A Endpoint Control and Status Register – USBEAxCSR, x=1~3............................. 566
USB xth Type A Endpoint Interrupt Enable Register – USBEAxIER, x=1~3................................... 568
USB xth Type A Endpoint Interrupt Status Register – USBEAxISR, x=1~3.................................... 569
USB xth Type A Endpoint Transfer Count Register – USBEAxTCR, x=1~3................................... 570
USB xth Type A Endpoint Configuration Register – USBEAxCFGR, x=1~3................................... 571
USB yth Type B Endpoint Control and Status Register – USBEByCSR, y=1~4............................. 572
USB yth Type B Endpoint Interrupt Enable Register – USBEByIER, y=1~4.................................. 575
USB yth Type B Endpoint Interrupt Status Register – USBEByISR, y=1~4................................... 576
USB yth Type B Endpoint Transfer Count Register – USBEByTCR, y=1~4................................... 577
USB yth Type B Endpoint Configuration Register – USBEByCFGR, y=1~4.................................. 578
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
PDMA Interrupt Status Clear Register 0 – PDMAISCR0............................................................... 597
PDMA Interrupt Status Clear Register 1 – PDMAISCR1............................................................... 598
PDMA Interrupt Enable Register 0 – PDMAIER0.......................................................................... 599
PDMA Interrupt Enable Register 1 – PDMAIER1.......................................................................... 600
25 CMOS Sensor Interface (CSIF, for HT32F2755 Only)...................................... 601
Features.............................................................................................................................. 601
Function Descriptions......................................................................................................... 602
CSIF Signal.................................................................................................................................... 602
CSIF Frame Timing........................................................................................................................ 602
Pixel Data Format.......................................................................................................................... 604
Window Capture............................................................................................................................ 605
Row & Column Sub-Sampling....................................................................................................... 607
PDMA Data Transmission – Trigger PDMA by Rx......................................................................... 609
Interrupts and Status..................................................................................................................... 609
Register Map...................................................................................................................... 611
Register Description........................................................................................................... 612
CSIF Enable Register – CSIFENR ............................................................................................... 612
CSIF Control Register – CSIFCR ................................................................................................. 613
CSIF Image Width and Height Register – CSIFIMGWH ............................................................... 614
CSIF Window Capture Register 0 – CSIFWCR0 .......................................................................... 615
CSIF Window Capture Register 1 – CSIFWCR1 .......................................................................... 616
CSIF Sub-Sample Register – CSIFSMP ...................................................................................... 617
CSIF Column Sub-Sample Register – CSIFSMPCOL .................................................................. 618
CSIF Row Sub-Sample Register – CSIFSMPROW ..................................................................... 619
CSIF FIFO Register n – CSIFFIFOn, n=0~7 ................................................................................ 620
CSIF Interrupt Enable Register – CSIFIER .................................................................................. 621
CSIF Status Register – CSIFSR ................................................................................................... 622
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Introduction......................................................................................................................... 601
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
List of Tables
Rev. 1.00
1. HT32F1755/1765/2755 Series Features and Peripheral List.................................................... 26
2. Document Conventions............................................................................................................. 28
3. HT32F1755/1765/2755 Register Map....................................................................................... 33
4. Flash Memory and Option Byte................................................................................................. 38
5. Relationship between wait state cycle and HCLK..................................................................... 38
6. Booting Modes.......................................................................................................................... 39
7. Option Byte Memory Map......................................................................................................... 43
8. Access Permission of Protected Main Flash Page.................................................................... 44
9. Access Permission When Security Protection Is Enabled........................................................ 45
10. FMC Register Map.................................................................................................................. 46
11. Operation Mode Definitions..................................................................................................... 63
12. Enter/Exit Power Saving Modes.............................................................................................. 64
13. Power Status After System Reset........................................................................................... 65
14. PWRCU Register Map............................................................................................................ 66
15. Output Divider 2 Setting.......................................................................................................... 79
16. Feedback Divider 2 value Setting........................................................................................... 79
17. CKOUT Clock Source............................................................................................................. 81
18. CKCU Register Map................................................................................................................ 82
19. RSTCU Register Map........................................................................................................... 105
20. AFIO, GPIO and I/O Pad Control Signal True Table..............................................................115
21. Register map of GPIO............................................................................................................115
22. AFIO Register Map................................................................................................................ 171
23. Exception Types.................................................................................................................... 194
24. NVIC Register Map............................................................................................................... 197
25. EXTI Register Map................................................................................................................ 201
26. A/D Converter Register Map................................................................................................. 218
27. OPA/CMP Functional Signal Definition................................................................................. 242
28. OPA/CMP Register Map........................................................................................................ 243
29. Counting Direction and Encoding Signals............................................................................. 271
30. GPTM Register Map............................................................................................................. 279
31. GPTM Internal Trigger Connection....................................................................................... 286
32. BFTM Register Map.............................................................................................................. 322
33. Compare Match Output Setup.............................................................................................. 344
34. Output Control Bits for Complementary Output with a Break Event Occurrence.................. 350
35. Counting Direction and Encoding Signals............................................................................. 354
36. Lock Level Table................................................................................................................... 362
37. MCTM Register Map............................................................................................................. 364
38. MCTM Internal Trigger Connection....................................................................................... 371
39. LSE Startup Mode Operating Current and Startup Time....................................................... 412
40. RTCOUT Output Mode and Active Level Setting.................................................................. 414
41. RTC Register Map................................................................................................................ 415
42. WDT Register Map................................................................................................................ 424
43. Conditions of Holding SCL line.............................................................................................. 442
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HT32F1755/HT32F1765/HT32F2755
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I2C Register Map................................................................................................................... 444
I2C Clock Setting Example.................................................................................................... 454
SPI Interface Format Setup................................................................................................... 462
SPI Mode Fault Trigger conditions........................................................................................ 469
SPI Master Mode SEL Pin Status......................................................................................... 469
SPI Register Map.................................................................................................................. 470
Baud Rate Error calculation – CK_USART=72MHz.............................................................. 487
USART Register Map............................................................................................................ 496
USART Interrupt Control Function........................................................................................ 501
DI Field Based Di Encoded Decimal Values.......................................................................... 521
FI Field Based Fi Encoded Decimal Values.......................................................................... 521
Possible ETU Values Obtained with the Fi/Di Ratio............................................................... 521
SCI Register Map ................................................................................................................. 528
Endpoint Characteristics....................................................................................................... 545
USB Data Types and Buffer Size.......................................................................................... 545
USB Register Map................................................................................................................ 548
Resume Event Detection...................................................................................................... 551
PDMA Channel Assignments................................................................................................ 580
PDMA Address Modes.......................................................................................................... 582
PDMA Register Map.............................................................................................................. 583
CSIF Signals......................................................................................................................... 602
CSIF_MCK Output Setup – refer to the CKCU Chapter....................................................... 602
Pixel Data Format – without Window-capturing and Sub-sampling...................................... 604
Window Capture Setting....................................................................................................... 605
Row & Column Sub-sampling Setting................................................................................... 607
Interrupts and Status............................................................................................................. 610
Interrupts Status.................................................................................................................... 610
CSIF Register Map.................................................................................................................611
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table of Contents
Rev. 1.00
1. HT32F1755/1765/2755 Block Diagram................................................................................... 27
2. Cortex™-M3 Block Diagram.................................................................................................... 30
3. HT32F1755/1765/2755 Bus Architecture................................................................................ 31
4. HT32F1755/1765/2755 Memory Map...................................................................................... 32
5. Flash Memory Controller Block Diagram................................................................................. 36
6. Flash Memory Map.................................................................................................................. 37
7. Vector Remapping................................................................................................................... 39
8. Page Erase Operation Flowchart............................................................................................ 40
9. Mass Erase Operation Flowchart............................................................................................ 41
10. Word Programming Operation Flowchart.............................................................................. 42
11. PWRCU Block Diagram......................................................................................................... 60
12. CKCU Block Diagram............................................................................................................ 75
13. External HSE Crystal, Ceramic, and Resonator.................................................................... 76
14. PLL Block Diagram................................................................................................................ 78
15. External Crystal, Ceramic, and Resonator for LSE............................................................... 80
16. RSTCU Block Diagram........................................................................................................ 104
17. Power On Reset Sequence................................................................................................. 105
18. GPIO Block Diagram............................................................................................................112
19. AFIO/GPIO Control Signal....................................................................................................114
20. AFIO Block Diagram............................................................................................................ 169
21. EXTI Channel Input Selection............................................................................................. 170
22. EXTI Block Diagram............................................................................................................ 199
23. EXTI Wake-up Event Management..................................................................................... 200
24. EXTI Debounce Function.................................................................................................... 201
25. ADC Block Diagram............................................................................................................. 210
26. One Shot Conversion Mode................................................................................................ 213
27. Continuous Conversion Mode............................................................................................. 214
28. Discontinuous Conversion Mode......................................................................................... 215
29. Simplied Block Diagram of OPA/CMP with Digital I/O......................................................... 241
30. OPA/CMP Functional Diagram............................................................................................ 242
31. GPTM Block Diagram.......................................................................................................... 250
32. Up-counting Example.......................................................................................................... 252
33. Down-counting Example...................................................................................................... 253
34. Center-aligned Counting Example....................................................................................... 254
35. GPTM Clock Selection Source............................................................................................ 256
36. Trigger Control Block........................................................................................................... 257
37. Slave Controller Diagram.................................................................................................... 258
38. GPTM in Restart Mode........................................................................................................ 258
39. GPTM in Pause Mode......................................................................................................... 259
40. GPTM in Trigger Mode........................................................................................................ 260
41. Master GPTMn and Slave GPTMm/MCTMm Connection................................................... 261
42. MTO Selection..................................................................................................................... 261
43. Capture/Compare Block Diagram........................................................................................ 262
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HT32F1755/HT32F1765/HT32F2755
Rev. 1.00
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Input Capture Mode............................................................................................................. 263
PWM Pulse Width Measurement Example.......................................................................... 264
Channel 0 and Channel 1 Input Stage................................................................................ 265
Channel 2 and Channel 3 Input Stage................................................................................ 266
Output Stage Block Diagram............................................................................................... 266
Toggle Mode Channel Output Reference Signal (CHxPRE=0)........................................... 267
Toggle Mode Channel Output Reference Signal (CHxPRE=1)........................................... 268
PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode............ 268
PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode....... 269
PWM Mode 1 Channel Output Reference Signal and Counter in Centre-align Mode......... 269
Update Event Setting Diagram............................................................................................ 270
Input Stage and Quadrature Decoder Block Diagram......................................................... 271
Both TI0 and TI1 Quadrature Decoder Counting................................................................. 272
GTn_ETI Pin Digital Filter Diagram with N=2...................................................................... 273
Clearing CHxOREF by ETIF................................................................................................ 273
Single Pulse Mode............................................................................................................... 274
Immediate Active Mode Minimum Delay............................................................................. 275
Pausing GPTM1 using the GPTM0 CH0OREF Signal........................................................ 276
Triggering GPTM1 with GPTM0 Update Event.................................................................... 277
Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input.................................................... 278
GPTM PDMA Mapping Diagram.......................................................................................... 279
BFTM Block Diagram.......................................................................................................... 320
BFTM – Repetitive Mode..................................................................................................... 321
BFTM – One Shot Mode...................................................................................................... 322
BFTM – One Shot Mode Counter Updating........................................................................ 323
MCTM Block Diagram......................................................................................................... 328
Up-counting Example.......................................................................................................... 330
Down-counting Example...................................................................................................... 331
Center-aligned Counting Example....................................................................................... 332
Update Event Dependent Repetition Mechanism Example................................................. 333
MCTM Clock Selection Source............................................................................................ 335
Trigger Control Block........................................................................................................... 336
Slave Controller Diagram.................................................................................................... 337
MCTM in Restart Mode....................................................................................................... 337
MCTM in Pause Mode......................................................................................................... 338
MCTM in Trigger Mode........................................................................................................ 338
Master MCTMn and Slave GPTM Connection.................................................................... 339
MTO selection..................................................................................................................... 339
Capture/Compare Block Diagram........................................................................................ 340
Input Capture Mode............................................................................................................. 341
PWM Pulse Width Measurement Example.......................................................................... 342
Channel 0 and Channel 1 Input Stage................................................................................ 343
Channel 2 and Channel 3 Input Stage................................................................................ 343
Output Stage Block Diagram............................................................................................... 344
Toggle Mode Channel Output Reference Signal – CHxPRE=0........................................... 345
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Rev. 1.00
89. Toggle Mode Channel Output Reference Signal – CHxPRE=1........................................... 346
90. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode............ 346
91. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode....... 347
92. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-align Mode......... 347
93. Dead-time Insertion Performed for Complementary Outputs.............................................. 348
94. MT_BRK Pin Digital Filter Diagram with N=2...................................................................... 349
95. Channel 3 Output with a Break Event Occurrence.............................................................. 350
96. Channel 0~2 Complementary Outputs with a Break Event Occurrence............................. 351
97. Channel 0~2 Only One Output Enabled when Fault Event Occurs..................................... 352
98. Hardware Protection When Both CHxO and CHxNO Are in Active Condition..................... 353
99. Update Event 1 Setup Diagram........................................................................................... 355
100. CHxE, CHxNE and CHxOM Updated by Update Event 2................................................. 356
101. Update Event 2 Setup Diagram......................................................................................... 356
102. Input Stage and Quadature Decoder Block Diagram........................................................ 357
103. Both TI0 and TI1 Quadrature Decoder Counting............................................................... 358
104. MTn_ETI Pin Digital Filter Diagram with N=2.................................................................... 359
105. Clearing CHxOREF by ETIF.............................................................................................. 359
106. Single Pulse Mode............................................................................................................. 360
107. Immediate Active Mode Minimum Delay........................................................................... 361
108. Pausing GPTM0 using the MCTM0 CH0OREF Signal...................................................... 362
109. Triggering GPTM0 with MCTM0 Update Event 1.............................................................. 363
110. Trigger MCTM0 and GPTM0 with the MCTM0 CH0 Input................................................. 364
111. CH1XOR Input as Hall Sensor Interface............................................................................ 365
112. MCTM PDMA Mapping Diagram....................................................................................... 367
113. RTC Block Diagram............................................................................................................ 415
114. Watchdog Timer Block Diagram........................................................................................ 425
115. Watchdog Timer Behavior.................................................................................................. 427
116. I2C Module Block Diagram................................................................................................. 433
117. START and STOP Condition.............................................................................................. 435
118. Data Validity....................................................................................................................... 435
119. 7-bit Addressing Mode....................................................................................................... 436
120. 10-bit Addressing Write Transmit Mode............................................................................. 437
121. 10-bit Addressing Read Receive Mode............................................................................. 437
122. I2C Bus Acknowledge........................................................................................................ 438
123. Clock Synchronization during Arbitration........................................................................... 439
124. Two Master Arbitration Procedure..................................................................................... 439
125. Master Transmitter Timing Diagram.................................................................................. 442
126. Master Receiver Timing Diagram...................................................................................... 443
127. Slave Transmitter Timing Diagram.................................................................................... 444
128. Slave Receiver Timing Diagram........................................................................................ 445
129. SCL Timing Diagram.......................................................................................................... 458
130. SPI Block Diagram............................................................................................................ 464
131. SPI Single Byte Transfer Timing Diagram – CPOL=0, CPHA=0....................................... 467
132. SPI Continuous Data Transfer Timing Diagram – CPOL=0, CPHA=0............................... 467
133. SPI Single Byte Transfer Timing Diagram – CPOL=0, CPHA=1....................................... 468
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Rev. 1.00
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SPI Continuous Transfer Timing Diagram – CPOL=0, CPHA=1....................................... 468
SPI Single Byte Transfer Timing Diagram – CPOL=1, CPHA=0....................................... 469
SPI Continuous Data Transfer Timing Diagram – CPOL=1, CPHA=0............................... 469
SPI Single Transfer Timing Diagram – CPOL=1, CPHA=1............................................... 470
SPI Continuous Transfer Timing Diagram – CPOL=1, CPHA=1....................................... 470
SPI Multi-Master Slave Environment................................................................................. 472
USART Block Diagram...................................................................................................... 488
USART Serial Data Format............................................................................................... 490
USART Clock CK_USART and Data Frame Timing.......................................................... 491
USART I/O and IrDA Block Diagram................................................................................. 493
IrDA Modulation and Demodulation................................................................................... 493
RS485 Interface and Waveform........................................................................................ 494
USART Synchronous Transmission Example................................................................... 496
8-bit Format USART Synchronous Waveform................................................................... 497
USART RTS Flow Control................................................................................................. 498
USART CTS flow control................................................................................................... 498
SCI Block Diagram............................................................................................................ 523
Character Frame and Compensation Mode...................................................................... 526
Character and Block Waiting Time Duration – CWT and BWT.......................................... 528
SCI Card Detection Diagram............................................................................................. 529
SCI Interrupt Structure....................................................................................................... 531
USB Block Diagram........................................................................................................... 548
Endpoint Buffer Allocation Example.................................................................................. 550
Double-buffering Operation Example................................................................................ 551
PDMA Block Diagram........................................................................................................ 583
PDMA Channel Arbitration and Scheduling Example........................................................ 585
CSIF Block Diagram.......................................................................................................... 605
VSYNC & HSYNC Timing.................................................................................................. 607
CSIF Frame Timing........................................................................................................... 607
Image Structure................................................................................................................. 608
Proper Window Capture.................................................................................................... 609
Improper Window Capture................................................................................................. 610
Row and Column Sub-sampling Example......................................................................... 612
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
1
Introduction
Overview
The Holtek HT32F1755/1765/2755 series of devices are high performance, low power consumption
32-bit microcontrollers based on the ARM® Cortex™-M3 processor core. The Cortex™-M3 is a
next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller
(NVIC), SysTick timer and advanced debug support.
The HT32F1755/1765/2755 device operates at a frequency of up to 72MHz with a Flash accelerator
to obtain maximum efficiency. It provides 128 kbytes of embedded Flash memory for code/data
storage and up to 64 kbytes of embedded SRAM memory for system operation and application
program usage. A variety of peripherals, such as ADC, I2C, USART, SPI, PDMA, GPTM, MCTM,
SCI, CSIF, USB 2.0 FS, SWJ-DP (Serial Wire/JTAG Debug Port), etc., are also implemented in
the device series. Several power saving modes provide the flexibility for maximum optimization
between wake-up latency and power consumption, an especially important consideration in low
power applications.
The above features make the HT32F1755/1765/2755 device suitable for use in a wide range of
applications, especially in areas such as white goods application control, power monitors, alarm
systems, consumer products, handheld equipment, data logging applications, motor control,
fingerprint recognition and so on.
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Introduction
This user manual provides detailed information including how to use the HT32F1755/1765/2755
series of devices, system and bus architecture, memory organization and peripheral instructions.
The target audiences for this document are software developers, application developers and
hardware developers. For more information regarding pin assignment, package and electrical
characteristics, please refer to the HT32F1755/1765/2755 series datasheet.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Features
Introduction
▀ Core
● 32-bit ARM® Cortex™-M3 processor core
● Up to 72MHz operating frequency
● 1.25 DMIPS/MHz (Dhrystone 2.1)
● Single-cycle multiplication and hardware division
● Integrated Nested Vectored Interrupt Controller (NVIC)
● 24-bit SysTick timer
▀ On-chip memory
● 128KB on-chip Flash memory for instruction/data and options storage
● Up to 64KB on-chip SRAM
● Supports multiple boot modes
▀ Flash Memory Controller
● Flash accelerator to obtain maximum efficiency
● 32-bit word programming with ISP and IAP
● Flash protection capability to prevent illegal access
▀ Reset and Clock Control Units
● Supply supervisor: Power On Reset (POR), Brown Out Detector (BOD) and Programmable
Low Voltage Detector (LVD)
● External 4 to 16MHz crystal oscillator
● External 32,768Hz crystal oscillator
● Internal 8MHz RC oscillator trimmed to 1% accuracy at 3.3V operating voltage and 25ºC
operating temperature
● Internal 32kHz RC oscillator
● Integrated system clock PLL
● Independent clock gating bits for peripheral clock sources
▀ Power management
● Single 3.3V power supply: 2.7V to 3.6V
● Integrated 1.8V LDO regulator for core and peripheral power supply
● VBAT battery power supply for RTC and backup registers
● Three power domains: 3.3V, 1.8V and Backup
● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
▀ Analog to Digital Converter
● 12-bit SAR ADC engine
● Up to 1Msps conversion rate – 1μs at 56MHz, 1.17μs at 72MHz
● 8 external analog input channels
● Supply voltage range: 2.7V~3.6V
● Conversion range: VREF+~VREF▀ Analog Operational Amplifier/Comparator
● Two Operational Amplifiers or Comparator functions which are software configurable
● Supply voltage range: 2.7V~3.6V
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
▀ I/O ports
● Up to 80 GPIOs
● Port A , Port B, Port C, Port D and Port E are mapped as 16 external interrupts – EXTI
● Almost all I/O pins are 5V-tolerant except for pins shared with analog inputs
▀ Basic Function Timer – BFTM
● Two 32-bit compare/match count-up counters – no I/O control features
● One shot mode – counting stops after a match condition
● Repetitive mode – restart counter after a match condition
▀ Motor Control Timer – MCTM
● Single 16-bit up, down, up/down auto-reload counter
● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor
between 1 and 65536
● Input Capture Function
● Compare Match Output
● PWM waveform generation with Edge and Centre – aligned Modes
● Single Pulse Mode Output
● Complementary Outputs with programmable dead-time insertion
● Encoder interface controller with two inputs using quadrature decoder
● Supports 3-phase motor control and hall sensor interface
● Break input to force the timer’s output signals into a reset or fixed condition
▀ Watchdog Timer
● 12-bit down-counting counters with 3-bit prescaler
● Interrupt or reset event for the system
● Programmable watchdog timer window function
● Write protection function
▀ Real Time Clock
● 32-bit up-counting counters with a programmable prescaler
● Alarm function
● Interrupt and Wake-up event
▀ Communication Interfaces
● Two I2C interfaces which support both master and slave mode with a frequency of up to 1MHz
● Two SPI interfaces which support both master and slave mode with a frequency of up to
36MHz for the master and a frequency of up to 18MHz for the slave
● Two USART interfaces operate at a frequency of up to 4.5MHz
Rev. 1.00
24 of 628
August 13, 2012
Introduction
▀ PWM Generation and Capture Timers
● Two 16-bit General-Purpose Timer – GPTM
● Up to 4 Channels with PWM, compare output or input capture input for each GPTM
● External trigger input
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
▀ Peripheral Direct Memory Access – PDMA
● 12 channels with trigger source grouping
● Transfer modes: single and block
● Data Transfer Width: 8, 16, and 32-bit
● Addressing modes: increment, decrement and fixed
● 4 levels programmable channel priority
● Auto reload mode
● PDMA trigger sources: CSIF, ADC, SPI, USART, I2C, GPTM, MCTM, SCI and software
▀ Universal Serial Bus Device Controller – USB
● Complies with USB 2.0 full-speed (12Mbps) specification
● On-chip USB full-speed transceiver
● 1 control endpoint (EP0) for control transfer
● 3 single-buffered endpoints for bulk and interrupt transfer
● 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
● 1KB EP-SRAM used as the endpoint data buffers
▀ CMOS Sensor Interface – CSIF, HT32F2755 only
● Up to 2048×2048 input resolution
● Supports 8-bit YUV422 and Raw RGB formats
● Up to 24MHz input pixel clock frequency
● Multi VSYNC and HSYNC setting for image capture
● Fractional hardware sub-sample function
● Hardware windowing capture function
● Dual FIFOs with a capacity of 8×32 bits which can be read by the PDMA or CPU
▀ Debug support
● Serial Wire or JTAG Debug Port – SWJ-DP
● 6 instruction comparator and 2 literal comparator for hardware breakpoint or code/literal patch
● 4 comparators for hardware watchpoints
● 1-bit asynchronous trace for serial wire debug mode – TRACESWO
▀ 48, 64, and 100-pin LQFP packages
▀ Operation temperature range: -40ºC to +85ºC
Rev. 1.00
25 of 628
August 13, 2012
Introduction
▀ Smart Card Interface – SCI
● Supports ISO 7816-3 Standard
● Character transfer mode
● Single transmit buffer and single receive buffer
● 11-bit Elementary Time Unit (ETU) counter
● 9-bit Guard Time counter – GT
● 24-bit Waiting Time counter – WT
● Parity generation and checking
● Automatic character retry on parity error detection in transmission and reception modes
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Device Information
Most features are common to all devices while the main features distinguishing them are CSIF, and
SRAM memory capacities.
Table 1. HT32F1755/1765/2755 Series Features and Peripheral List
Peripherals
HT32F1765
HT32F2755
127
127
Option Bytes Flash
1
1
1
SRAM (KB)
32
64
64
Times
MCTM
1
GPTM
2
BFTM
2
RTC
1
WDT
1
Communication
CSIF
—
USB
1
SCI
1
USART
2
SPI
2
IC
2
GPIO
Up to 80
EXTI
16
12-bit ADC Number of channels
—
Introduction
127
2
Rev. 1.00
HT32F1755
Main Flash (KB)
1
1
8 Channels
OPA/Comparator
2
CPU frequency
Up to 72MHz
Operating voltage
2.7V~3.6V
Operating temperature
-40℃ ~+85℃
Package
LQFP 48/64/100
26 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Block Diagram
JTRST� JTDI� JTDO�
JTCK_SWCLK�
JTMS_SWDIO
TR�CESWO
�F
BOOT0
BOOT1
�F
CSIF_VSYNC� CSIF_HSYNC�
CSIF_MCK� CSIF_PCK�
CSIF_D[7:0]
�F
�F
Powered by VDD18
SWJ-DP
ICode
TPIU
Control/Data
Re�isters
PLL
HSE
�F
Interr�pt req�est
SR�M Controller
PDM�
fMax: 144 MHz
Clock and reset control
�HB Peripherals
4 ~ 16 MHz
XT�LIN
XT�LOUT
HSI
SR�M
8 MHz
VLDOIN
PDM� req�est
LDO
�HB to �PB
�HB
to �PB
Brid�e
Brid�e
VLDOOUT
1.8 V
VSSLDO
BOD
LVD
SPI1
�F
SPI0
GPTM 0 ~ 1
PB [15:0]
GPIOB
PC [15:0]
GPIOC
PD [15:0]
GPIOD
PE [15:0]
GPIOE
�PB1
GPIO�
�PB0
P� [15:0]
GT0_CH0~
GT0_CH��
GT0_ETI
GT1_CH0~
GT1_CH��
GT1_ETI
SCI_CLK�
SCI_DIO�
SCI_DET
�F
Powered by VDD�
�F
WDT
USBDP
USBDM
�F
OP�/CMP
RTCOUT
BFTM 0 ~ 1
SCI
RTC
I�C0_SD��
I�C0_SCL
I�C1_SD��
I�C1_SCL
�F
�nalo�
OP�/CMP
USB Device
Power control
�F
�DC
SPI1_MOSI�
SPI1_MISO�
SPI1_SCK�
SPI1_SEL
�F
�F
I�C 0 ~ 1
1�-bit
S�R �DC
UR1_TX�
UR1_RX�
UR1_RTS/TXE�
UR1_CTS/SCK
�F
US�RT1
�F
�F
VDD18
US�RT0
PWRSW
VB�T
VB�K
�FIO
PWRCU
VLDOIN
EXTI
PORB
�F
MCTM
VB�K �.� V
LSE
W�KEUP
���768 Hz
nRST
Back�p Domain VB�K
Powered by VDD18
�F
BREG
LSI
�� kHz
�F
XT�L��KIN
XT�L��KOUT
Power s�pply:
B�s:
Control si�nal:
�lternate f�nction:
�F
Note: The AHB peripheral function, CSIF, only exists in the HT32F2755 device.
Figure 1. HT32F1755/1765/2755 Block Diagram
Rev. 1.00
27 of 628
August 13, 2012
Introduction
VSS��_1~4
1.8 V
CKCU/RSTCU
Control
Re�isters
Powered by VLDOIN
VDD�
VSS�
MT_CH0~
MT_CH� �
MT_CH0N~
MT_CH�N �
MT_CH� �
MT_ETI �
MT_BRK .
CSIF
FMC
Control
Re�isters
1� Channels
VREF+� VREFCN0� CP0
�OUT0
CN1� CP1
�OUT1
PDM�
Control
Re�isters
B�s Matrix
NVIC
�DC_IN0
:
�DC_IN7
VDD��_1~4
POR
DCode System
fMax: 7� MHz
SPI0_MOSI�
SPI0_MISO�
SPI0_SCK�
SPI0_SEL
Flash Memory
MPU
CortexTM-M�
Processor
UR0_TX�
UR0_RX�
UR0_DCD�
UR0_DSR�
UR0_DTR�
UR0_RI
UR0_RTS/TXE
UR0_CTS/SCK
Flash Memory Interface
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
2
Document Conventions
The conventions used in this document are shown in the following table.
Table 2. Document Conventions
Notation
0x
Example
0x5a05
32-bit Hexadecimal address or data.
b
b0101
The number string with a lowercase b prefix indicates a binary
number.
NAME [n]
ADDR [5]
Specific bit of NAME. NAME can be a register or field of register.
For example, ADDR [5] means bit 5 of ADDR register (field).
NAME [m:n]
ADDR [11:5]
Specific bits of NAME. NAME can be a register or field of register.
For example, ADDR [11:5] means bit 11 to 5 of ADDR register (field).
X
b10X1
Don’t care notation which means any value is allowed.
RO
Software can read and write to this bit.
3
2
HSIRDY
RO
1
HSERDY
RO
0
Software can only read this bit. A write operation will have no effect.
RC
Software can only read this bit. Read operation will clear it to 0
automatically.
WC
Software can read this bit or clear it by writing 1. Writing 0 will
have no effect.
WO
Software can only write to this bit. A read operation always returns 0.
Reserved
Reserved bit(s) for future use. Data read from these bits is not
well defined and should be treated as random data. Normally
these reserved bits should be set to 0. Note that reserved bit must
be kept at reset value.
Word
Data length of a word is 32-bit.
Half-word
Data length of a half-word is 16-bit.
Byte
Data length of a byte is 8-bit.
28 of 628
August 13, 2012
Document Conventions
0xnnnn_nnnn 0x2000_0100
RW
Rev. 1.00
Description
The number string with a 0x prefix indicates a hexadecimal number.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
3
System Architecture
ARM® CortexTM-M3 Processor
The Cortex™-M3 is a general purpose 32-bit processor core especially suitable for products
requiring high performance and low power consumption microcontrollers. It offers many new
features such as a Thumb-2 instruction sets, hardware divider, low latency interrupt respond
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction
sets. Some system peripherals listed below are also provided by Cortex™-M3:
▀ Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private Peripheral Bus
(PPB) and debug accesses (AHB-AP)
▀ Nested Vectored Interrupt Controller (NVIC)
▀ Flash Patch and Breakpoint (FPB)
▀ Data Watchpoint and Trace (DWT)
▀ Instrument Trace Macrocell (ITM)
▀ Memory Protection Unit (MPU)
▀ Serial Wire debug Port (SW-DP)
▀ Serial Wire JTAG Debug Port (SWJ-DP)
▀ Embedded Trace Macrocell (ETM)
▀ Trace Port Interface Unit (TPIU)
The following figure shows the Cortex™-M3 processor block diagram. For more information, refer
to the ARM® Cortex™-M3 Technical Reference Manual.
Rev. 1.00
29 of 628
August 13, 2012
System Architecture
The system architecture of the HT32F1755/1765/2755 series of devices that includes the ARM®
Cortex™-M3 processor, bus architecture and memory organization will be described in the
following sections. The Cortex™-M3 is a next generation processor core which offers many new
features. Integrated and advanced features make the Cortex™-M3 processor suitable for market
products that require microcontrollers with high performance and low power consumption. In
brief, The Cortex™-M3 processor includes three AHB-Lite buses known as ICode, DCode and
System buses. All memory accesses of the Cortex™-M3 processor are executed on the three buses
according to the different purposes and the target memory spaces. The memory organization uses
a Harvard architecture, pre-defined memory map and up to 4GB of memory space, making the
system flexible and extendable.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
System Architecture
Figure 2. Cortex™-M3 Block Diagram
Rev. 1.00
30 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bus Architecture
ICode
DCode
B�s Matrix
System
Figure 3. HT32F1755/1765/2755 Bus Architecture
Memory Organization
The ARM® Cortex™-M3 processor is structured in Harvard architecture which can use separate
buses to fetch instructions and load/store data. The instruction code and data are both located in
the same memory address space but in different address ranges. The maximum address range of
the Cortex™-M3 is 4GB since it has 32-bit bus address width. Additionally, a pre-defined memory
map is provided by the Cortex™-M3 processor to reduce the software complexity of repeated
implementation of different device vendors. However, some regions are used by the ARM®
Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference Manual
for more information. The following figure shows the memory map of HT32F1755/1765/2755 series
of devices, including Code, SRAM, peripheral, and other pre-defined regions.
Rev. 1.00
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August 13, 2012
System Architecture
The HT32F1755/1765/2755 series consist of four masters and four slaves in the bus architecture.
The Cortex™-M3 ICode, DCode, System bus and Peripheral Direct Memory Access (PDMA)
are the masters while the internal SRAM access bus, the internal Flash memory access bus, the
AHB peripherals access bus and the AHB to APB bridge are the slaves. The ICode bus is used
for instruction and vector fetches from the Code region (0x0000_0000~0x1FFF_FFFF) to the
Cortex™-M3 core. The DCode bus is used for loading/storing data and also for debug access of the
Code region. Similarly, the System bus is used for instruction/vector fetches, data loading/storing
and debugging access of the system regions. The system regions include the internal SRAM
region and the peripheral region. All of the four master buses are based on 32-bit Advanced
High-performance Bus-Lite (AHB-Lite) protocol. The following figure shows the bus architecture
of the HT32F1755/1765/2755 series.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Memory Map
0xFFFF_FFFF
Reserved
0x400F_FFFF
0xE010_0000
0xE000_0000
Reserved
APB/AHB bit band alias
Peripheral
32 Mbytes
0x4200_0000
0x4010_0000
0x4008_0000
0x4000_0000
0x2220_0000
Reserved
AHB peripherals
512 kbytes
APB peripherals
512 kbytes
Reserved
SRAM bit band alias
2 Mbytes
SRAM
0x2200_0000
0x2001_0000
0x2000_8000
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
0x1F00_0000
Code
0x0002_0000
Reserved
64 kbytes
(HT32F1765/
HT32F2755)
32 kB on-chip SRAM
32 kB on-chip SRAM
32 kbytes
(HT32F1755)
Reserved
Option bytes alias
1 kbytes
Reserved
Boot loader
2 kbytes
Reserved
128 kbytes
128 kB on-chip Flash
0x0000_0000
0x400C_E000
0x400C_C000
0x4009_2000
0x4009_0000
0x4008_A000
0x4008_8000
0x4008_2000
0x4008_0000
0x4007_8000
0x4007_7000
0x4007_6000
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4004_F000
0x4004_E000
0x4004_A000
0x4004_9000
0x4004_8000
0x4004_5000
0x4004_4000
0x4004_3000
0x4004_1000
0x4004_0000
0x4002_D000
0x4002_C000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_F000
0x4001_E000
0x4001_D000
0x4001_C000
0x4001_B000
0x4001_A000
0x4001_9000
0x4001_8000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_1000
0x4000_0000
Reserved
CSIF
Reserved
PDMA
Reserved
CKCU/RSTCU
Reserved
FMC
Reserved
BFTM1
BFTM0
Reserved
GPTM1
GPTM0
Reserved
RTC/PWRCU
Reserved
WDT
Reserved
USB
Reserved
I2C1
I2C0
Reserved
SPI1
SCI
Reserved
USART1
Reserved
MCTM
Reserved
EXTI
Reserved
AFIO
Reserved
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Reserved
OPA/CMP
Reserved
ADC
Reserved
SPI0
Reserved
USART0
AHB
APB1
APB0
Note: For HT32F1755, the SRAM memory space at 0x2000_8000 to 0x2000_FFFF is reserved.
Figure 4. HT32F1755/1765/2755 Memory Map
Rev. 1.00
32 of 628
August 13, 2012
System Architecture
0x4400_0000
Private peripheral bus
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table 3. HT32F1755/1765/2755 Register Map
Start Address
Peripheral
0x4000_0000
0x4000_0FFF
USART0
0x4000_1000
0x4000_3FFF
Reserved
0x4000_4000
0x4000_4FFF
SPI0
0x4000_5000
0x4001_FFFF
Reserved
0x4001_0000
0x4001_0FFF
ADC
0x4001_1000
0x4001_7FFF
Reserved
0x4001_8000
0x4001_8FFF
OPA/Comparator
0x4001_9000
0x4001_9FFF
Reserved
0x4001_A000
0x4001_AFFF
GPIOA
0x4001_B000
0x4001_BFFF
GPIOB
0x4001_C000
0x4001_CFFF
GPIOC
0x4001_D000
0x4002_DFFF
GPIOD
0x4001_E000
0x4001_EFFF
GPIOE
0x4001_F000
0x4002_1FFF
Reserved
0x4002_2000
0x4002_2FFF
AFIO
0x4002_3000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
EXTI
0x4002_5000
0x4002_BFFF
Reserved
0x4002_C000
0x4002_CFFF
MCTM
0x4002_D000
0x4003_FFFF
Reserved
0x4004_0000
0x4004_0FFF
USART1
0x4004_1000
0x4004_2FFF
Reserved
0x4004_3000
0x4004_3FFF
SCI
0x4004_4000
0x4004_4FFF
SPI1
0x4004_5000
0x4004_7FFF
Reserved
0x4004_8000
0x4004_8FFF
I2C0
0x4004_9000
0x4004_9FFF
I2C1
0x4004_A000
0x4004_DFFF
Reserved
0x4004_E000
0x4004_EFFF
USB
0x4004_F000
0x4006_7FFF
Reserved
0x4006_8000
0x4006_8FFF
WDT
0x4006_9000
0x4006_9FFF
Reserved
0x4006_A000
0x4006_AFFF
RTC/PWRCU
0x4006_B000
0x4006_DFFF
Reserved
0x4006_E000
0x4006_EFFF
GPTM0
0x4006_F000
0x4006_FFFF
GPTM1
0x4007_0000
0x4007_5FFF
Reserved
0x4007_6000
0x4007_6FFF
BFTM0
0x4007_7000
0x4007_7FFF
BFTM1
0x4007_8000
0x4007_FFFF
Reserved
33 of 628
Bus
Register map
System Architecture
Rev. 1.00
End Address
APB
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Start Address
End Address
Peripheral
0x4008_1FFF
FMC
0x4008_2000
0x4008_7FFF
Reserved
0x4008_8000
0x4008_9FFF
CKCU/RSTCU
0x4008_A000
0x4008_FFFF
Reserved
0x4009_0000
0x4009_1FFF
PDMA
0x4009_2000
0x400C_BFFF
Reserved
0x400C_C000
0x400C_DFFF
CSIF
0x400C_E000
0x400F_FFFF
Reserved
Register map
AHB
Embedded Flash Memory
HT32F1755/1765/2755 series of devices provide 128KB of on-chip flash memory which is located
at address 0x0000_0000. It supports byte, half-word, and word access operations. Note that the
flash memory only supports read operations for the Cortex™-M3 ICode or DCode bus access. Any
write operations to the flash memory (via DCode bus) will cause a bus fault exception. The flash
memory has a capacity of 128 pages. Each page has a memory capacity of 1KB and can be erased
independently. A 32-bit programming interface provides the capability of changing bits from 1 to
0. A data storage or firmware upgrade can be implemented using several method such as In System
Programming (ISP), In Application Programming (IAP) or In Circuit Programming (ICP). For
more information refer to the Flash Memory Controller section.
Embedded SRAM Memory
The HT32F1765/2755 devices contain 64KB on-chip SRAM while the HT32F1755 device contains
32KB on-chip SRAM, which is located at address 0x2000_0000. They support byte, half-word
and word access operations. In order to reduce the time of read-modify-write operations, the
Cortex™-M3 provides a bit-banding function to perform a single atomic bit operation. Users can
modify a single bit in the SRAM bit-band region by accessing the corresponding bit-band alias. For
more information about bit-binding, refer to the ARM® Cortex™-M3 Technical Reference Manual.
The following formulas and examples show how to access a bit in the bit-band region by calculating
the bit-band alias.
Bit-band alias=Bit-band base+(byte offset*32)+(bit number*4)
For example, if you want to access bit 7 of address 0x2000_0200, the bit-band alias is:
Bit-band alias=0x2200_0000+(0x200*32)+(7*4)=0x2200_401C
Writing to address 0x2200_401C will cause bit 7 of address 0x2000_0200 change while a read to
address 0x2200_401C will return 0x01 or 0x00 according to the value of bit 7 at the SRAM address
0x2000_0200.
Rev. 1.00
34 of 628
August 13, 2012
System Architecture
0x4008_0000
Bus
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
AHB Peripherals
The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals
such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the
AHB bus directly. The AHB peripherals clocks are always enabled after a system reset. Access to
registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral
registers in the AHB bus support only word access.
The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB bridge
provides access capability between the Cortex™-M3 and the APB peripherals. Additionally, the
APB peripheral clocks are disabled after a system reset. Software must enable the peripheral clock
by setting up the APBCCRn register in the Clock Control Unit before accessing the corresponding
peripheral register. Note that the APB to AHB bridge will duplicate the half-word or byte data to word
width when a half-word or byte access is performed on the APB peripheral registers. In other words,
the access result of a half-word or byte access on the APB peripheral register will vary depending on
the data bit width of the access operation on the peripheral registers.
Rev. 1.00
35 of 628
August 13, 2012
System Architecture
APB Peripherals
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
4
Flash Memory Controller (FMC)
Introduction
Flash Memory Controller
Flash
Option Byte
Boot Loader
System Bus
Wait State
Control
Control Register
Addressing
I/D Code
Bus
Pre-fetch Buffer
Data
Branch Cache
Programming
Control
Main Flash
Figure 5. Flash Memory Controller Block Diagram
Features
▀ 128KB on-chip Flash memory for storing instruction/data and options
● HT32F1755: 127KB + 1KB (instruction/data + option byte)
● HT32F1765: 127KB + 1KB (instruction/data + option byte)
● HT32F2755: 127KB + 1KB (instruction/data + option byte)
Page
size of 1KB – total of 128 pages
▀
▀ Wide access interface with pre-fetch buffer and branch cache to reduce instruction gaps
▀ Page erase and mass erase capability
▀ 32-bit word programming
▀ Interrupt function to indicate end of Flash memory operations or an error occurs
▀ Flash read protection to prevent illegal code/data access
▀ Page erase/program protection to prevent unexpected operation
Rev. 1.00
36 of 628
August 13, 2012
Flash Memory Controller (FMC)
The Flash Memory Controller, FMC, provides all the necessary functions, pre-fetch buffer and
branch cache for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory
is slower than the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Function Descriptions
Flash Memory Map
0x1FFF_FFFF
Reserved
0x1FF0_0400
0x1FF0_0000
Option Byte
1 KB
Reserved
0x1F00_0800
0x1F00_0000
0x0002_0000
Boot Loader
2 KB
Reserved
Main Flash
(User Application)
127 KB
0x0000_0000
Figure 6. Flash Memory Map
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
The following figure is the Flash memory map of the HT32F1755/1765/2755 devices in which the
address ranges from 0x0000_0000 to 0x1FFF_FFFF (0.5GB). The address from 0x1F00_0000
to 0x1F00_07FF is mapped to the Boot Loader with a capacity of 2KB. Additionally, the region
addressed from 0x1FF0_0000 to 0x1FF0_03FF is the Option Byte Block with a capacity of 1KB.
The memory mapping on system view is shown as below.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Memory Architecture
The Flash memory consists of 128KB Main Flash organized into 128 pages with 1KB capacity per
page and a 2KB Information Block for the Boot Loader. The main Flash memory contains a total of
128 pages which can be erased individually. The following table shows the base address, size and
protection setting bit of each page.
Table 4. Flash Memory and Option Byte
Address
Page Protection Bit
Size
Page 0
0x0000_0000~0x0000_03FF
OB_PP [0]
1KB
Page 1
0x0000_0400~0x0000_07FF
OB_PP [1]
1KB
Page 2
0x0000_0800~0x0000_0BFF
OB_PP [2]
1KB
.....
.....
.....
.....
Main Flash
Name
Page 126
0x0001_F800~0x0001_FBFF
OB_PP [126]
1KB
Option Byte
0x1FF0_0000~0x1FF0_03FF
OB_CP [1]
1KB
Information Block Boot Loader
0x1F00_0000~0x1F00_07FF
NA
2KB
Note: The Information Block stores the boot loader – this block can not be programmed or erased by user.
Wait State Setting
When the CPU clock, HCLK, is greater than the access speed of the Flash memory, then wait state
cycles must be inserted during the CPU fetch instructions or load data from Flash memory. The wait
state can be changed by setting the WAIT [2:0] bits of the Flash Cache and Pre-fetch Control Register,
CFCR. In order to match the wait state requirement, the following two rules should be considered.
▀ HCLK clock is switched from low to high frequency: Change the wait state setting first and then
switch the HCLK clock.
▀ HCLK clock is switched from high to low frequency: Switch the HCLK clock first and then
change the wait state setting.
The following table shows the relationship between the wait state cycle and the CPU clock HCLK.
The default wait state is 0 since the High Speed Internal oscillator HSI which operates at a
frequency of 8MHz is selected as the HCLK clock source after reset.
Table 5. Relationship between wait state cycle and HCLK
Wait State Cycle
Rev. 1.00
HCLK
0
0MHz < HCLK ≤ 24MHz
1
24MHz < HCLK ≤ 48MHz
2
48MHz < HCLK ≤ 72MHz
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August 13, 2012
Flash Memory Controller (FMC)
Block
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Booting Configuration
The HT32F1755/1765/2755 devices provide three kinds of boot modes which can be selected using
the BOOT0 and BOOT1 pins. The BOOT0 and BOOT1 pins are sampled during a power-on reset
or a system reset. Once the logic value on these pins has been determined, the first 4 words of
vector will be remapped to the corresponding source according to the boot mode. The boot modes
are shown in the following table.
Booting mode selection pins
Mode
Descriptions
BOOT1
BOOT0
0
0
SRAM
Vector source is SBVT0~SBVT3
0
1
Boot Loader
Vector source is Boot Loader
1
X
Main Flash
Vector source is Main Flash memory
The Vector Mapping Control Register (VMCR) is provided to change the vector remapping setting
temporarily after a device reset. The initial reset value of the VMCR register is determined by the
BOOT0 and BOOT1 pins which will be sampled during the reset duration.
.
BOOT1 and BOOT0 Setting
.
.
01: Boot Loader
1X: Main Flash
00: SRAM
0xC
Hard fault Handler
+0xC
+0xC
+0xC
SBVT3
0x8
NMI Handler
+0x8
+0x8
+0x8
SBVT2
0x4
Program Counter
+0x4
+0x4
+0x4
SBVT1
0x0
Initial Stack Point
0x0000_0000
0x1F00_0000
0x4008_0300
SBVT0
0
Figure 7. Vector Remapping
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
Table 6. Booting Modes
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Page Erase
The FMC provides a page erase function which is used to initialize the contents of a Flash memory
page to a high state. Each page can be erased independently without affecting the contents of other
pages. The following steps show the access sequence of the register for a page erase operation.
Note that a correct target page address must be confirmed. The software may run out of control if
the target erase page is being used to fetch codes or to access data. The FMC will not provide any
notification when this occurs. Additionally, the page erase operation will be ignored on protected
pages. A Flash operation error interrupt will be triggered by the FMC if the OREIEN bit in the
OIER register is set. The software can check the PPEF bit in the OISR register to detect this
condition in the interrupt handler. The following figure shows the page erase operation flow.
Start
No
Is OPM equal to
0xE | 0x6?
Yes
Set TADR, OCMR
Send command by
setting OPCR
No
Is OPM equal to
0xE?
Yes
Finish
Figure 8. Page Erase Operation Flowchart
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
▀ Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the previous operation has been finished.
▀ Write the page address into the TADR register.
▀ Write the page erase command into the OCMR register (CMD [3:0]=0x8).
▀ Send the page erase command to the FMC by setting the OPCR register (set OPM [3:0]=0xA).
▀ Wait until all the operations have been completed by checking the value of the OPCR register
(OPM [3:0] equal to 0xE).
▀ Read and verify the page if required using DCODE access.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Mass Erase
The FMC provides a mass erase function which is used to initialize the complete Flash memory
contents to a high state. The following steps show the mass erase operation register access
sequence.
Since all Flash contents will be reset to the value of 0xFFFF_FFFF, the mass erase operation can
be implemented by an application that runs in SRAM or by the debug tool that accesses the FMC
registers directly. An application executes on the Flash memory will not trigger a mass erase
operation. The following figure shows the mass erase operation flow.
Start
No
Is OPM equal to
0xE | 0x6?
Yes
Set OCMR= 0xA
Send command by
setting OPCR
No
Is OPM equal to
0xE?
Yes
Finish
Figure 9. Mass Erase Operation Flowchart
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
▀ Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the previous operation has been finished.
▀ Write the mass erase command into the OCMR register (CMD [3:0]=0xA).
▀ Send the mass erase command to the FMC by setting the OPCR register (set OPM [3:0]=0xA).
▀ Wait until all operations have been completed by checking the value of the OPCR register (OPM
[3:0] equal to 0xE).
▀ Read and verify the Flash memory if required using DCODE access.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Word Programming
The FMC provides a 32-bit word programming function which is used to modify the Flash memory
contents. The following steps show the word programming operation register access sequence.
Note that the word programming operation can not be applied to the same address twice.
Successive word programming operations to the same address must be separated by a page erase
operation. Additionally, the word programming operation will be ignored on protected pages.
A Flash operation error interrupt will be triggered by the FMC if the OREIEN bit in the OIER
register is set. The software can check the PPEF bit in the OISR register to detect this condition in
the interrupt handler. The following figure shows the word programming operation flow.
Start
No
Is OPM equal to
0xE | 0x6?
Yes
Set TADR, WRDR and
OCMR
Send command by
setting OPCR
No
Is OPM equal to
0xE?
Yes
Finish
Figure 10. Word Programming Operation Flowchart
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
▀ Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the previous operation has been finished.
▀ Write the word address into the TADR register. Write the word data into the WRDR register.
▀ Write the word programming command into the OCMR register (CMD [3:0]=0x4).
▀ Send the word programming command to the FMC by setting the OPCR register (set OPM
[3:0]=0xA).
▀ Wait until all operations have been completed by checking the value of the OPCR register (OPM
[3:0] equal to 0xE).
▀ Read and verify the Flash memory if required using DCODE access.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Option Byte Description
The Option Byte region can be treated as an independent Flash memory in which the base address
is 0x1FF0_0000. The following table shows the functional description and the Option Byte
memory map.
Table 7. Option Byte Memory Map
Option Byte
Offset
Description
Reset Value
OB_PP
OB_CP
OB_CK
Rev. 1.00
0x000
0x004
0x008
0x00C
OB_PP [n]: Main Flash Page Erase/Program Protection
(n=0~126 for page 0~page 126)
0: Main Flash Page n Erase/Program Protection is enabled
1: Main Flash Page n Erase/Program Protection is disabled
OB_PP [127]: Reserved
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0x010
OB_CP [0]: Flash Security Protection
0: Flash Security protection is enabled
1: Flash Security protection is disabled
OB_CP [1]: Option Byte Erase/Program Protection
0: Option Byte protection is enabled
1: Option Byte protection is disabled
OB_CP [31:2]: Reserved
0xFFFF_FFFF
0x020
OB_CK [31:0]: Option Byte Checksum
OB_CK should be set as the sum of the 5 words Option Byte
content, of which the address offset ranges form 0x000 to 0x010
(0x000 + 0x004 + 0x008 + 0x00C + 0x010), when the content of
the OB_PP or OB_CP register is not equal to 0xFFFF_FFFF.
0xFFFF_FFFF
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August 13, 2012
Flash Memory Controller (FMC)
Option Byte Base Address=0x1FF0_0000
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Page Erase/Program Protection
Table 8. Access Permission of Protected Main Flash Page
Mode
ISP/IAP
ICP/Debug mode
Boot from SRAM
DCODE Read
O
O
O
Program
X
X
X
Page Erase
X
X
X
Mass Erase
O
O
O
Operation
Notes: 1. The write protection setup is based on specific pages. The above access permission only
affects the pages that the protection function has been enabled. Other pages are not
affected.
2. The Main Flash page protection is configured by OB_PP [126:0]. The Option Byte page
protection is configured by the OB_CP [1] bit.
The following steps show the page erase/program protection procedure register access sequence:
▀ Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the previous operation has been finished.
▀ Write the OB_PP address into the TADR register (TADR=0x1FF0_0000~0x1FF0_000C).
▀ Write the data which indicates the protection function of the corresponding page is enabled or
disabled into the WRDR register (0: Enabled, 1: Disabled).
▀ Write the word programming command into the OCMR register (CMD [3:0]=0x4).
▀ Send the word programming command to the FMC by setting the OPCR register (set OPM
[3:0]=0xA).
Wait
until all operations have been finished by checking the value of the OPCR register (OPM
▀
[3:0] equals to 0xE).
▀ Read and verify the OB_PP if required using DCODE access.
▀ Before to active the new OB_PP setting, the OB_CK must be updated according to the Option
Byte checksum rule.
▀ Apply a system reset to active the new setting.
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
The FMC provides page erase/program protection functions to prevent inadvertent operations on
the Flash memory. The page erase or word programming command will not be accepted by the
FMC on protected pages. When the page erase or word programming command is sent to the FMC
on a protected page, the PPEF bit in the OISR register will then be set by the FMC. If the OREIEN
bit in the OIER register is also set to 1 then the Flash operation error interrupt will be triggered by
the FMC. The page protection function can be individually enabled for each page by configuring
the OB_PP [126:0] bit field in the Option Byte. If a page erase operation is executed on the Option
Byte region, all the Flash Memory page protection functions will be disabled. The page protection
function of the Option Byte is enabled by clearing the OB_CP [1] bit to 0. Once the Option Byte
has been protected, the only way to disable its protection function is to execute a mass erase
operation. The following table shows the access permission of the Main Flash page when the page
protection is enabled.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Security Protection
Table 9. Access Permission When Security Protection Is Enabled
Mode
User application(1)
ICP/Debug mode
Boot from SRAM
O
X(2)
X(2)
Program
O(1)
X
X
Page Erase
O
X
X
O
O
Operation
DCODE Read
Mass Erase
(1)
O
Notes: 1. User application means the software that is executed or booted from the Main Flash
memory with the JTAG/SW debugger disconnected. However the Option Byte and the
page 0 are still protected in which Programming and Page Erase operations can not be
executed.
2. When the JTAG/SW debugger is connected or the executing application is booted from
SRAM, all the DCODE read operation to all Flash memory regions will return with the value
of 0.
The following steps show the security protection procedure register access sequence:
▀ Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the pervious operation has been finished.
▀ Write the OB_CP address to the TADR register (TADR=0x1FF0_0010).
▀ Write the data into the WRDR register to clear OB_CP [0] bit to 0.
▀ Write the word programming command into the OCMR register (CMD [3:0]=0x4).
▀ Send the word programming command to the FMC by setting the OPCR register (set
OPM=0xA).
▀ Wait until all operations have been finished by checking the value of the OPCR register (OPM
[3:0] equals to 0xE).
Read
and verify the OB_CP if required using DCODE access.
▀
▀ Before to activate the security protection function, the OB_CK field must be updated according
to the Option Byte checksum rule.
▀ Apply a system reset to active the new setting.
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
The FMC provides a security protection function to prevent illegal code/data access on the Flash
memory. This function is useful for protecting the software/firmware from illegal users. The
function is activated by configuring the OB_CP [0] bit in the Option Byte. Once the function has
been enabled, all the main Flash DCODE access, programming and page erase operations will
not be allowed except for the user’s application. However, the mass erase operation will still be
accepted by the FMC in order to disable this security protection function. The following table
shows the access permission of Flash memory when the security protection is enabled.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Map
The following table shows the FMC registers and reset values.
Table 10. FMC Register Map
Register
Offset
Description
Reset Value
FMC Base Address=0x4008_0000
0x000
Flash Target Address Register
0x0000_0000
WRDR
0x004
Flash Write Data Register
0x0000_0000
OCMR
0x00C
Flash Operation Command Register
0x0000_0000
OPCR
0x010
Flash Operation Control Register
0x0000_000C
OIER
0x014
Flash Operation Interrupt Enable Register
0x0000_0000
OISR
0x018
Flash Operation Interrupt Status Register
0x0001_0000
PPSR
0x020
0x024
0x028
0x02C
Flash Page Erase/Program Protection Status Register
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
CPSR
0x030
Flash Security Protection Status Register
0xXXXX_XXXX
VMCR
0x100
Flash Vector Mapping Control Register
0x0000_000X
CFCR
0x200
Flash Cache and Pre-fetch Control Register
0x0000_13D1
SBVT0
0x300
SRAM Booting Vector 0 (Stack Point)
0x2000_XX00
SBVT1
0x304
SRAM Booting Vector 1 (Program Counter)
0x2000_0101
SBVT2
0x308
SRAM Booting Vector 2 (NMI Handler)
0x0000_0000
SBVT3
0x30C
SRAM Booting Vector 3 (Hard Fault Handler)
0x0000_0000
Note: “X” means various reset values which depend on the Device, Flash value, option byte value, or
power on reset setting.
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
TADR
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
Flash Target Address Register – TADR
This register specifies the target address of the page erase and word programming operations.
Offset:
0x000
Reset value: 0x0000_0000
30
29
28
27
26
25
24
TADB
Type/Reset
RW
0
23
RW
0
RW
22
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
TADB
Type/Reset
RW
0
15
RW
0
RW
14
0
13
RW
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
TADB
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
TADB
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:0]
TADB
Flash Target Address Bits
For programming operations, the TADR register specifies the address where
the data is written. Since the programming length is 32 bits, TADR shall be set
as word-aligned (4 bytes). The TADB [1:0] will be ignored during programming
operations. For page erase operations, the TADR register contains the page address
which is going to be erased. Since the page size is 1KB, TADB [9:0] will be ignored in
order to limit the target address as 1KB-aligned. For 127KB Main Flash addressing,
TADB [31:17] should be zero. The Option Byte which has a 1KB capacity ranges
from 0x1FF0_0000 to 0x1FF0_03FF. This field is used to specify the Flash Memory
address which must be within the range from 0x0000_0000 to 0x1FFF_FFFF.
Otherwise, an Invalid Target Address interrupt will be generated if the corresponding
interrupt enable bit is set.
Rev. 1.00
47 of 628
August 13, 2012
Flash Memory Controller (FMC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Write Data Register – WRDR
This register stores the data to be written into the TADR register for programming operations.
Offset:
0x004
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
RW
0
23
RW
0
22
RW
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
WRDB
Type/Reset
RW
0
15
RW
0
14
RW
0
13
RW
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
WRDB
Type/Reset
RW
0
7
RW
0
6
RW
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
WRDB
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:0]
WRDB
Flash Write Data Bits
The data value for programming operation.
Rev. 1.00
48 of 628
RW
0
RW
0
RW
0
August 13, 2012
Flash Memory Controller (FMC)
WRDB
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Operation Command Register – OCMR
This register is used to specify the Flash operation commands that include word program, page erase
and mass erase.
Offset:
0x00C
Reset value: 0x0000_0000
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Flash Memory Controller (FMC)
31
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
CMD
Type/Reset
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[3:0]
CMD
Flash Operation Command
The following table shows the definitions of the operation command bits CMD [3:0]
which determine the Flash Memory operation. If an invalid command is set and the
IOCMIEN bit is equal to 1, an Invalid Operation Command interrupt will occur.
CMD [3:0]
0x0
0x4
0x8
0xA
Others
Rev. 1.00
Description
Idle - default
Word program
Page erase
Mass erase
Reserved
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August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Operation Control Register – OPCR
This register is used for controlling the command commitment and checking the status of the FMC
operations.
Offset:
0x010
Reset value: 0x0000_000C
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
OPM
RW
0
RW
1
RW
1
Reserved
RW
0
Bits
Field
Descriptions
[4:1]
OPM
Operation Mode
The following table shows the operation modes of the FMC. User can commit the
command which is set by the OCMR register for the FMC according to the address
alias setting in the TADR register. The contents of the TADR, WRDR, and OCMR
registers should be prepared before setting this register. After all the operations have
been finished, the OPM field will be set as 0xE by the FMC hardware. The Idle mode
can be set when all the operations have been finished for power saving purposes.
Note that the operation status should be checked before the next operation is
executed on the FMC. The contents of the TADR, WRDR, OCMR, and OPCR
registers should not be changed until the previous operation has been finished.
OPM [3:0]
0x6
0xA
0xE
Others
Rev. 1.00
Description
Idle (default)
Commit command to main Flash
All operation finished on main Flash
Reserved
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August 13, 2012
Flash Memory Controller (FMC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Operation Interrupt Enable Register – OIER
This register is used to enable or disable the FMC interrupt function. The FMC generates interrupts to
the controller when corresponding interrupt enable bits are set.
Offset:
0x014
Reset value: 0x0000_0000
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
Reserved
Type/Reset
5
4
3
OREIEN
RW
0
IOCMIEN
RW
0
OBEIEN
ITADIEN
ORFIEN
RW
RW
RW
Bits
Field
Descriptions
[4]
OREIEN
Operation Error Interrupt Enable
0: Operation Error interrupt is disabled
1: Operation Error interrupt is enabled
[3]
IOCMIEN
Invalid Operation Command Interrupt Enable
0: Invalid Operation Command interrupt is disabled
1: Invalid Operation Command interrupt is enabled
[2]
OBEIEN
Option Byte Check Sum Error Interrupt Enable
0: Option Byte Check Sum Error interrupt is disabled
1: Option Byte Check Sum Error interrupt is enabled
[1]
ITADIEN
Invalid Target Address Interrupt Enable
0: Invalid Target Address interrupt is disabled
1: Invalid Target Address interrupt is enabled
[0]
ORFIEN
Operation Finished Interrupt Enable
0: Operation Finish interrupt is disabled
1: Operation Finish interrupt is enabled
Rev. 1.00
51 of 628
0
0
0
August 13, 2012
Flash Memory Controller (FMC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Operation Interrupt and Status Register – OISR
This register indicates the FMC interrupt status which is used to check if a Flash operation has
finished otherwise an error occurs. The status bits are available when the corresponding interrupt
enable bits in the OIER register are set.
Offset:
0x018
Reset value: 0x0001_0000
30
29
28
27
26
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
PPEF
RORFF
RO
RO
0
11
10
9
8
3
2
1
0
1
Reserved
Type/Reset
7
6
Reserved
Type/Reset
Rev. 1.00
5
4
OREF
IOCMF
WC
WC
0
52 of 628
0
OBEF
WC
0
ITADF
WC
0
ORFF
WC
0
August 13, 2012
Flash Memory Controller (FMC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[17]
PPEF
Page Erase/Program Protected Error Flag
0: Page Erase/Program Protected Error does not occur
1: Operation error occurs due to an invalid page erase/program operation being
applied to a protected page
This bit is reset by hardware once a new Flash operation command is committed.
[16]
RORFF
Raw Operation Finished Flag
0: The last Flash operation command has not yet finished
1: The last Flash operation command has finished
This bit is directly connected to the Flash memory for debugging purpose.
[4]
OREF
Operation Error Flag
0: No Flash operation error occurred
1: The last Flash operation is failed
This bit will be set when any Flash operation error such as an invalid command,
program error and erase error, etc., occurs. The ORE interrupt occurs if the OREIEN
bit in the OIER register is set. Reset this bit by writing 1.
[3]
IOCMF
Invalid Operation Command Flag
0: No invalid Flash operation command was set
1: An invalid Flash operation command has been written to the OCMR register
The IOCM interrupt will occur if the IOCMIEN bit in the OIER register is set. Reset
this bit by writing 1.
[2]
OBEF
Option Byte Checksum Error Flag
0: Option Byte Checksum is correct
1: Option Byte Checksum is incorrect
The OBE interrupt will occur if the OBEIEN bit in the OIER register is set. Reset this
bit by writing 1.
[1]
ITADF
Invalid Target Address Flag
0: The target address TADR is valid
1: The target address TADR is invalid
The data in the TADR field must have a range from 0x0000_0000 to 0x1FFF_FFFF.
An ITAD interrupt will occur if the ITADIEN bit in the OIER register is set. Reset this
bit by writing 1.
[0]
ORFF
Operation Finished Flag
0: Flash operation has not finished
1: Last Flash operation has finished
The ORF interrupt will occur if the ORFIEN bit in the OIER register is set. Reset this
bit by writing 1.
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Page Erase/Program Protection Status Register – PPSR
This register indicates the page protection status of the Flash Memory.
Offset:
0x020~0x02C
Reset value: 0xXXXX_XXXX
31
30
29
28
27
26
25
24
RO
X
23
RO
X
RO
22
X
21
RO
X
20
RO
X
19
RO
X
18
RO
X
17
RO
X
16
PPSBn
Type/Reset
RO
X
15
RO
X
RO
14
X
13
RO
X
12
RO
X
11
RO
X
10
RO
X
9
RO
X
8
PPSBn
Type/Reset
RO
X
7
RO
X
RO
6
X
5
RO
X
4
RO
X
3
RO
X
2
RO
X
1
RO
X
0
PPSBn
Type/Reset
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
Bits
Field
Descriptions
[126:0]
PPSBn
Page n Erase/Program Protection Status Bits (n=0~126)
0: The corresponding page n is protected
1: The corresponding page n is not protected
The content of this register is not dynamically updated and will only be reloaded by
the Option Byte loader which is activated when any kind of reset occurs. The erase
or program function of the specific pages is not allowed when the corresponding
bits of the PPSR registers are reset. The reset value of the bits PPSR [126:0] is
determined by the Option Byte, OB_PP [126:0]. The other bits of the OB_PP and
PPSR registers are reserved for future usage.
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
PPSBn
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Security Protection Status Register – CPSR
This register indicates the Flash Memory Security protection status. The content of this register is not
dynamically updated and will only be reloaded by the Option Byte loader which is activated when any
kind of reset occurs.
Offset:
0x030
Reset value: 0xXXXX_XXXX
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Flash Memory Controller (FMC)
31
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
Reserved
Type/Reset
3
OBPSB
CPSB
RO
RO
X
X
Bits
Field
Descriptions
[1]
OBPSB
Option Byte Page Erase/Program Protection Status Bit
0: The Option Byte page is protected
1: The Option Byte page is not protected
The reset value of OPBSB is determined by the OB_CP [1] bit in the Option Byte.
[0]
CPSB
Flash Memory Security Protection Status Bit
0: Flash Memory Security protection is enabled
1: Flash Memory Security protection is disabled
The reset value of the CPSB bit is determined by the OB_CP [0] bit in the Option Byte.
Rev. 1.00
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August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Vector Mapping Control Register – VMCR
This register is used to control the vector mapping. The reset value of the VMCR register is determined
by the status of the external booting pins, BOOT0 and BOOT1 during the power on reset period.
Offset:
0x100
Reset value: 0x0000_000X
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Flash Memory Controller (FMC)
31
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
VMCB
RW
X
RW
X
Bits
Field
Descriptions
[1:0]
VMCB
Vector Mapping Control Bit
The VMCB bits are used to control the mapping source of the first 4-word vectors
addressed from 0x0 to 0xC. The following table shows the vector mapping setup.
BOOT1 BOOT0 VMCB [1:0]
Low
Low
00
Low
High
01
High
Low
10
High
High
11
Descriptions
SRAM booting mode
The vector mapping source is SBVT0~3.
Boot Loader mode
The vector mapping source is the Boot Loader area.
Main Flash mode
The vector mapping source is the Main Flash
Memory area.
The reset value of the VMCR register is determined by the pins status of the external
booting pins BOOT1 and BOOT0 during a power on reset and system reset.
However, when the application program is executed, the vector mapping setting can
be temporarily changed by configuring the VMCB bits to correctly access the first
4-word vectors in the Flash memory, especially when the CPU is booted from the
Boot Loader or the SRAM region.
Rev. 1.00
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August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Flash Cache and Pre-fetch Control Register – CFCR
This register is used for controlling the FMC cache and pre-fetch module.
Offset:
0x200
Reset value: 0x0000_13D1
31
30
29
28
27
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved
FZWPSEN
Type/Reset
0
15
14
FHLAEN
Type/Reset
RW
0
7
Reserved
RW
1
12
0
RW
6
5
4
Reserved
1
0
11
CE
0
DCDB
Type/Reset
13
9
8
Reserved
1
PFBE
RW
10
1
0
0
1
1
3
2
1
0
Reserved
0
WAIT
RW
0
RW
0
RW
1
Bits
Field
Descriptions
[16]
FZWPSEN
Flash Zero Wait-state Power Saving Enable Bit
0: Flash zero wait-state power saving is disabled
1: Flash zero wait-state power saving is enabled
This bit can only be set to 1 to reduce the Flash memory operating current when
the Flash memory is operated in zero wait-state. This bit has no effect when the
wait-state setting is changed to non-zero.
[15]
FHLAEN
Flash Memory Half-cycle Access Enable Bit
0: Half-cycle access is disabled
1: Half-cycle access is enabled
This bit can only be set when the Flash memory is operated in zero wait-state.
Setting this bit to 1 will reduce the Flash memory operation current further when
the system frequency HCLK is less than a frequency of 12MHz. This bit has no
effect when the wait-state setting is changed to non-zero.
[12]
CE
Branch Cache Enable Bit
0: Branch cache is disabled
1: Branch cache is enabled
The branch cache is enabled in default state.
[7]
DCDB
DCODE data Cacheable Enable Bit
0: DCODE data is Cacheable
1: DCODE data is Non-cacheable
The DCODE data is non-cacheable in default state.
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Flash Memory Controller (FMC)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[4]
PFBE
Pre-fetch Buffer Enable Bit
0: Pre-fetch buffer is disabled
1: Pre-fetch buffer is enabled
The pre-fetch buffer is enabled in default state. When the pre-fetch buffer is
disabled, the instruction and data are provided directly by the Flash memory.
[2:0]
WAIT
Flash Wait-state Setting
These bits are used to set the HCLK wait clock during a non-sequential Flash
access. The actual value of the wait clocks is given by (WAIT [2:0]-1). Since a
wide access interface with a pre-fetch buffer and branch cache is provided, the
wait-state of sequential Flash access is very close to zero.
Rev. 1.00
WAIT [2:0]
Wait Status
Allowed HCLK Range
001
0
0MHz < HCLK ≤ 24MHz
010
1
24MHz < HCLK ≤ 48MHz
011
2
48MHz < HCLK ≤ 72MHz
Others
Reserved
Reserved
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August 13, 2012
Flash Memory Controller (FMC)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
SRAM Booting Vector Register n – SBVTn, n=0~3
These registers specify the initial values of the Stack Point, Program Counter, NMI handler address
and Hard Fault handler address for the SRAM Booting mode.
Offset:
0x300~0x30C
Reset value: Various depending on the address offset
30
29
28
27
26
25
24
SBVTn
Type/Reset
RW
X
23
RW
X
RW
22
X
RW
21
X
RW
20
X
RW
19
X
18
RW
X
RW
17
X
16
SBVTn
Type/Reset
RW
X
15
RW
X
RW
14
X
RW
13
X
RW
12
X
RW
11
X
10
RW
X
RW
9
X
8
SBVTn
Type/Reset
RW
X
7
RW
X
RW
6
X
RW
5
X
RW
4
X
RW
3
X
2
RW
X
RW
1
X
0
SBVTn
Type/Reset
RW
X
RW
X
RW
X
RW
X
RW
X
RW
X
RW
X
RW
X
Bits
Field
Descriptions
[31:0]
SBVTn
SRAM Booting Vector n ( n=0~3)
The SRAM Booting Vector 0~3 provides a SRAM booting capability for application
debugging. The contents of the SBVTn registers are re-mapped into the addresses
0x0 to 0xC of the Flash memory CODE area under the SRAM booting mode. Refer
to the description of the VMCR register and BOOT1/BOOT0 boot pins. The following
table shows the purpose and reset value of the SBVTn register. The reset value
provides a fixed setting for program execution during the SRAM booting mode.
These registers can be modified by the debugging tool in order to change the
program execution setting. The reset values of the SBVTn register will be reloaded
only by a power-on reset. Other reset sources will have no effect.
Name
Address Offset
Purpose Descriptions
Reset Value
SBVT0
0x300
Stack point
64KB SRAM: 0x2001_0000
32KB SRAM: 0x2000_8000
SBVT1
0x304
Program counter
0x2000_0151
0x0000_0000
SBVT2
0x308
NMI handler address
SBVT3
0x30C
Hard fault handler address 0x0000_0000
This access width of the registers SBVT0~SBVT3 must be 32-bit (Word access).
8 or 16-bit (Byte or Half-Word) access is not allowed.
Rev. 1.00
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August 13, 2012
Flash Memory Controller (FMC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
5
Power Control Unit (PWRCU)
Introduction
VLDOIN
VBAK
LDOOFF
LCM
VLDOIN
LDO
OKV33
DMOSON
VBAT
PWRSW
BOD
WKUP1
nRST
PWR_CTRL
WKUP4
WKUP2
WAKEUP
RTCOUT
RTC
PORB
LSE
BREG
HSE
SLEEPDEEP
VDD18
POR
3.3V Domain
CortexTM-M3
APB IPs
APB INTF
AHB IPs
SLEEPING
1.8V Domain
Backup Domain
PORB: VBAK Power On Reset
BREG: Backup Registers
LVD/BOD
HSI
WKUP3
LSI
DMOS
LDO: Voltage Regulator
DMOS: Depletion MOS
LVD: Low Voltage Detector
BOD: Brown Out Detector
Figure 11. PWRCU Block Diagram
Rev. 1.00
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Power Control Unit (PWRCU)
The power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power
saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2, and Power-Down modes. These modes
reduce the power consumption and allow the application to achieve the best trade-off between the
conflicting demands of CPU operating time, speed and power consumption. The dash line in the
Figure 11 indicates the power supply source of three digital power domains.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Features
▀
▀
▀
▀
▀
▀
▀
Function Descriptions
Backup Domain
Power Switch
The Backup Domain is powered by the 3.3V power source, V LDOIN, or the battery power source,
VBAT, which is selected by the power switch PWRSW. The operating voltage of the power switch
ranges from 2.7V to 3.6V. If V LDOIN is lower than V BAT, then the power source will be switched
from V LDOIN to V BAT. Therefore, even if V LDOIN is powered down, all the circuitry in the backup
domain can operate normally. This means that the backup register contents will be retained, the
RTC circuitry will operate normally and the low speed oscillators can keep running.
Backup Domain Reset
The Backup Domain reset sources include the Backup Domain power-on-reset (PORB) and the
Backup Domain software reset which is activated by setting the BAKRST bit in the BAKCR
register. The PORB signal forces the device to stay in the reset mode until the V BAK is greater than
1.36V. The slew rate of PORB signal is approximately VBAK /100ms. Also the application software
can trigger Backup Domain software reset by setting the BAKRST bit in the BAKCR register. All
registers of PWRCU and RTC will be reset only by the Backup Domain reset.
LSE, LSI and RTC
The Real Time Clock circuitry clock source can be derived from either the Low Speed Internal RC
oscillator, LSI, or the Low Speed External Crystal oscillator, LSE. Before entering the power saving
mode by executing WFI/WFE instruction, the CortexTM-M3 needs to setup the compare register
with an expected wake-up time and enable the wake-up function to achieve the RTC timer wake-up
event. After entering the power saving mode for a certain amount of time, the Compare Match flag,
CMFLAG, will be asserted to wake-up the device when the compare match event occurs. The details
of the RTC configuration for wake-up timer will be described in the RTC chapter.
Rev. 1.00
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Power Control Unit (PWRCU)
▀
Three power domains: Backup, 3.3V and 1.8V power domains
Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes
Internal Voltage regulator supplies 1.8V voltage source
Additional Depletion MOS supplies 1.8V voltage source with low leakage and low operating
current
Brown Out Detector can issue a system reset or an interrupt when 3.3V power source (VLDOIN) is
lower than 2.6V
Low Voltage Detector can issue an interrupt or wake-up event when VLDOIN is lower than a
programmable threshold voltage ranging from 2.7V to 3.0V
Battery power (VBAT) for backup domain when VLDOIN is shut down
40 bytes of backup registers powered by VBAK for data storage of user application data when in
the Power-Down mode
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
LDO Power Control
The LDO will be automatically switched off when one of the following conditions occurs:
▀ The Power-Down or Deep-Sleep 2 mode is entered
▀ The control bits BODEN=1, BODRIS=0 and the supply power VLDOIN ≤ 2.6V
The LDO will be automatically switched on by hardware if any of the following conditions occurs:
▀ Resume operation from the power saving mode – RTC wake-up, LVD wake-up or WAKEUP pin
rising edge
▀ Detect a falling edge on the external reset pin (nRST)
▀ The control bit BODEN=1 and the supply power VLDOIN > 2.6V
To enter the Deep-Sleep1 mode, the PWRCU will request the LDO to operate in a low current
mode, LCM. To enter the Deep-Sleep2 mode, the PWRCU will turn off the LDO and turn on the
DMOS to supply an alternative 1.8V power.
3.3V Power Domain
Voltage Regulator
The voltage regulator, LDO, Depletion MOS, DMOS, Low voltage Detector, LVD, the Brown out
Detector, BOD and High Speed Internal oscillator, HSI, all operate under the 3.3V power domain.
The LDO can be configured to operate in either normal mode (LDOOFF=0, SLEEPDEEP=0,
I=200mA) or low current mode (LDOOFF=0, SLEEPDEEP=1, I=100mA) to supply the 1.8V
power. An alternative 1.8V power source is the output of the DMOS which has low leakage and
drive current characteristics. It is controlled using the DMOSON bit in the BAKCR register. The
DMOS output has weak drive current capability and can operate only in the Deep-Sleep2 mode for
data retention purposes in the V DD18 power domain.
Low Voltage Detector/Brown Out Detector
The Brown Out Detector, BOD, is used to detect if the 3.3V supply voltage is equal to or lower
than 2.6V. When the BODEN bit in the LVDCSR register is set to 1 and the 3.3V supply voltage is
lower than 2.6V then the BODF flag is active. The PWRCU will regard this as a power down reset
situation and then immediately disable the internal LDO regulator when the BODRIS bit is cleared
to 0 or issue an interrupt to notify the CortexTM-M3 to execute a power down procedure when the
BODRIS bit is set to 1. The Low Voltage Detector, LVD, can also detect whether the 3.3V supply
voltage is lower than a programmable threshold voltage ranging from 2.7V to 3.0V. It is selected by
the LVDS bits in the LVDCSR register. When a low voltage on the V LDOIN power pin is detected,
the LVDF flag will be active and an interrupt will be generated and sent to the CortexTM-M3 if the
LVDEN and LVDIWEN bits in the LVDCSR register are set.
Rev. 1.00
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August 13, 2012
Power Control Unit (PWRCU)
Backup Registers and Isolation Cells
Ten 32-bit registers, up to 40 bytes, are located in the Backup Domain for user application data
storage. These registers are powered by V BAK which constantly supplies power when the 1.8V
power is switched off. The Backup Registers are only reset by the Backup Domain power-on-reset,
PORB, or the Backup Domain software reset, BAKRST. When the device resumes operation
from the 1.8V power, either by Hardware or Software, access to the Backup registers and the RTC
registers are disabled by the isolation cells which protect these registers against possible parasitic
write accesses. To resume access operations, users can disable these isolation cells by setting the
BKISO bit in the LPCR register of the Clock Control Unit to 1.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
1.8V Power Domain
The main functions that include the APB interface for the backup domain, 1.8V power on reset
(POR), CortexTM-M3 logic, AHB/APB peripherals, and so on are located in this power domain.
Once the 1.8V is powered up, the POR will generate a reset sequence (Refer to PORB) on the 1.8V
power domain. Subsequently, to enter the expected power saving mode, the associated control bits
including the LDOOFF, DMOSON, and SLEEPDEEP bits must be configured. Then, once a WFI
or WFE instruction is executed, the device will enter an expected power saving mode which will
be discussed in the following section.
Operation Modes
Run Mode
In the Run mode, the system operates with full functions and all power domains are active. There
are two ways to reduce the power consumption in this mode. The first is to slow down the system
clock by setting the AHBPRE field in the CKCU AHBCFGR register, and the second is to turn
off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers. Reducing the
system clock speed before entering the sleep mode will also help to minimize power consumption.
Additionally, there are several power saving modes to provide maximum optimization between
device performance and power consumption.
Table 11. Operation Mode Definitions
Mode name
Rev. 1.00
Hardware Action
Run
After system reset, CortexTM-M3 fetches instructions to execute.
Sleep
1. CortexTM-M3 core clock will be stopped.
2. Peripherals, Flash and SRAM clocks can be stopped.
Deep-Sleep
1. Stop all clocks in the 1.8V power domain.
2. Disable HSI, HSE, and PLL.
3. Reduce the 1.8V power domain current by turning on the LDO low current
mode or DMOS.
Power-Down
Shut down the 1.8V power domain.
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Power Control Unit (PWRCU)
High Speed Internal Oscillator
The High Speed Internal Oscillator, HSI, is located in the 3.3V power domain. When exiting from
the Deep-Sleep mode, the HSI clock will be configured as the system clock for a certain period by
setting the PSRCEN bit to 1. This bit is located in the Global Clock Control Register, GCCR, in
the Clock Control Unit, CKCU. The system clock will not be switched back to the original clock
source used before entering the Deep-Sleep mode until the original clock source, which may be
either sourced from the PLL or HSE, stabilizes. Also the system will force the HSI oscillator to be
the system clock after a wake up from Power-Down mode since a 1.8V power on reset will occur.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table 12. Enter/Exit Power Saving Modes
Mode
Mode Entry
Cortex -M3
Instruction
TM
Sleep
Deep-Sleep1
Deep-Sleep2
Power-Down
CortexTM-M3
SLEEPDEEP
0
WFI or WFE
(Takes effect)
LDOOFF
X
DMOSON
Mode Exit
X
WFI: Any interrupt
WFE:
Any wake-up event(1) or
Any interrupt (NVIC on) or
Any interrupt with
SEVONPEND=1 (NVIC off)
1
0
0
Any EXTI in event mode or
RTC wake-up or
LVD wake-up(2) or
Wake-up pin rising edge
1
X
1
RTC wake-up or
LVD wake-up(2) or
WAKEUP pin rising edge
0
RTC wake-up or
LVD wake-up(2) or
WAKEUP pin rising edge or
External reset (nRST)
1
1
Notes: 1. Wake-up event means EXTI line in event mode, RTC, LVD, and WAKEUP pin rising edge.
2. If the system allows the LVD activity to wake it up after the system has entered the power saving mode,
the LVDEWEN and LVDEN bits in the LVDCSR register must be set to 1 to make sure that the system
can be woken up by a LVD event and then the LDO regulator can be turned on when system is woken
up from the Deep-Sleep2 and Power-Down modes.
Rev. 1.00
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August 13, 2012
Power Control Unit (PWRCU)
Sleep Mode
By default, only the CortexTM-M3 clock will be stopped in the Sleep mode. Clearing the FMCEN or
SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash clock
or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to access
the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN and
SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep mode,
it is only necessary to clear the SLEEPDEEP bit to 0 and execute a WFI or WFE instruction. The
system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table
provides more information about the power saving modes.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Power-Down Mode
The Power-Down mode is derived from the Deep-Sleep mode of the CortexTM-M3 together with the
additional control bits LDOOFF and DMOSON. To enter the Power-Down mode, users can configure
the registers shown in the preceding Mode-Entering table and execute the WFI or WFE instruction.
A RTC wake-up trigger event, a LVD wake-up, a low to high transition on the external WAKEUP pin
or an external reset (nRST) signal will force the microcontroller out of the Power-Down mode. In the
Power-Down mode, the 1.8V power supply will be turned off. The remaining active power supplies
are the 3.3V I/O power (VDD33) and the Backup Domain power (VBAK).
After a system reset, the PORSTF bit in the RSTCU GRSR register, the PDF and BAKPORF bits
in the BAKSR register should be checked by software to confirm if the device is being resumed
from the Power-Down mode by a backup domain power on reset, an unexpected loss of the 1.8V
power or other reset events (nRST, WDT, …). If the device has entered the Power-Down mode
under the correct firmware procedure, then the PDF bit will be set. The System information could
be saved in the Backup Registers and be retrieved when the 1.8V power domain is powered on
again. More information about the PDF and BAKPORF bits in the BAKSR register and PORSTF
bit in the RSTCU GRSR register is shown in the following table.
Table 13. Power Status After System Reset
BAKPORF PDF PORSTF
Rev. 1.00
Description
1
0
1
Power-up for the first time after the backup domain is reset:
Power on reset when VBAK is applied for the first time or executing
a software reset command on the backup domain.
0
0
1
Restart from unexpected loss of the 1.8V power or other reset
(nRST, WDT, …).
0
1
1
Restart from the Power-Down mode.
1
1
x
Reserved
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August 13, 2012
Power Control Unit (PWRCU)
Deep-Sleep Mode
To enter Deep-Sleep mode, configure the registers as shown in the preceding table and execute
the WFI or WFE instruction. In the Deep-Sleep mode, all clocks including PLL and high speed
oscillator, known as HSI and HSE, will be stopped. In addition, Deep-Sleep1 turns the LDO
into low current mode while Deep-Sleep2 turns off the LDO and uses a DMOS to keep 1.8V
power. Once the PWRCU receives a wake-up event or an interrupt as shown in the preceding
Mode-Exiting table, the LDO will then operate in normal mode and the high speed oscillator will
be enabled. Finally, the CortexTM-M3 will return to Run mode to handle the wake-up interrupt if
required. A Low Voltage Detection also can be regarded as a wake-up event if the corresponding
wake-up control bit LVDEWEN in the LVDCSR register is enabled. The last wake-up event is
a transition from low to high on the external WAKEUP pin sent to the PWRCU to resume from
Deep-Sleep mode. During the Deep-Sleep mode, retaining the register and memory contents will
shorten the wake-up latency.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Map
The following table shows the PWRCU registers and reset values. Note all the registers in this unit
are located in the V BAK backup power domain.
Table 14. PWRCU Register Map
Register
Offset
Description
Reset Value
PWRCU Base Address=0x4006_A000
0x100
Backup Domain Status Register
0x0000_0001
BAKCR
0x104
Backup Domain Control Register
0x0000_0000
BAKTEST
0x108
Backup Domain Test Register
0x0000_0027
HSIRCR
0x10C
HSI Ready Counter Control Register
0x0000_0003
LVDCSR
0x110
Low Voltage/Brown Out Detect Control and Status Register 0x0000_0000
BAKREG0
0x200
Backup Register 0
0x0000_0000
BAKREG1
0x204
Backup Register 1
0x0000_0000
BAKREG2
0x208
Backup Register 2
0x0000_0000
BAKREG3
0x20C
Backup Register 3
0x0000_0000
BAKREG4
0x210
Backup Register 4
0x0000_0000
BAKREG5
0x214
Backup Register 5
0x0000_0000
BAKREG6
0x218
Backup Register 6
0x0000_0000
BAKREG7
0x21C
Backup Register 7
0x0000_0000
BAKREG8
0x220
Backup Register 8
0x0000_0000
BAKREG9
0x224
Backup Register 9
0x0000_0000
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August 13, 2012
Power Control Unit (PWRCU)
Rev. 1.00
BAKSR
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
Backup Domain Status Register – BAKSR
This register indicates backup domain status.
Offset:
0x100
Reset value: 0x0000_0001 (Reset only by Backup Domain reset)
30
29
28
27
26
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
WUPF
Type/Reset
RC
7
6
5
4
Reserved
Type/Reset
3
2
0
1
0
PDF
BAKPORF
RC
0
RC
1
Bits
Field
Descriptions
[8]
WUPF
External WAKEUP Pin Flag
0: The Wakeup pin is not asserted
1: The Wakeup pin is asserted
This bit is set by hardware when the WAKEUP pin asserts and is cleared by a
software read. Software should read this bit to clear it after a system wakes up from
the power saving mode.
[1]
PDF
Power Down Flag
0: Wake-up from abnormal VDD18 shutdown (Loss of VDD18 is unexpected)
1: Wake-up from Power-Down mode. The loss of VDD18 is under expectation
This bit is set by hardware when the system has successfully entered the
Power-Down mode This bit is cleared by a software read.
[0]
BAKPORF
Backup Domain Reset Flag
0: Backup Domain reset does not occur
1: Backup Domain reset occurs
This bit is set by hardware when Backup Domain reset occurs, either a Backup
Domain power on reset or Backup Domain software reset. The bit is cleared by a
software read. This bit must be cleared after the system is first powered, otherwise it
will be impossible to detect when a Backup Domain reset has been triggered. When
this bit is read as 1, a read software loop must be implemented until the bit returns
again to 0. This software loop is necessary to confirm that the Backup Domain is ready
for access. It must be implemented after the Backup Domain is first powered up.
Rev. 1.00
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August 13, 2012
Power Control Unit (PWRCU)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Backup Domain Control Register – BAKCR
This register provides power control bits for the Deep-Sleep and Power-Down modes.
Offset:
0x104
Reset value: 0x0000_0000 (Reset only by Backup Domain reset)
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
WUPIEN
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
DMOSSTS
Type/Reset
RO
Rev. 1.00
RW
RW
6
DMOSON
12
11
Reserved V18RDYSC
0
7
Type/Reset
13
5
0
4
Reserved
RW
3
2
LDOOFF
0
RW
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0
0
WUPEN
RW
0
1
0
Reserved
BAKRST
WO
0
August 13, 2012
Power Control Unit (PWRCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[15]
DMOSSTS
Depletion MOS Status
This bit is set to 1 if the DMOSON bit in this register has been set to 1.
This bit is cleared to 0 if the DMOSON bit has been set to 0 or if a BOD reset
occurred.
[12]
V18RDYSC VDD18 Ready Source Selection
Setting this bit to determine what control signal of isolation cells is used to disable
the isolation function of the V18 to V33 power domain level shifter.
0: BKISO bit in the LPCR register located in the CKCU
1: VDD18 POR
[9]
WUPIEN
External WAKEUP Pin Interrupt Enable
0: Disable WAKEUP pin interrupt function
1: Enable WAKEUP pin interrupt function
The software can set the WUPIEN bit to 1 to assert the LPWUP interrupt in the NVIC
unit when both the WUPEN and WUPF bits are set to1.
[8]
WUPEN
External WAKEUP Pin Enable
0: Disable WAKEUP pin function
1: Enable WAKEUP pin function
The software can set the WUPEN bit as 1 to enable the WAKEUP pin function before
entering the power saving mode. When WUPEN=1, a rising edge on the WAKEUP
pin wakes up the system from the power saving mode. As the WAKEUP pin is active
high, this bit will set an input pull down mode when the bit is high. The corresponding
register bits which should be properly setup are the PBPD [6] to 1 in the PBPDR
register, the PBPU [6] to 0 in the PBPUR register and the PBCFG6 field to 0x01 in
the GPBCFGR register.
Note: This bit is reset by a system reset or a Backup Domain reset. Because this bit
is located in the Backup Domain, after reset activity there will be a delay until
the bit is active. The bit will not be active until the system reset finished and
the Backup Domain ISO signal has been disabled. This means that the bit
can not be immediately set by software after a system reset finished and the
Backup domain ISO signal disabled. The delay time needed is a minimum of
three 32kHz clock periods until the bit reset activity has finished.
[7]
DMOSON
DMOS Control
0: DMOS is OFF
1: DMOS is ON
A DMOS is implemented to provide an alternative voltage source for the 1.8V power
domain when the CortexTM-M3 enters the Deep-Sleep mode (SLEEPDEEP=1).
The control bit DMOSON is set by software and cleared by software or PORB.
If the DMOSON bit is set to 1, the LDO will automatically be turned off when the
CortexTM-M3 enters the Deep-Sleep mode.
[3]
LDOOFF
LDO Operating Mode Control
0: The LDO operates in a low current mode when CortexTM-M3 enters the DeepSleep mode (SLEEPDEEP=1). The VDD18 power is available.
1: The LDO is turned off when the CortexTM-M3 enters the Deep-Sleep mode
(SLEEPDEEP=1). The VDD18 power is not available.
Note: This bit is only available when the DMOSON bit is cleared to 0.
[0]
BAKRST
Backup Domain Software Reset
0: No action
1: Backup Domain Software Reset is activated – includes all the related RTC and
PWRCU registers.
Rev. 1.00
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August 13, 2012
Power Control Unit (PWRCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Backup Domain Test Register – BAKTEST
This register specifies a read-only value for the software to recognize whether backup domain is
ready for access.
Offset:
0x108
Reset value: 0x0000_0027
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Power Control Unit (PWRCU)
31
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
BAKTEST
Type/Reset
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
1
RO
1
Bits
Field
Descriptions
[7:0]
BAKTEST
Backup Domain Test Bits
A constant 0x27 will be read when the Backup Domain is ready for CortexTM-M3
access.
Rev. 1.00
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August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
HSI Ready Counter Control Register – HSIRCR
This register specifies the counter bit length of the HSI ready counter.
Offset:
0x10C
Reset value: 0x0000_0003 (Reset only by Backup Domain reset)
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
HSIRCBL
RW
1
RW
1
Bits
Field
Descriptions
[1:0]
HSIRCBL
HSI Ready Counter Bit Length
00: 4 bits
01: 5 bits
10: 6 bits
11: 7 bits
The HSIRCBL field specifies the bit length of the HSI ready counter. Software can
set the HSIRCBL field to shorten the startup waiting time of the HSI oscillator before
entering the Deep-Sleep mode or Power-Down mode. (HSICRBL is reset only by
Backup Domain reset).
Rev. 1.00
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August 13, 2012
Power Control Unit (PWRCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Low Voltage/Brown Out Detect Control and Status Register – LVDCSR
This register specifies flags, enable bits, and option bits for Low-Voltage/Brown-out detector.
Offset:
0x110
Reset value: 0x0000_0000 (Reset only by Backup Domain reset)
31
30
29
28
27
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved LVDEWEN LVDIWEN
Type/Reset
RW
15
14
0
13
RW
0
12
LVDF
RO
0
11
LVDS
RW
0
RW
0
LVDEN
RW
0
10
9
8
2
1
0
Reserved
BODRIS
BODEN
RW
RW
Reserved
Type/Reset
7
6
5
4
Reserved
BODF
Type/Reset
Rev. 1.00
3
RO
72 of 628
0
0
0
August 13, 2012
Power Control Unit (PWRCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[21]
LVDEWEN
LVD Event Wake-up Enable
0: LVD event wake-up is disabled
1: LVD event wake-up is enabled
Setting this bit to 1 will enable the LVD event wake-up function to wake up the
system when a LVD condition occurs which result in the LVDF bit being asserted. If
the system requires to be woken up from the Deep-Sleep or Power-Down mode by a
LVD condition, this bit must be set to 1.
[20]
LVDIWEN
LVD Interrupt Wake-up Enable
0: LVD interrupt wake-up is disabled
1: LVD interrupt wake-up is enabled
Setting this bit to 1 will enable the LVD interrupt function. When a LVD condition
occurs and the LVDIWEN bit is set to 1, a LVD interrupt will be generated and sent to
the CortexTM-M3 NVIC unit.
[19]
LVDF
Low Voltage Detect Status Flag
0: VDD33 is higher than the specific voltage level
1: VDD33 is equal to or lower than the specific voltage level
When the LVD condition occurs, the LVDF flag will be asserted. When the LVDF flag is
asserted, a LVD interrupt will be generated for CortexTM-M3 if the LVDIWEN bit is set to 1.
However, if the LVDEWEN bit is set to 1 and the LVDIWEN bit is cleared to 0, only a LVD
event will be generated rather than a LVD interrupt when the LVDF flag is asserted.
[18:17]
LVDS
Low Voltage Detect Level Selection
00: 2.7V nominal – default value
01: 2.8V nominal
10: 2.9V nominal
11: 3.0V nominal
[16]
LVDEN
Low Voltage Detect Enable
0: Disable Low Voltage Detect
1: Enable Low Voltage Detect
Setting this bit to 1 will generate a LVD event when the 3.3V power is lower than
the voltage set by LVDS bits. Therefore when the LVD function is enabled before
the system is into the Deep-Sleep2 (DMOS is turn on and LDO is power down) or
Power-Down mode (DMOS and LDO are power down), the LVDEWEN bit has to be
enabled to avoid the LDO does not activate in the meantime when the CPU is woken
up by the low voltage detection activity.
[3]
BODF
Brow Out Detection Flag
If VDD33 < 2.6V, BODF=1. Otherwise, BODF=0.
[1]
BODRIS
BOD Reset or Interrupt Selection
0: Reset the whole device
1: Generate Interrupt
[0]
BODEN
Brown Out Detect Enable
0: Disable Brown Out Detect
1: Enable Brown Out Detect
Rev. 1.00
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August 13, 2012
Power Control Unit (PWRCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Backup Register n – BAKREGn, n=0~9
This register specifies backup register n for storing data during the VDD18 power-off period.
Offset:
0x200~0x224
Reset value: 0x0000_0000 (Reset only by Backup Domain reset)
31
30
29
28
27
26
25
24
RW 0
23
RW
0
RW
22
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
BAKREGn
Type/Reset
RW
0
15
RW
0
RW
14
0
13
RW
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
BAKREGn
Type/Reset
RW
0
7
RW 0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
BAKREGn
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:0]
BAKREGn
Backup Register n (n=0~9)
These registers are used for data storage in general purpose. The contents of
BAKREGn registers will remain even if the VDD18 power is lost.
Rev. 1.00
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August 13, 2012
Power Control Unit (PWRCU)
BAKREGn
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
6
Clock Control Unit (CKCU)
Introduction
fCSIF_MCK,max = 24MHz
CK_MCK
CSIF_MCK
( to CSIF clock output)
8 MHz
HSI RC
Divider
¸2
f CK_PLL,max = 144MHz
CK_PLL
1
HSIEN
PLL
0
CK_HSI
11
CK_HSE
AHB
Prescaler
¸ 1,2,4,8
CK_SYS
LSEEN(Note1)
32 kHz
LSI RC
FCLK
( free running clock)
1
0
CK_LSI
HCLKC
( to CortexTM-M3)
CM3EN
(control by HW)
WDTSRC
CK_WDT
PDMAEN
HCLKD
( to PDMA)
CSIFEN
CK_CSIF
( to CSIF)
WDTEN
RTCSRC(Note1)
LSIEN
STCLK
(to SysTick)
10
Clock
Monitor
32.768 kHz CK_LSE
LSE OSC
CK_USART0
CK_USART1
URnEN
¸8
CK_AHB
HSEEN
fCK_USARTn,max = 72MHz
URPRE
fCK_SYS,max = 144MHz
0x
USBEN
Prescaler
¸1, 2
SW[1:0]
4-16 MHz
HSE XTAL
CK_USB
USBPRE
fCK_AHB,max = 72MHz
PLLEN
fCK_USB,max = 48MHz
Prescaler
¸1, 2, 3
CSIFMPRE
CSIFMEN
PLLSRC
CK_PLL
Prescaler
¸1 ~ 32
HCLKF
( to Flash)
CM3EN
(Note1)
FMCEN
1
0
HCLKS
( to SRAM)
CK_RTC
CM3EN
RTCEN(Note1)
SRAMEN
HCLKBM
( to Bus Matrix)
CKOUTSRC[2:0]
CM3EN
CKOUT
000
CK_MCK
001
CK_AHB/16
010
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
BMEN
HCLKAPB0
( to APB0 Bridge)
CM3EN
APB0EN
HCLKAPB1
( to APB1 Bridge)
CM3EN
APB1EN
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
OPA0EN
WDTEN
Note 1: Those control bits are located at RTC Control Register
(RTC_CTRL)
ADC
Prescaler
¸ 1,2,4,6,8...
PCLK
(OPA, AFIO,
GPIO Port,
ADC, SPI,
USART, I2C,
GPTM, MCTM,
BFTM, EXTI,
RTC, SCI,
Watchdog Timer)
CK_ADC
ADCEN
Figure 12. CKCU Block Diagram
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
The Clock Control unit, CKCU, provides a range of frequencies and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers and clock gating circuitry.
The clocks of the AHB, APB and CortexTM-M3 are derived from the system clock (CK_SYS)
which can source from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC)
use either the LSI or LSE as their clock source. The maximum operating frequency of the system
core clock (CK_AHB) can be up to 72MHz.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Some of the internal clocks can also be wired out via the CKOUT pin for debugging purposes. The
clock monitor circuit can be used to detect an HSE clock failure. Once the HSE clock has ceased
to operate, for whatever reason, the CKCU will force the system clock source to switch to the HSI
clock to prevent a system halt from occurring.
Features
4 to 16MHz High Speed External crystal oscillator – HSE
8MHz High Speed Internal RC oscillator – HSI
32,768Hz Low Speed External crystal oscillator – LSE
32kHz Low Speed Internal RC oscillator – LSI
PLL clock source can be HSE or HSI
HSE clock monitor
Functional Descriptions
High Speed External Crystal Oscillator – HSE
The high speed external crystal oscillator, HSE, which has a frequency from 4 to 16MHz, produces a
highly accurate clock source for use as the system clock. The crystal with a specific frequency must
be connected and located close to the two HSE pins, XTALIN/XTALOUT. The external resistor and
capacitor components connected to the crystal are necessary for proper oscillation.
XTALIN
XTALOUT
Rf1
C1
4~16 MHz
Crystal
Rd
C2
Figure 13. External HSE Crystal, Ceramic, and Resonator
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
▀
▀
▀
▀
▀
▀
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock
Control Register GCCR. The HSERDY flag in the Global Clock Status Register GCSR indicates
if the high-speed external crystal oscillator is stable. When the HSE is powered up, it will not be
released for use until this HSERDY bit is set by the hardware. This specific delay period is known
as the oscillator “Start-up time”. As the HSE becomes stable, an interrupt will be generated if the
related interrupt enable bit HSERDYIE in the Global Clock Interrupt Register GCIR is set. At this
point the HSE clock can be used directly as the system clock source or the PLL input clock.
The frequency accuracy of the HSI can be calibrated by the manufacturer, but its operating
frequency is still less accurate than HSE. The applications requirements, environmens and cost
will determine which oscillator type is selected.
If the HSE or PLL is the system clock source, to minimize the time required for the system to
recover from the Deep-Sleep Mode, the software can set the PSRCEN bit (Power Saving Wake-up
RC Clock Enable) to 1 to force the HSI clock to be system clock when the system initially wake-up.
Subsequently, the system clock will automatically be switched back to the original clock source,
HSE or PLL, when the original clock source ready flag is asserted. This function will reduce the
wake-up time when using the HSE or PLL as the system clock.
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
High Speed Internal RC Oscillator – HSI
The high speed internal RC oscillator, HSI, has a fixed frequency of 8MHz and is the default
clock source selection for the CPU when the device is powered up. The HSI oscillator provides
a lower cost type clock source as no external components are required. The HSI RC oscillator
can be switched on or off using the HSIEN bit in the Global Clock Control Register GCCR. The
HSIRDY flag in the Global Clock Status Register GCSR is used to indicate if the internal RC
oscillator is stable. The start-up time of the HSI oscillator is shorter than the HSE crystal oscillator.
An interrupt can be generated if the related interrupt enable bit, HSIRDYIE, in the Global Clock
Interrupt Register, GCIR, is set when the HSI becomes stable. The HSI clock can also be used as
the PLL input clock.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Phase Locked Loop – PLL
The internal Phase Locked Loop, PLL, can provide 8~144MHz clock output which is 2~36 multiples
of a fundamental reference frequency of 4~16MHz. The PLL includes a reference divider, feedback
dividers, a digital phase frequency detector (PD), a current-controlled charge pump (CP), an internal
loop filter and a voltage-controlled oscillator (VCO) to achieve a stable phase-locked state.
CKIN = 4~16 MHz
Ref
Divider
PD
CP
VCO
Loop
filter
Feedback
Divider2
Output
Divider1
Output
Divider2
PLLout=8~144MHz
S1~S0
Feedback
Divider1
/4
B5~B0
Figure 14. PLL Block Diagram
The PLL output clock frequency can be determined by the following formula:
PLLOUT = CK IN *
NF1* NF 2
NF 2
4 * NF 2
= CK IN *
= CK IN *
NR * NO1* NO 2
2 * 2 * NO 2
NO 2
where NR=Ref divider=2, NF1=Feedback divider 1=4, NF2=Feedback divider 2=1~64,
NO1=Output divider 1=2, NO2=Output divider 2=1, 2, 4, or 8
Consider a duty cycle of 50% and where both input and output frequencies are divided by 2. If a
given clock PLL input clock source frequency, CK IN, generates a specific PLL output frequency,
then it is recommended to use a higher value for NF2 in order to increase PLL stability and
reduce jitter at the expense of settling time. The setup bits of the output and feedback divider 2
are described in the following two tables. All the setup bits named S1~S0 and B5~B0 in the tables
are defined in the PLL Configuration Register PLLCFGR and the PLL Control Register PLLCR in
the Register Definition section. Note that the VCOOUT frequency must have a range from 64MHz
to 144MHz. If the selected configuration exceeds this range, the PLL output frequency cannot be
guaranteed to match the above PLLOUT formula.
The PLL can be switched on or off by using the PLLEN bit in the Global Clock Control Register
GCCR. The PLLRDY flag in the Global Clock Status Register GCSR will indicate if the PLL clock
is stable. An interrupt can be generated if the related interrupt enable bit, PLLRDYIE, in the Global
Clock Interrupt Register, GCIR, is set as the PLL becomes stable.
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
VCOout=64~144MHz
/2
/2
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table 15. Output Divider 2 Setting
Output divider 2 setup bits S1~S0
(POTD bits in the PLLCFGR register)
NO2 (Output divider 2 value)
00
1
01
2
10
4
11
8
Feedback divider 2 setup bits B5~B0
(PFBD bits in the PLLCFGR register)
NF2 (Feedback divider 2 value)
000000
64
000001
1
000010
2
000011
3
000100
4
000101
5
000110
6
000111
7
001000
8
001001
9
001010
10
001011
11
001100
12
001101
13
001110
14
......
......
111111
Rev. 1.00
63
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August 13, 2012
Clock Control Unit (CKCU)
Table 16. Feedback Divider 2 value Setting
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Low Speed External Crystal Oscillator – LSE
XTAL32KIN
XTAL32KOUT
Rf2
C3
32768Hz
C4
Figure 15. External Crystal, Ceramic, and Resonator for LSE
Low Speed Internal RC Oscillator – LSI
The low speed internal RC oscillator has a frequency of about 32kHz and is a low power clock source
for the Real Time Clock circuit or the Watchdog Timer. The LSI offers a low cost clock source as
no external components are required. The LSI RC oscillator can be switched on or off by using the
LSIEN bit in the RTC Control Register, RTCCR. The frequency accuracy can be calibrated using the
configuration options. The LSIRDY flag in the Global Clock Status Register GCSR will indicate if
the LSI clock is stable. An interrupt can be generated if the related interrupt enable bit LSIRDYIE in
the Global Clock Interrupt Register GCIR is set when the LSI becomes stable.
Rev. 1.00
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Clock Control Unit (CKCU)
The low speed external crystal or ceramic resonator oscillator, which has a frequency of 32,768Hz,
produces a low power but highly accurate clock source for the Real-Time-Clock circuit and the
Watchdog Timer. The crystal or ceramic resonator must be located close to the two LSE pins,
XTAL32KIN and XTAL32KOUT. Their external resistors and capacitors are necessary for proper
oscillation. The LSE oscillator can be switched on or off using the LSEEN bit in the RTC Control
Register RTCCR. The LSERDY flag in the Global Clock Status Register GCSR will indicate if the
LSE clock is stable. An interrupt can be generated if the related interrupt enable bit LSERDYIE, in
the Global Clock Interrupt Register GCIR is set when the LSE becomes stable.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Clock Ready Flag
System Clock Selection – CK_SYS
After the system reset, the default CK_SYS source will be HSI and can be switched to HSE or
PLL by changing the System Clock Switch bits, SW, in the Global Clock Control Register, GCCR.
When the SW value is changed, the CK_SYS will continue to operate using the original clock
source until the target clock source is stable. The corresponding clock ready status is in the Global
Clock Status Register, GCSR, and the clock source usage can be found in the Clock Source Status
Register, CKST. When a clock source is used directly by the CK_SYS or the PLL, it is not possible
to stop it.
HSE Clock Monitor
The HSE clock monitor function is enabled by the HSE Clock Monitor Enable bit, CKMEN, in
the Global Clock Control Register, GCCR. This function should be enabled after the HSE start-up
delay and disabled when the HSE is stopped. Once the HSE failure is detected, the HSE will be
automatically disabled. The HSE Clock Stuck Flag, CKSF, in the Global Clock Interrupt Register,
GCIR, will be set and the HSE failure event will be generated if the Clock Stuck Interrupt Enable
bit, CKSIE, in the GCIR register is set. This failure interrupt is connected to the Non-Maskable
Interrupt, NMI, of the CortexTM-M3. If the HSE is selected as the clock source of CK_SYS or PLL,
the HSE failure will force the CK_SYS source to HSI and the PLL will be disabled automatically.
Clock Output Capability
The clock output capability of HT32 series MCU is ranging from 32kHz to 9MHz. There are
several clock signals can be selected via the CKOUT Clock Source Selection bits, CKOUTSRC,
in the Global Clock Configuration Register, GCFGR. The corresponding GPIO pin should be
configured in the properly Alternate Function I/O (AFIO) mode to output the selected clock signal.
Table 17. CKOUT Clock Source
Rev. 1.00
CKOUTSRC
Clock Source
000
CK_MCK
001
CK_AHB/16
010
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
111
Reserved
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Clock Control Unit (CKCU)
The CKCU provides the corresponding clock ready flags of the HSI, HSE, PLL, LSI, and LSE
to indicate if these clocks are stable. Before users select the clock as the system clock source or
other purpose, it is necessary to confirm the specific clock ready flag is set. Software can check
the specific clock is ready or not by polling the individual clock ready status bit in the GCSR
register. Additionally, the CKCU can trigger an interrupt to notify the specific clock is ready if the
corresponding interrupt enable bit in the GCIR register is set. Software should clear the interrupt
status bit in the GCIR register during the interrupt service routine.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Map
The following table shows the CKCU registers and their reset value.
Table 18. CKCU Register Map
Register
Offset
Description
Reset Value
CKCU Base Address=0x4008_8000
0x000
Global Clock Configuration Register
0x0000_0102
GCCR
0x004
Global Clock Control Register
0x0000_0803
GCSR
0x008
Global Clock Status Register
0x0000_0028
GCIR
0x00C
Global Clock Interrupt Register
0x0000_0000
PLLCFGR
0x018
PLL Configuration Register
0x0000_0000
PLLCR
0x01C
PLL Control Register
0x0000_0000
AHBCFGR
0x020
AHB Configuration Register
0x0001_0000
AHBCCR
0x024
AHB Clock Control Register
0x0000_00E5
APBCFGR
0x028
APB Configuration Register
0x0001_0000
APBCCR0
0x02C
APB Clock Control Register 0
0x0000_0000
APBCCR1
0x030
APB Clock Control Register 1
0x0000_0000
CKST
0x034
Clock Source Status Register
0xC100_0000
LPCR
0x300
Low Power Control Register
0x0000_0000
MCU Debug Control Register
0x0000_0000
MCUDBGCR 0x304
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Clock Control Unit (CKCU)
GCFGR
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
Global Clock Configuration Register – GCFGR
This register specifies the clock source for the CSIF/USB/PLL/USART/Watchdog Timer/CKOUT circuit.
Offset:
0x000
Reset value:
0x0000_0102
30
29
28
27
26
LPMOD
Type/Reset
RO
0
23
RO
0
22
RW
15
0
RW
14
RO
0
21
0
24
CSIFMPRE
RW
0
20
USBPRE
Type/Reset
25
RW
0
RW
19
0
RW
18
URPRE
RW
13
0
RW
0
RW
17
Reserved
0
12
11
10
9
8
Reserved
PLLSRC
Type/Reset
RW
7
6
5
4
Reserved
3
2
1
WDTSRC
Type/Reset
Rev. 1.00
0
16
RW
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0
1
0
CKOUTSRC
RW
0
RW
1
RW
0
August 13, 2012
Clock Control Unit (CKCU)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[31:29]
LPMOD
Lower Power Mode Status
000: Device in initial status
001: Device has been woken up from Sleep mode
010: Device has been woken up from Deep Sleep mode 1
011: Device has been woken up from Deep Sleep mode 2
100: Device has been woken up from Power Down mode
Others: Reserved
This field is set and reset by hardware.
[28:24]
CSIFMPRE
CSIF_MCK Clock Prescaler Selection
CK_MCK=CK_PLL/(CSIFMPRE + 1)/2
00000: CK_MCK=CK_PLL/2
00001: CK_MCK=CK_PLL/4
......
11111: CK_MCK=CK_PLL/64
This field is set and reset by software to control the CSIF_MCK clock prescaler division.
[23:22]
USBPRE
USB Clock Prescaler Selection
00: CK_USB=CK_PLL
01: CK_USB=CK_PLL/2
10: CK_USB=CK_PLL/3
11: Reserved
This field is set and reset by software to control the USB clock prescaler division.
[21:20]
URPRE
USART Clock Prescaler Selection
00: CK_USART=CK_AHB
01: CK_USART=CK_AHB/2
Others: Reserved
This field is set and reset by software to control the USART clock prescaler value.
[8]
PLLSRC
PLL Clock Source Selection
0: External 4~16MHz crystal oscillator clock is selected (HSE)
1: Internal 8MHz RC oscillator clock is selected (HSI)
This bit is set and reset by software to control the PLL clock source.
[3]
WDTSRC
Watchdog Timer Clock Source Selection
0: Internal LSI 32kHz RC oscillator clock selected
1: External LSE 32,768Hz crystal oscillator clock selected
This bit is set and reset by software to control the Watchdog Timer clock source.
[2:0]
CKOUTSRC
CKOUT Clock Source Selection
Set and reset by software.
000: CK_MCK selected
001: (CK_AHB/16) selected
010: (CK_SYS/16) selected
011: (CK_HSE/16) selected
100: (CK_HSI/16) selected
101: CK_LSE selected
110: CK_LSI selected
111: Reserved
Rev. 1.00
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Clock Control Unit (CKCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Global Clock Control Register – GCCR
This register specifies the clock enable bits.
Offset:
0x004
Reset value:
0x0000_0803
31
30
29
28
27
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved
PSRCEN
Type/Reset
RW
15
14
13
12
Reserved
Type/Reset
7
6
5
4
11
10
0
9
HSIEN
HSEEN
PLLEN
RW
RW
3
2
0
Rev. 1.00
1
Reserved
0
SW
RW
85 of 628
0
0
Reserved
Type/Reset
RW
8
RW
1
CKMEN
1
RW
1
August 13, 2012
Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[17]
PSRCEN
Power Saving Wakeup RC Clock Enable
0: No action
1: Use HSI as the temporary CK_SYS source after waking up from Deep-Sleep1
or Deep-Sleep2
When the PSRCEN bit is set to 1, the HSI will be used as the clock source of the
CK_SYS after waking up from the Deep-Sleep1 or Deep-Sleep2 mode. This means
that the instruction can be executed early before the original CK_SYS source such
as HSE or PLL is stable.
[16]
CKMEN
HSE Clock Monitor Enable
0: Disable the External 4~16MHz crystal oscillator (HSE) clock monitor
1: Enable the External 4~16MHz crystal oscillator (HSE) clock monitor
When the hardware detects that the HSE clock is stuck at a low or high state, the
internal hardware will switch the system clock to be the internal high speed HSI RC
clock. The way to recover the original system clock is by either an external reset,
power on reset or clearing CKSF by software.
NOTE: When the HSE clock monitor is enabled, the hardware will automatically enable
the HSI internal RC oscillator regardless of the control bit, HSIEN, state.
[11]
HSIEN
Internal High Speed oscillator Enable
0: Internal 8MHz RC oscillator disabled
1: Internal 8MHz RC oscillator enabled
Set and reset by software. This bit cannot be reset if the HSI clock is used as the
system clock.
[10]
HSEEN
External High Speed oscillator Enable
0: External 4~16MHz crystal oscillator disabled
1: External 4~16MHz crystal oscillator enabled
Set and reset by software. This bit cannot be reset if the HSE clock is used as the
system clock or the PLL input clock.
[9]
PLLEN
PLL Enable
0: PLL is switched off
1: PLL is switched on
Set and reset by software. This bit cannot be reset if the PLL clock is used as the
system clock.
[1:0]
SW
System Clock Switch
0X: Select CK_PLL as the CK_SYS source
10: Select CK_HSE as the CK_SYS source
11: Select CK_HSI as the CK_SYS source
Set by software to select the CK_SYS source. Because the change of CK_SYS has
inherent latency, software should read these bits to confirm whether the switching is
complete or not. The switch will be forced to HSI by HSE clock monitor when the HSE
failure is detected and the HSE is selected as the clock source of CK_SYS or PLL.
Rev. 1.00
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Clock Control Unit (CKCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Global Clock Status Register – GCSR
This register indicates the clock ready status.
Offset:
0x008
Reset value:
0x0000_0028
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
Reserved
LSIRDY
LSERDY
Type/Reset
RO 1
RO
3
0
HSIRDY
RO
1
HSERDY
RO
0
PLLRDY
RO
Reserved
0
Bits
Field
Descriptions
[5]
LSIRDY
LSI Internal Low Speed Oscillator Ready Flag
0: LSI oscillator not ready
1: LSI oscillator ready
This bit is set by hardware to indicate if the LSI oscillator is stable and ready for use.
[4]
LSERDY LSE External Low Speed Oscillator Ready Flag
0: LSE oscillator not ready
1: LSE oscillator ready
This bit is set by hardware to indicate if the LSE oscillator is stable and ready for use.
[3]
HSIRDY
[2]
HSERDY HSE High Speed External Clock Ready Flag
0: HSE oscillator not ready
1: HSE oscillator ready
This bit is set by hardware to indicate if the HSE oscillator is stable and ready for use.
[1]
PLLRDY PLL Clock Ready Flag
0: PLL not ready
1: PLL ready
This bit is set by hardware to indicate if the PLL output clock is stable and ready for use.
Rev. 1.00
HSI High Speed Internal Oscillator Ready Flag
0: HSI oscillator not ready
1: HSI oscillator ready
This bit is set by hardware to indicate if the HSI oscillator is stable and ready for use.
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Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Global Clock Interrupt Register – GCIR
This register specifies the interrupt enable and flag bits.
Offset:
0x00C
Reset value:
0x0000_0000
31
30
29
28
27
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE Reserved
Type/Reset
RW
15
0
RW
14
0
13
RW
0
12
RW
0
11
RW
0
CKSIE
RW
10
9
8
2
1
0
0
Reserved
Type/Reset
7
6
5
Reserved LSIRDYF
Type/Reset
WC
0
4
3
LSERDYF HSIRDYF
WC
0
WC
0
HSERDYF
WC
0
PLLRDYF Reserved
WC
0
CKSF
WC
0
Bits
Field
Descriptions
[22]
LSIRDYIE
LSI Ready Interrupt Enable
0: Disable the LSI stabilization interrupt
1: Enable the LSI stabilization interrupt
This bit is used to control whether the LSI stabilization interrupt is enabled or disabled.
[21]
LSERDYIE
LSE Ready Interrupt Enable
0: Disable the LSE stabilization interrupt
1: Enable the LSE stabilization interrupt
This bit is used to control whether the LSE stabilization interrupt is enabled or disabled.
[20]
HSIRDYIE
HSI Ready Interrupt Enable
0: Disable the HSI stabilization interrupt
1: Enable the HSI stabilization interrupt
This bit is set and reset by software used to enable or disable the HSI stabilization
interrupt.
[19]
HSERDYIE
HSE Ready Interrupt Enablethe
0: Disable the HSE stabilization interrupt
1: Enable the HSE stabilization interrupt
This bit is set and reset by software used to enable or disable the HSE stabilization
interrupt.
[18]
PLLRDYIE
PLL Ready Interrupt Enable
0: Disable the PLL stabilization interrupt
1: Enable the PLL stabilization interrupt
This bit is set and reset by software used to enable or disable the PLL stabilization
interrupt.
[16]
CKSIE
Clock Stuck Interrupt Enable
0: Disable the clock fail interrupt
1: Enable the clock fail interrupt
This bit is set and reset by software used to enable or disable the clock monitor
interrupt.
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[6]
LSIRDYF
LSI Ready Interrupt Flag
0: No LSI stabilization clock ready interrupt generated
1: LSI stabilization interrupt generated
This bit is cleared by writing 1 into it and set by hardware when the Internal 32kHz
RC oscillator clock is stable and the LSIRDYIE bit is set.
[5]
LSERDYF
LSE Ready Interrupt Flag
0: No LSE stabilization interrupt generated
1: LSE stabilization interrupt generated
This bit is cleared by writing 1 into it and set by hardware when the External
32,768Hz crystal oscillator clock is stable and the LSERDYIE bit is set.
[4]
HSIRDYF
HSI Ready Interrupt Flag
0: No HSI stabilization interrupt generated
1: HSI stabilization interrupt generated
This bit is cleared by writing 1 into it and set by hardware when the internal 8MHz
RC oscillator clock is stable and the HSIRDYIE bit is set.
[3]
HSERDYF
HSE Ready Interrupt Flag
0: No HSE stabilization interrupt generated
1: HSE stabilization interrupt generated
This bit is cleared by writing 1 into it and set by hardware when the External 4~16MHz
crystal oscillator clock is stable and the HSERDYIE bit is set.
[2]
PLLRDYF
PLL Ready Interrupt Flag
0: No PLL stabilization interrupt generated
1: PLL stabilization interrupt generated
This bit is cleared by writing 1 into it and set by hardware when the PLL is stable and
the PLLRDYIE bit is set.
[0]
CKSF
HSE Clock Stuck Interrupt Flag
0: Clock operating normally
1: HSE clock stuck
This bit is cleared by writing 1 into it and set by hardware when the HSE clock is
stuck and the CKSIE bit is set.
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
PLL Configuration Register – PLLCFGR
This register specifies the PLL configuration.
Offset:
0x018
Reset value:
0x0000_0000
31
30
29
28
27
26
PFBD [5:1]
Type/Reset
RW
23
22
21
PFBD[0]
Type/Reset
RW
15
0
0
20
RW
0
19
POTD
RW
0
24
RW
14
13
RW
0
18
RW
0
RW
17
16
10
9
8
2
1
0
0
Reserved
0
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
Bits
Field
Descriptions
[28:23]
PFBD
PLL VCO Output Clock Feedback Divider (B5~B0 in Figure 14)
Feedback Divider divides the output clock from the PLL VCO.
[22:21]
POTD
PLL Output Clock Divider (S1~S0 in Figure 14)
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
Reserved
25
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
PLL Control Register – PLLCR
This register specifies the PLL Bypass mode.
Address offset:
0x01C
Reset value:
0x0000_0000
31
30
29
28
RW
23
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
0
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
Bits
Field
Descriptions
[31]
PLLBPS
PLL Bypass Mode Enable
0: Disable the PLL Bypass mode
1: Enable the PLL Bypass mode in which the PLL output clock PLLOUT is equal to
the CKIN clock (refer to the PLL Block diagram)
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
PLLBPS
Type/Reset
27
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
AHB Configuration Register – AHBCFGR
This register specifies the system clock frequency.
Offset:
0x020
Reset value:
0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
AHBPRE
RW
0
Bits
Field
Descriptions
[1:0]
AHBPRE
AHB Pre-Scaler
00: CK_AHB=CK_SYS
01: CK_AHB=CK_SYS/2
10: CK_AHB=CK_SYS/4
11: CK_AHB=CK_SYS/8
This field is set and reset by software to control the AHB clock division ratio.
Rev. 1.00
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RW
0
August 13, 2012
Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
AHB Clock Control Register – AHBCCR
This register specifies the AHB clock enable bits.
Offset:
0x024
Reset value:
0x0000_00E5
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
CSIFMEN
Type/Reset
RW
7
6
APB1EN
Type/Reset
Rev. 1.00
RW
1
5
APB0EN
RW
1
4
BMEN
RW
1
PDMAEN
RW
0
93 of 628
3
2
Reserved
SRAMEN
RW
0
CSIFEN
RW
0
1
0
Reserved
Reserved
1
August 13, 2012
Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[9]
CSIFMEN
CSIF_MCK Clock Output Enable
0: CSIF_MCK clock disabled
1: CSIF_MCK clock enabled
This bit is set and reset by software used to enable or disable the CSIF_MCK clock
output.
[8]
CSIFEN
CSIF Clock Enable
0: CSIF clock disabled
1: CSIF clock enabled
This bit is set and reset by software used to enable or disable the CSIF circuitry clock.
[7]
APB1EN
APB1 bridge Clock Enable
0: APB1 bridge clock disabled in Sleep mode
1: APB1 bridge clock enabled in Sleep mode
This bit is set and reset by software. Note that this bit is only available in the Sleep
mode. If the APB1 bridge is not used in the Sleep mode, users can clear the APB1EN
bit to 0 to reduce the power consumption before the device enters the Sleep mode.
[6]
APB0EN
APB0 bridge Clock Enable
0: APB0 bridge clock disabled in Sleep mode
1: APB0 bridge clock enabled in Sleep mode
This bit is set and reset by software. Note that this bit is only available in the Sleep
mode. If the APB0 bridge is not used in the Sleep mode, users can clear the APB0EN
bit to 0 to reduce the power consumption before the device enters the Sleep mode.
[5]
BMEN
Bus Matrix Clock Enable
0: Bus Matrix clock disabled in Sleep mode
1: Bus Matrix clock enabled in Sleep mode
This bit is set and reset by software. Note that this bit is only available in the Sleep mode.
If the Bus Matrix bridge is not used in the Sleep mode, users can clear the BMEN bit to 0
to reduce the power consumption before the device enters the Sleep mode.
[4]
PDMAEN
Peripheral DMA Clock Enable
0: PDMA clock disabled
1: PDMA clock enabled
This bit is set and reset by software. The PDMA can operate when the processor is in
the Sleep mode. However, the relevant clocks of the AHB bus slave, such as SRAM or
Flash, or the APB peripherals, such as I2C or SPI, which communicate with the PDMA
in the Sleep mode have to be enabled before entering the Sleep mode.
[2]
SRAMEN
SRAM Clock Enable
0: SRAM clock disabled in Sleep mode
1: SRAM clock enabled in Sleep mode
This bit is set and reset by software. Note that this bit is only available in the Sleep
mode. If the SRAM is not used in the Sleep mode, users can clear the SRAMEN bit to 0
to reduce the power consumption before the device enters the Sleep mode.
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
APB Configuration Register – APBCFGR
This register specifies the frequency of the A/D Converter clock.
Offset:
0x028
Reset value:
0x0001_0000
31
30
29
28
27
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved
ADCDIV
Type/Reset
RW
15
14
13
12
11
0
RW
0
RW
10
9
8
2
1
0
1
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
Bits
Field
Descriptions
[18:16]
ADCDIV
A/D Converter Clock Frequency Division Selection
000: Reserved
001: CK_ADC=(CK_AHB/2)
010: CK_ADC=(CK_AHB/4)
011: CK_ADC=(CK_AHB/8)
100: CK_ADC=(CK_AHB/16)
101: CK_ADC=(CK_AHB/32)
110: CK_ADC=(CK_AHB/64)
111: CK_ADC=(CK_AHB/6)
This field is set and reset by software to select the A/D Converter clock division ratio.
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
APB Clock Control Register 0 – APBCCR0
This register specifies several APB peripheral clock enable bits.
Offset:
0x02C
Reset value:
0x0000_0000
31
30
29
28
27
26
25
24
SCIEN
RW
23
22
21
20
Reserved
Type/Reset
15
Type/Reset
14
13
EXTIEN
AFIOEN
RW
RW
7
Type/Reset
0
19
17
PEEN
PDEN
PCEN
PBEN
RW
RW
RW
0
12
0
11
0
10
Reserved
0
6
5
4
Reserved
SPI1EN
SPI0EN
RW
RW
0
16
RW
3
0
Bits
Field
Descriptions
[24]
SCIEN
Smart Card Interface Clock Enable
0: Smart Card clock disabled
1: Smart Card clock enabled
This bit is set and reset by software.
[20]
PEEN
GPIO Port E Clock Enable
0: Port E clock disabled
1: Port E clock enabled
This bit is set and reset by software.
[19]
PDEN
GPIO Port D Clock Enable
0: Port D clock disabled
1: Port D clock enabled
This bit is set and reset by software.
[18]
PCEN
GPIO Port C Clock Enable
0: Port C clock disabled
1: Port C clock enabled
This bit is set and reset by software.
[17]
PBEN
GPIO Port B Clock Enable
0: Port B clock disabled
1: Port B clock enabled
This bit is set and reset by software.
[16]
PAEN
GPIO Port A Clock Enable
0: Port A clock disabled
1: Port A clock enabled
This bit is set and reset by software.
[15]
EXTIEN
External Interrupt Clock Enable
0: EXTI clock disabled
1: EXTI clock enabled
This bit is set and reset by software.
Rev. 1.00
18
96 of 628
0
0
9
PAEN
RW
0
8
UR1EN
UR0EN
RW
RW
0
0
2
1
0
Reserved
I2C1EN
I2C0EN
RW
RW
0
0
August 13, 2012
Clock Control Unit (CKCU)
Reserved
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[14]
AFIOEN
Alternate Function I/O Clock Enable
0: AFIO clock disabled
1: AFIO clock enabled
This bit is set and reset by software.
[9]
UR1EN
USART1 Clock Enable
0: USART1 clock disabled
1: USART1 clock enabled
This bit is set and reset by software.
[8]
UR0EN
USART0 Clock Enable
0: USART0 clock disabled
1: USART0 clock enabled
This bit is set and reset by software.
[5]
SPI1EN
SPI1 Clock Enable
0: SPI1 clock disabled
1: SPI1 clock enabled
This bit is set and reset by software.
[4]
SPI0EN
SPI0 Clock Enable
0: SPI0 clock disabled
1: SPI0 clock enabled
This bit is set and reset by software.
[1]
I2C1EN
I2C1 Clock Enable
0: I2C1 clock disabled
1: I2C1 clock enabled
This bit is set and reset by software.
[0]
I2C0EN
I2C0 Clock Enable
0: I2C0 clock disabled
1: I2C0 clock enabled
This bit is set and reset by software.
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Clock Control Unit (CKCU)
Bits
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
APB Clock Control Register 1 – APBCCR1
This register specifies several APB peripheral clock enable bits.
Offset:
0x030
Reset value:
0x0000_0000
31
30
29
28
27
26
25
24
ADCEN
RW
23
22
OPA1EN
Type/Reset
RW
0
Rev. 1.00
20
19
OPA0EN
RW
14
Reserved
USBEN
RW
Reserved
12
11
10
Reserved
Reserved
RTCEN
0
4
Reserved
WDTEN
RW
3
0
98 of 628
0
9
2
Reserved
1
BFTM0EN
RW
0
8
GPTM1EN
RW
5
16
BFTM1EN
0
6
17
RW
13
7
RW
18
0
15
Type/Reset
Type/Reset
21
0
0
GPTM0EN
RW
0
0
MCTMEN
RW
0
August 13, 2012
Clock Control Unit (CKCU)
Reserved
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[24]
ADCEN
ADC Clock Enable
0: ADC clock disabled
1: ADC clock enabled
This bit is set and reset by software.
[23]
OPA1EN
OPA/CMP 1 Clock Enable
0: OPA/CMP 1 clock disabled
1: OPA/CMP 1 clock enabled
This bit is set and reset by software.
[22]
OPA0EN
OPA/CMP 0 Clock Enable
0: OPA/CMP 0 clock disabled
1: OPA/CMP 0 clock enabled
This bit is set and reset by software.
[17]
BFTM1EN
BFTM1 Clock Enable
0: BFTM1 clock disabled
1: BFTM1 clock enabled
This bit is set and reset by software.
[16]
BFTM0EN
BFTM0 Clock Enable
0: BFTM0 clock disabled
1: BFTM0 clock enabled
This bit is set and reset by software.
[14]
USBEN
USB Clock Enable
0: USB clock disabled
1: USB clock enabled
This bit is set and reset by software.
[9]
GPTM1EN
GPTM1 Clock Enable
0: GPTM1 clock disabled
1: GPTM1 clock enabled
This bit is set and reset by software.
[8]
GPTM0EN
GPTM0 Clock Enable
0: GPTM0 clock disabled
1: GPTM0 clock enabled
This bit is set and reset by software.
[6]
RTCEN
RTC Clock Enable
0: RTC clock disabled
1: RTC clock enabled
This bit is set and reset by software.
[4]
WDTEN
Watchdog Timer Clock Enable
0: Watchdog Timer clock disabled
1: Watchdog Timer clock enabled
This bit is set and reset by software.
[0]
MCTMEN
MCTM Clock Enable
0: MCTM0 clock disabled
1: MCTM0 clock enabled
This bit is set and reset by software.
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Clock Control Unit (CKCU)
Bits
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Clock Source Status Register – CKST
This register specifies the clock source status.
Offset:
0x034
Reset value:
0xC100_0000
31
30
29
RO
23
1
RO
27
26
25
Reserved
HSIST
1
RO
22
21
20
24
19
0
18
RO
0
17
HSEST
RO
14
13
12
11
10
5
RO
0
8
PLLST
RO
6
0
9
Reserved
Type/Reset
7
1
16
Reserved
Type/Reset
15
RO
4
0
3
RO
0
2
RO
1
0
RO
0
0
Reserved
Type/Reset
Bits
Field
Descriptions
[31:30]
CKSWST
Clock Switch Status
0x: CK_PLL used as system clock
10: CK_HSE used as system clock
11: CK_HSI used as system clock
[26:24]
HSIST
High Speed Internal Clock Occupation Status (CK_HSI)
xx1: HSI used by System Clock (CK_SYS) (SW=0x03)
x1x: HSI used by PLL
1xx: HSI used by Clock Monitor
[17:16]
HSEST
High Speed External Clock Occupation Status (CK_HSE)
x1: HSE used by System Clock (CK_SYS) (SW=0x02)
1x: HSE used by PLL
[11:8]
PLLST
PLL Clock Occupation Status
xxx1: PLL used by System Clock (CK_SYS)
xx1x: PLL used by USART
x1xx: PLL used by USB
1xxx: PLL used by CSIF
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August 13, 2012
Clock Control Unit (CKCU)
CKSWST
Type/Reset
28
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Low Power Control Register – LPCR
This register specifies low power control.
Offset:
0x300
Reset value:
0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
Reserved
Type/Reset
3
BKISO
R/W
0
Bits
Field
Descriptions
[0]
BKISO
Backup Domain Isolation Control
0: Backup domain isolated from other power domain
1: Backup domain accessible by other power domain
This bit is set and reset by software. Refer to the Power Control Unit chapter for
more information.
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August 13, 2012
Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
MCU Debug Control Register – MCUDBGCR
This register specifies the MCU debug control bits.
Offset:
0x304
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved
DBBFTM1 DBBFTM0
Type/Reset
R/W
15
14
DBSCI
Type/Reset
R/W
0
7
13
DBDSLP2
R/W
0
R/W
0
R/W
11
10
9
R/W
0
8
DBI2C1
DBI2C0
DBSPI1
DBSPI0
DBUR1
DBUR0
R/W
R/W
R/W
R/W
R/W
R/W
6
DBGPTM1 DBGPTM0
Type/Reset
12
0
0
0
5
4
Reserved
DBMCTM
0
R/W
0
3
0
2
DBWDT
R/W
0
0
1
DBPD
R/W
0
0
0
DBDSLP1
R/W
0
0
DBSLP
R/W
0
Bits
Field
Descriptions
[17]
DBBFTM1
BFTM1 Debug Mode Enable
0: BFTM1 counter keeps counting even if the core is halted
1: BFTM1 counter is stopped when the core is halted
Set and reset by software. This bit is used to control whether the BFTM1 counter is
stopped or not when the core is halted.
[16]
DBBFTM0
BFTM0 Debug Mode Enable
0: BFTM0 counter keeps counting even if the core is halted
1: BFTM0 counter is stopped when the core is halted
Set and reset by software. This bit is used to control whether the BFTM0 counter is
stopped or not when the core is halted.
[15]
DBSCI
SCI Debug Mode Enable
0: Same behavior as normal mode
1: SCI timeout is stopped
Set and reset by software. This bit is used to control whether the SCI timeout mode
is stopped or not when the core is halted.
[14]
DBDSLP2
Debug Deep-Sleep2
0: LDO=Off, DMOS=On, FCLK=Off and HCLK=Off in Deep-Sleep2
1: LDO=On, FCLK=On and HCLK=On in Deep-Sleep2
This bit is set and reset by software.
[13]
DBI2C1
I2C1 Debug Mode Enable
0: Same behavior as normal mode
1: I2C1 timeout is stopped
Set and reset by software. This bit is used to control whether the I2C1 timeout mode
is stopped or not when the core is halted.
[12]
DBI2C0
I2C0 Debug Mode Enable
0: Same behavior as normal mode
1: I2C0 timeout is stopped
Set and reset by software. This bit is used to control whether the I2C0 timeout mode
is stopped or not when the core is halted.
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August 13, 2012
Clock Control Unit (CKCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[11]
DBSPI1
SPI1 Debug Mode Enable
0: Same behavior as normal mode
1: SPI1 FIFO timeout is stopped
Set and reset by software. This bit is used to control whether the SPI1 timeout mode
is stopped or not when the core is halted.
[10]
DBSPI0
SPI0 Debug Mode Enable
0: Same behavior as normal mode
1: SPI0 FIFO timeout is stopped
Set and reset by software. This bit is used to control whether the SPI0 timeout mode
is stopped or not when the core is halted.
[9]
DBUR1
USART1 Debug Mode Enable
0: Same behavior as normal mode
1: USART1 FIFO timeout is stopped
Set and reset by software. This bit is used to control whether the USART1 timeout
mode is stopped or not when the core is halted.
[8]
DBUR0
USART0 Debug Mode Enable
0: Same behavior as normal mode
1: USART0 FIFO timeout is stopped
Set and reset by software. This bit is used to control whether the USART0 timeout
mode is stopped or not when the core is halted.
[7]
DBGPTM1
GPTM1 Debug Mode Enable
0: GPTM1 counter keeps counting even if the core is halted
1: GPTM1 counter is stopped when the core is halted
Set and reset by software. This bit is used to control whether the GPTM1 counter is
stopped or not when the core is halted.
[6]
DBGPTM0
GPTM0 Debug Mode Enable
0: GPTM0 counter keeps counting even if the core is halted
1: GPTM0 counter is stopped when the core is halted
Set and reset by software. This bit is used to control whether the GPTM0 counter is
stopped or not when the core is halted.
[4]
DBMCTM
MCTM Debug Mode Enable
0: MCTM counter keeps counting even if the core is halted
1: MCTM counter is stopped when the core is halted
Set and reset by software. This bit is used to control whether the MCTM counter is
stopped or not when the core is halted.
[3]
DBWDT
Watchdog Timer Debug Mode Enable
0: Watchdog Timer counter keeps counting even if the core is halted
1: Watchdog Timer counter is stopped when the core is halted
Set and reset by software. This bit is used to control whether the Watchdog Timer
counter is stopped or not when the core is halted.
[2]
DBPD
Debug Power-Down Mode
0: LDO=Off, FCLK=Off, and HCLK=Off in Power-Down mode
1: LDO=On, FCLK=On, and HCLK=On in Power-Down mode
This bit is set and reset by software.
[1]
DBDSLP1
Debug Deep-Sleep1
0: LDO=Low power mode, FCLK=Off, and HCLK=Off in Deep-Sleep1
1: LDO=On, FCLK=On, and HCLK=On in Deep-Sleep1
This bit is set and reset by software.
[0]
DBSLP
Debug Sleep Mode
0: LDO=On, FCLK=On, and HCLK=Off in Sleep mode
1: LDO=On, FCLK=On, and HCLK=On in Sleep mode
This bit is set and reset by software.
Rev. 1.00
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August 13, 2012
Clock Control Unit (CKCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
7
Reset Control Unit (RSTCU)
Introduction
CortexTM-M3
RSTCU
1.8V Core
Power
RESET
VDD18
POR18
Filter
BODRST
VDD33
Brown Out
Detector
RESET
PORRESETn
NVICDBGRESETn
CM3 Core
NVICRESETn
CORERESTn
Filter
WDT_RSTn
SYSRESETREQ
----
VDD33
NVIC
SYSRESETREQ
VECTRESET
nRST
VBAT
SYSRESETREQ
Filter
Backup
Domain
RESET
PORB
Filter
Delay
SYSRESETn
HRESETn
System Components
(BusMatrix, MPU)
RTC/PWRCU reset
BAKRST
WDTRST
Reset
generator
USARTRST
Reset
generator
WDT reset
PORRESETn
System Debug
Components
(FPB, DWT, ITM)
USART reset
Figure 16. RSTCU Block Diagram
Functional Descriptons
Power On Rest
The Power on reset, POR, is generated by either an external reset or by the internal reset generator.
Both types have an internal filter to prevent glitches from causing erroneous reset operations. By
referring to Figure 16, the POR18 active low signal will be de-asserted when the internal LDO
voltage regulator is ready to provide 1.8V power. In addition to the POR18 signal, the Power
Control Unit, PWRCU, will assert the BODF signal as a Power Down Reset, PDR, when the
BODEN bit in the LVDCSR register is set and the brown-out event occurs. For more details about
the PWRCU function, refer to the PWRCU chapter.
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August 13, 2012
Reset Control Unit (RSTCU)
The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and
APB unit reset. The power on reset, known as a cold reset, resets the full system during a power
up. A system reset resets the processor core and peripheral IP components with the exception of
the debug port controller. The resets can be triggered by an external signal, internal events and the
reset generators. More information about these resets will be described in the following section.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
VDD33
VDD18
t1
Reset Control Unit (RSTCU)
POR18
PORESTn
t2
SYSRESTn
t1 = 25us *Typical.
t2 = 13us
t3 = 150us
t3
* This timing is dependent on the internal LDO regulator output capacitor value.
Figure 17. Power On Reset Sequence
System Reset
A System reset is generated by a power on reset (PORRESETn), a Watchdog Timer reset
(WDT_RSTn), an NVIC reset (NVICRESETn) or a software reset (VECTREST) event. For more
information about the Watchdog Timer and NVIC reset events, refer to the related chapter in the
CortexTM-M3 reference manual.
AHB and APB Unit Reset
The AHB and APB unit reset can be divided into hardware and software resets. A hardware
reset can be generated by either a power on reset or a system reset for all AHB and APB units.
Each functional IP connected to the AHB and APB buses can be reset individually through the
associated software reset bits in the RSTCU. For example, the application software can generate a
USART0 reset via the UR0RST bit in the APBPRSTR0 register to reset the USART0 circuts.
Register Map
The following table shows the RSTCU registers and reset values.
Table 19. RSTCU Register Map
Register
Offset
Description
Reset Value
RSTCU Base Address=0x4008_8000
Rev. 1.00
GRSR
0x100
Global Reset Status Register
0x0000_0008
AHBPRSTR
0x104
AHB Peripheral Reset Register
0x0000_0000
APBPRSTR0
0x108
APB Peripheral Reset Register 0
0x0000_0000
APBPRSTR1
0x10C
APB Peripheral Reset Register 1
0x0000_0000
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August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
Global Reset Status Register – GRSR
This register specifies a variety of reset status conditions.
Offset:
0x100
Reset value:
0x0000_0008
30
29
28
27
26
25
24
18
17
16
10
9
8
Reset Control Unit (RSTCU)
31
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
Reserved
4
3
2
1
0
PORSTF
WDTRSTF
EXTRSTF
SYSRSTF
Type/Reset
WC
1
WC
0
WC
0
WC
0
Bits
Field
Descriptions
[3]
PORSTF
Core 1.8V Power On Reset Flag
0: No POR occured
1: POR occured
This bit is set by hardware when a power on reset occurs and reset by writing 1 into it.
[2]
WDTRSTF
Watchdog Timer Reset Flag
0: No Watchdog Timer reset occured
1: Watchdog Timer occured
This bit is set by hardware when a watchdog timer reset occurs and reset by writing 1
into it or by hardware when a power on reset occurs.
[1]
EXTRSTF
External Pin Reset Flag
0: No pin reset occured
1: Pin reset occured
This bit is set by hardware when an external pin reset occurs and reset by writing 1 into it
or by hardware when a power on reset occurs.
[0]
SYSRSTF
System Reset Flag
0: No NVIC asserting system reset occured
1: NVIC asserting system reset occured
This bit is set by hardware when a system reset occurs and reset by writing 1 into it or by
hardware when a power on reset occurs.
Rev. 1.00
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August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
AHB Peripheral Reset Register – AHBPRSTR
This register specifies the AHB peripheral software reset control bits.
Offset:
0x104
Reset value:
0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
Reserved
Type/Reset
5
4
3
CSIFRST
RW
Reserved
PDMARST
0
RW
Bits
Field
Descriptions
[4]
CSIFRST
CMOS Sensor Interface (CSIF) Reset Control
0: No reset
1: Reset CMOS Sensor Interface (CSIF)
This bit is set by software and cleared to 0 by hardware automatically.
[0]
PDMARST
Peripheral DMA (PDMA) Reset Control
0: No reset
1: Reset Peripheral DMA (PDMA)
This bit is set by software and cleared to 0 by hardware automatically.
Rev. 1.00
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0
August 13, 2012
Reset Control Unit (RSTCU)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
APB Peripheral Reset Register 0 – APBPRSTR0
This register specifies several APB peripheral software reset control bits.
Offset:
0x108
Reset value:
0x0000_0000
31
30
29
28
27
26
25
24
SCIRST
RW
23
22
21
20
Reserved
Type/Reset
15
14
EXTIRST
Type/Reset
RW
0
7
Type/Reset
13
19
17
PDRST
PCRST
PBRST
PARST
RW
RW
RW
RW
RW
0
12
0
11
0
10
Reserved
9
RW
5
Reserved
SPI1RST
RW
4
0
3
SPI0RST
RW
0
0
0
2
1
Reserved
I2C1RST
RW
0
Field
Descriptions
[24]
SCIRST
Smart Card Interface Reset Control
0: No reset
1: Reset Smart Card Interface
This bit is set by software and cleared to 0 by hardware automatically.
[20]
PERST
GPIO Port E Reset Control
0: No reset
1: Reset Port E
This bit is set by software and cleared to 0 by hardware automatically.
[19]
PDRST
GPIO Port D Reset Control
0: No reset
1: Reset Port D
This bit is set by software and cleared to 0 by hardware automatically.
[18]
PCRST
GPIO Port C Reset Control
0: No reset
1: Reset Port C
Set and reset by software. It is cleared to 0 by hardware automatically.
[17]
PBRST
GPIO Port B Reset Control
0: No reset
1: Reset Port B
This bit is set by software and cleared to 0 by hardware automatically.
[16]
PARST
GPIO Port A Reset Control
0: No reset
1: Reset Port A
This bit is set by software and cleared to 0 by hardware automatically.
[15]
EXTIRST
External Interrupt Controller Reset Control
0: No reset
1: Reset EXTI
This bit is set by software and cleared to 0 by hardware automatically.
108 of 628
UR0RST
RW
0
0
Bits
Rev. 1.00
0
8
UR1RST
0
6
16
PERST
AFIORST
RW
18
0
I2C0RST
RW
0
August 13, 2012
Reset Control Unit (RSTCU)
Reserved
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[14]
AFIORST
Alternate Function I/O Reset Control
0: No reset
1: Reset Alternate Function I/O
This bit is set by software and cleared to 0 by hardware automatically.
[9]
UR1RST
USART1 Reset Control
0: No reset
1: Reset USART1
This bit is set by software and cleared to 0 by hardware automatically.
[8]
UR0RST
USART0 Reset Control
0: No reset
1: Reset USART0
This bit is set by software and cleared to 0 by hardware automatically.
[5]
SPI1RST
SPI1 Reset Control
0: No reset
1: Reset SPI1
This bit is set by software and cleared to 0 by hardware automatically.
[4]
SPI0RST
SPI0 Reset Control
0: No reset
1: Reset SPI0
This bit is set by software and cleared to 0 by hardware automatically.
[1]
I2C1RST
I2C1 Reset Control
0: No reset
1: Reset I2C1
This bit is set by software and cleared to 0 by hardware automatically.
[0]
I2C0RST
I2C0 Reset Control
0: No reset
1: Reset I2C0
This bit is set by software and cleared to 0 by hardware automatically.
Rev. 1.00
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August 13, 2012
Reset Control Unit (RSTCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
APB Peripheral Reset Register 1 – APBPRSTR1
This register specifies several APB peripheral software reset control bits.
Offset:
0x10C
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
ADCRST
RW
23
22
21
20
19
OPA1RST OPA0RST
Type/Reset
RW
0
RW
14
Reserved
USBRST
RW
7
Rev. 1.00
12
11
10
Reserved
4
RW
0
110 of 628
2
Reserved
1
BFTM0RST
RW
0
8
GPTM1RST
3
WDTRST
0
9
RW
5
16
BFTM1RST
0
6
17
RW
13
Reserved
Type/Reset
Reserved
0
15
Type/Reset
18
0
0
GPTM0RST
RW
0
0
MCTMRST
RW
0
August 13, 2012
Reset Control Unit (RSTCU)
Reserved
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[24]
ADCRST
A/D Converter Reset Control
0: No reset
1: Reset A/D Converter
This bit is set by software and cleared to 0 by hardware automatically.
[23]
OPA1RST
Comparator and OPA1 Controller Reset Control
0: No reset
1: Reset CMP/OPA1
This bit is set by software and cleared to 0 by hardware automatically.
[22]
OPA0RST
Comparator and OPA0 Controller Reset Control
0: No reset
1: Reset CMP/OPA0
This bit is set by software and cleared to 0 by hardware automatically.
[17]
BFTM1RST
BFTM1 Reset Control
0: No reset
1: Reset BFTM1
This bit is set by software and cleared to 0 by hardware automatically.
[16]
BFTM0RST
BFTM0 Reset Control
0: No reset
1: Reset BFTM0
This bit is set by software and cleared to 0 by hardware automatically.
[14]
USBRST
USB Reset Control
0: No reset
1: Reset USB
This bit is set by software and cleared to 0 by hardware automatically.
[9]
GPTM1RST
GPTM1 Reset Control
0: No reset
1: Reset GPTM1
This bit is set by software and cleared to 0 by hardware automatically.
[8]
GPTM0RST
GPTM0 Reset Control
0: No reset
1: Reset GPTM0
This bit is set by software and cleared to 0 by hardware automatically.
[4]
WDTRST
Watchdog Timer Reset Control
0: No reset
1: Reset Watchdog Timer
This bit is set by software and cleared to 0 by hardware automatically.
[0]
MCTMRST
MCTM Reset Control
0: No reset
1: Reset MCTM
This bit is set by software and cleared to 0 by hardware automatically.
Rev. 1.00
111 of 628
August 13, 2012
Reset Control Unit (RSTCU)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
8
General Purpose I/O (GPIO)
Introduction
The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility
on the package pins. The GPIO pins can be used as alternative functional pins by configuring the
corresponding registers regardless of the AF input or output pins.
The external interrupts on the GPIO pins of the device have related control and configuration
registers in the External Interrupt Control Unit (EXTI).
PxDOn
To AFIO MUX
PxRSTn
PxSETn
PxDVn
APB Interface
CIOPAD
PxODn
To IOPAD DS
PxPLn
To IOPAD PDN
PxPHn
To IOPAD PUN
PxDIN
IENAFIO
To IOPAD IEN
PxINENn
PxDIRn
To IOPAD OEN
OENAFIO
Figure 18. GPIO Block Diagram
Rev. 1.00
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August 13, 2012
General Purpose I/O (GPIO)
There are up to 80 General Purpose I/O port, GPIO, named PA0~PA15, PB0~PB15, PC0~PC15,
PD0~PD15 and PE0~PE15 for the device to implement the logic input/output functions. Each of
the GPIO ports has related control and configuration registers to satisfy the requirement of specific
applications.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Features
Input/output direction control
Schmitt Trigger Input function enable control
Input weak pull-up/pull-down control
Output push-pull/open drain enable control
Output set/reset control
Output drive current selection
External interrupt with programmable trigger edge – using EXTI configuration registers
Analog input/output configurations – using AFIO configuration registers
Alternate function input/output configurations – using AFIO configuration registers
Port configuration lock
Functional Descriptions
Default GPIO Pin Configuration
During or just after the reset period, the alternative functions are all inactive and the GPIO ports
are configured into the input disable floating mode, i.e. input disabled without pull-up/pull-down
resistors. Only the boot and Serial-Wired Debug pins which are pin-shared with the I/O pins PC8,
PC9, PE11, PE12, PE13, PE14 and PE15 are active after a device reset.
▀
▀
▀
▀
▀
▀
▀
PC8/BOOT0: Input enable with internal pull-up
PC9/BOOT1: Input enable with internal pull-up
PE11/JTDO/TRACESWO: Input enable with internal pull-down
PE12/JTCK/SWCLK: Input or output enable with internal pull-up
PE13/JTMS/SWDIO: Input enable with internal pull-up
PE14/JTDI: Input enable with internal pull-up
PE15/JTRS: Input enable with internal pull-up
General Purpose I/O – GPIO
The GPIO pins can be configured as inputs or outputs via the data direction control registers
PxDIRCR (where x=A~E). When the GPIO pins are configured as input pins, the data on the
external pins can be read if the enable bits in the input enable function register PxINER are set. The
GPIO pull-up/pull-down registers PxPUR/PxPDR can be configured to fit specific applications.
When the pull-up and pull-down functions are both enabled, the pull-up function has the higher
priority while the pull-down function will be blocked until the pull-up function is released.
The GPIO pins can be configured as output pins where the output data is latched into the data
register PxDOUTR. The output type can be setup to be either push-pull or open-drain by the
open drain selection register PxODR. Only one or several specific bits of the output data will be
set or reset by configuring the port output set and reset control register PxSRR or the port output
reset control register PxRR without affecting the unselected bits. As the port output set and reset
functions are both enabled, the port output set function has the higher priority and the port output
reset function will be blocked. The output driving current of the GPIO pins can be selected by
configuring the drive current selection register PxDRVR.
Rev. 1.00
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August 13, 2012
General Purpose I/O (GPIO)
▀
▀
▀
▀
▀
▀
▀
▀
▀
▀
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
PxCFGn
PUN
Input
DMUX
PDN
IEN
General Purpose I/O (GPIO)
Output
MUX
IP
AFIO
Control
OENIP
PxSETn
ADENAFIO
PxRSTn
OENAFIO
PxDOn
IENAFIO
AFIO
IOPAD
OEN
DS
ADC
ADEN
PxDIn
PxDVn
PxINENn
PxODn
PxDIRn
PxPLn
PxPHn
GPIO
PxDIn/PxDOn(x=A~E): Data Input/Data Output
PxRSTn/PxSETn(x=A~E): Reset/Set
PxDIRn(x=A~E): Direction
PxINENn(x=A~E): Input Enable
PxDVn(x=A~E): Output Drive
PXODn(x=A~E): Open Drain
PxPLn/PxPHn(x=A~E): Pull Low/High
PxCFGn(x=A~E): AFIO Configuration
Figure 19. AFIO/GPIO Control Signal
Rev. 1.00
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August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table 20. AFIO, GPIO and I/O Pad Control Signal True Table
AFIO
Type
GPIO
PAD
ADENAFIO OENAFIO IENAFIO PxDIRn PxINENn ADEN OEN
GPIO Input
IEN
1
1
0
1
1
1
0
GPIO Output
1
1
1
1
0 (1 if need)
1
0
1 (0)
AFIO Input
1
1
0
0
X
1
1
0
AFIO Output
1
0
1
X
0 (1 if need)
1
0
1 (0)
ADC Input
0
1
1
0
0 (1 if need)
0
1
1 (0)
OSC Output
0
1
1
0
0 (1 if need)
0
1
1 (0)
(Note)
Note: The signals, IEN and OEN, for I/O pads are derived from the GPIO register bits PxINENn and
PxDIRn respectively when the associated pin is configured in the GPIO input/output mode.
GPIO Locking Mechanism
The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR
(x=A~E) registers are used to lock the port x and lock control options. The value 0x5FA0 is written
into the PxLKEY field in the PxLOCKR registers to freeze the PxDIRCR, PxINER, PxPUR,
PxPDR, PxODR, PxDRVR control and AFIO mode configuration (GPxCFGR, where x=A~E). If
the value in the PxLOCKR is 0x5FA0_0001, it means that the Port x Lock function is enabled and
the Port x pin 0 is frozen.
Register Map
The following table shows the GPIO registers and reset values of the Port A~E.
Table 21. Register map of GPIO
Register
Offset
Description
Reset Value
GPIO A Base Address=0x4001_A000
PADIRCR
0x000
Port A Data Direction Control Register
0x0000_0000
PAINER
0x004
Port A Input Function Enable Control Register
0x0000_0000
PAPUR
0x008
Port A Pull-Up Selection Register
0x0000_0000
PAPDR
0x00C
Port A Pull-Down Selection Register
0x0000_0000
PAODR
0x010
Port A Open Drain Selection Register
0x0000_0000
PADRVR
0x014
Port A Drive Current Selection Register
0x0000_0000
PALOCKR
0x018
Port A Lock Register
0x0000_0000
PADINR
0x01C
Port A Data Input Register
0x0000_0000
PADOUTR
0x020
Port A Data Output Register
0x0000_0000
PASRR
0x024
Port A Output Set and Reset Control Register
0x0000_0000
PARR
0x028
Port A Output Reset Control Register
0x0000_0000
GPIO B Base Address=0x4001_B000
Rev. 1.00
PBDIRCR
0x000
Port B Data Direction Control Register
0x0000_0000
PBINER
0x004
Port B Input Function Enable Control Register
0x0000_0000
PBPUR
0x008
Port B Pull-Up Selection Register
0x0000_0000
PBPDR
0x00C
Port B Pull-Down Selection Register
0x0000_0000
PBODR
0x010
Port B Open Drain Selection Register
0x0000_0000
PBLOCKR
0x018
Port B Lock Register
0x0000_0000
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August 13, 2012
General Purpose I/O (GPIO)
1
(Note)
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register
Offset
Description
Reset Value
PBDINR
0x01C
Port B Data Input Register
0x0000_0000
PBDOUTR
0x020
Port B Data Output Register
0x0000_0000
PBSRR
0x024
Port B Output Set and Reset Control Register
0x0000_0000
PBRR
0x028
Port B Output Reset Control Register
0x0000_0000
GPIO C Base Address=0x4001_C000
0x000
Port C Data Direction Control Register
0x0000_0000
PCINER
0x004
Port C Input Function Enable Control Register
0x0000_0300
PCPUR
0x008
Port C Pull-Up Selection Register
0x0000_0300
PCPDR
0x00C
Port C Pull-Down Selection Register
0x0000_0000
PCODR
0x010
Port C Open Drain Selection Register
0x0000_0000
PCLOCKR
0x018
Port C Lock Register
0x0000_0000
PCDINR
0x01C
Port C Data Input Register
0x0000_0000
PCDOUTR
0x020
Port C Data Output Register
0x0000_0000
PCSRR
0x024
Port C Output Set and Reset Control Register
0x0000_0000
PCRR
0x028
Port C Output Reset Control Register
0x0000_0000
GPIO D Base Address=0x4001_D000
PDDIRCR
0x000
Port D Data Direction Control Register
0x0000_0000
PDINER
0x004
Port D Input Function Enable Control Register
0x0000_0000
PDPUR
0x008
Port D Pull-Up Selection Register
0x0000_0000
PDPDR
0x00C
Port D Pull-Down Selection Register
0x0000_0000
PDODR
0x010
Port D Open Drain Selection Register
0x0000_0000
PDLOCKR
0x018
Port D Lock Register
0x0000_0000
PDDINR
0x01C
Port D Data Input Register
0x0000_0000
PDDOUTR
0x020
Port D Data Output Register
0x0000_0000
PDSRR
0x024
Port D Output Set and Reset Control Register
0x0000_0000
PDRR
0x028
Port D Output Reset Control Register
0x0000_0000
GPIO E Base Address=0x4001_E000
Rev. 1.00
PEDIRCR
0x000
Port E Data Direction Control Register
0x0000_0000
PEINER
0x004
Port E Input Function Enable Control Register
0x0000_D000
PEPUR
0x008
Port E Pull-Up Selection Register
0x0000_E000
PEPDR
0x00C
Port E Pull-Down Selection Register
0x0000_1000
PEODR
0x010
Port E Open Drain Selection Register
0x0000_0000
PEDRVR
0x014
Port E Drive Current Selection Register
0x0000_0000
PELOCKR
0x018
Port E Lock Register
0x0000_0000
PEDINR
0x01C
Port E Data Input Register
0x0000_0000
PEDOUTR
0x020
Port E Data Output Register
0x0000_0000
PESRR
0x024
Port E Output Set and Reset Control Register
0x0000_0000
PERR
0x028
Port E Output Reset Control Register
0x0000_0000
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August 13, 2012
General Purpose I/O (GPIO)
PCDIRCR
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
Port A Data Direction Control Register – PADIRCR
This register is used to control the direction of the GPIO Port A pin as input or output.
Offset:
0x000
Reset value:
0x0000_0000
30
29
28
27
26
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PADIR
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PADIR
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PADIRn
GPIO Port A pin n Direction Control Bits (n=0~15)
0: Pin n is input mode
1: Pin n is output mode
Rev. 1.00
117 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Input Function Enable Control Register – PAINER
This register is used to enable or disable the GPIO Port A input function.
Offset:
0x004
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PAINEN
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PAINEN
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PAINENn
GPIO Port A pin n Input Enable Control Bits (n=0~15)
0: Pin n input function is disabled
1: Pin n input function is enabled
When the pin n input function is disabled, the input Schmitt trigger will be turned off
and the Schmitt trigger output will remain at a zero state.
Rev. 1.00
118 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Pull-Up Selection Register – PAPUR
This register is used to enable or disable the GPIO Port A pull-up function.
Offset:
0x008
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PAPU
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PAPU
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PAPUn
GPIO Port A pin n Pull-Up Selection Control Bits (n=0~15)
0: Pin n pull-up function is disabled
1: Pin n pull-up function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
119 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Pull-Down Selection Register – PAPDR
This register is used to enable or disable the GPIO Port A pull-down function.
Offset:
0x00C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PAPD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PAPD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PAPDn
GPIO Port A pin n Pull-Down Selection Control Bits (n=0~15)
0: Pin n pull-down function is disabled
1: Pin n pull-down function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
120 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Open Drain Selection Register – PAODR
This register is used to enable or disable the GPIO Port A open drain function.
Offset:
0x010
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PAOD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PAOD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[15:0]
PAODn
GPIO Port A pin n Open Drain Selection Control Bits (n=0~15)
0: Pin n Open Drain output is disabled (The output type is CMOS output)
1: Pin n Open Drain output is enabled (The output type is open-drain output)
Rev. 1.00
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0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Output Current Drive Selection Register – PADRVR
This register specifies the GPIO Port A output driving current.
Offset:
0x014
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
General Purpose I/O (GPIO)
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
PADV
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[7:0]
PADVn
GPIO Port A pin n Output Current Drive Selection Control Bits (n=0~7)
0: 4mA source/sink current
1: 8mA source/sink current
Rev. 1.00
122 of 628
RW
0
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Lock Register – PALOCKR
This register specifies the GPIO Port A lock configuration.
Offset:
0x018
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
RW
0
23
RW
0
RW
22
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
PALKEY
Type/Reset
RW
0
15
RW
0
RW
14
0
13
RW
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
PALOCK
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PALOCK
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:16]
PALKEY
GPIO Port A Lock Key
0x5FA0: Port A Lock function is enable
Others: Port A Lock function is disable
To lock the Port A function, a value 0x5FA0 should be written into the PALKEY field
in this register. To execute a successful write operation on this lock register, the
value written into the PALKEY field must be 0x5FA0. If the value written into this
field is not equal to 0x5FA0, any write operations on the PALOCKR register will be
aborted. The result of a read operation on the PALKEY field returns the GPIO Port
A Lock Status which indicates whether the GPIO Port A is locked or not. If the read
value of the PALKEY field is 0, this indicates that the GPIO Port A Lock function is
disabled. Otherwise, it indicates that the GPIO Port A Lock function is enabled as the
read value is equal to 1.
[15:0]
PALOCKn
GPIO Port A Pin n Lock Control Bits (n=0~15)
0: Port A Pin n is not locked
1: Port A Pin n is locked
The PALOCKn bits are used to lock the configurations of corresponding GPIO Pins
when the correct Lock Key is applied to the PALKEY field. The locked configurations
including PADIRn, PAINENn, PAPUn, PAPDn, PAODn and PADVn setting in the
related GPIO registers. Additionally, the GPACFGR field which is used to configure
the alternative function of the associated GPIO pin will also be locked. Note that the
PALOCKR can only be written once which means that PALKEY and PALOCKn (lock
control bit) should be written together and can not be changed until a system reset or
GPIO Port A reset occurs.
Rev. 1.00
123 of 628
August 13, 2012
General Purpose I/O (GPIO)
PALKEY
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Data Input Register – PADINR
This register specifies the GPIO Port A input data.
Offset:
0x01C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PADIN
Type/Reset
RO
0
7
RO
0
RO
6
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
PADIN
Type/Reset
RO
0
RO
0
RO
0
RO
0
RO
Bits
Field
Descriptions
[15:0]
PADINn
GPIO Port A pin n Data Input Bits (n=0~15)
0: The input data of pin is 0
1: The input data of pin is 1
Rev. 1.00
124 of 628
0
RO
0
RO
0
RO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Output Data Register – PADOUTR
This register specifies the GPIO Port A output data.
Offset:
0x020
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PADOUT
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PADOUT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PADOUTn
GPIO Port A pin n Data Output Bits (n=0~15)
0: Data to be output on pin n is 0
1: Data to be output on pin n is 1
Rev. 1.00
125 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Output Set/Reset Control Register – PASRR
This register is used to set or reset the corresponding bit of the GPIO Port A output data.
Offset:
0x024
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
WO
0
23
WO
0
WO
22
0
21
WO
0
20
WO
0
19
WO
0
18
WO
0
17
WO
0
16
PARST
Type/Reset
WO
0
15
WO
0
WO
14
0
13
WO
0
12
WO
0
11
WO
0
10
WO
0
9
WO
0
8
PASET
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PASET
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[31:16]
PARSTn
GPIO Port A pin n Output Reset Control Bits (n=0~15)
0: No effect on the PADOUTn bit
1: Reset the PADOUTn bit
[15:0]
PASETn
GPIO Port A pin n Output Set Control Bits (n=0~15)
0: No effect on the PADOUTn bit
1: Set the PADOUTn bit
Note that the function enabled by the PASETn bit has the higher priority if both the
PASETn and PARSTn bits are set at the same time.
Rev. 1.00
126 of 628
August 13, 2012
General Purpose I/O (GPIO)
PARST
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port A Output Reset Register – PARR
This register is used to reset the corresponding bit of the GPIO Port A output data.
Offset:
0x028
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PARST
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PARST
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[15:0]
PARSTn
GPIO Port A pin n Output Reset Bits (n=0~15)
0: No effect on the PADOUTn bit
1: Reset the PADOUTn bit
Rev. 1.00
127 of 628
WO
0
WO
0
WO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Data Direction Control Register – PBDIRCR
This register is used to control the direction of GPIO Port B pin as input or output.
Offset:
0x000
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBDIR
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PBDIR
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PBDIRn
GPIO Port B pin n Direction Control Bits (n=0~15)
0: Pin n is input mode
1: Pin n is output mode
Rev. 1.00
128 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Input Function Enable Control Register – PBINER
This register is used to enable or disable the GPIO Port B input function.
Offset:
0x004
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBINEN
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PBINEN
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PBINENn
GPIO Port B pin n Input Enable Control Bits (n=0~15)
0: Pin n input function is disabled
1: Pin n input function is enabled
When the pin n input function is disabled, the input Schmitt trigger will be turned off
and the Schmitt trigger output will remain at a zero state.
Rev. 1.00
129 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Pull-Up Selection Register – PBPUR
This register is used to enable or disable the GPIO Port B pull-up function.
Offset:
0x008
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBPU
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PBPU
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PBPUn
GPIO Port B pin n Pull-Up Selection Control Bits (n=0~15)
0: Pin n pull-up function is disabled
1: Pin n pull-up function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
130 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Pull-Down Selection Register – PBPDR
This register is used to enable or disable the GPIO Port B pull-down function.
Offset:
0x00C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBPD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PBPD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PBPDn
GPIO Port B pin n Pull-Down Selection Control Bits (n=0~15)
0: Pin n pull-down function is disabled
1: Pin n pull-down function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
131 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Open Drain Selection Register – PBODR
This register is used to enable or disable the GPIO Port B open drain function.
Offset:
0x010
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBOD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PBOD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[15:0]
PBODn
GPIO Port B pin n Open Drain Selection Control Bits (n=0~15)
0: Pin n Open Drain output is disabled (The output type is CMOS output)
1: Pin n Open Drain output is enabled (The output type is open-drain output)
Rev. 1.00
132 of 628
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Lock Register – PBLOCKR
This register specifies the GPIO Port B lock configuration.
Offset:
0x018
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
RW
0
23
RW
0
RW
22
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
PBLKEY
Type/Reset
RW
0
15
RW
0
RW
14
0
13
RW
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
PBLOCK
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PBLOCK
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:16]
PBLKEY
GPIO Port B lock Key
0x5FA0: Port B lock function is enable
Others: Port B lock function is disable
To lock the Port B function, a value 0x5FA0 should be written into the PBLKEY field
in this register. To execute a successful write operation on this lock register, the
value written into the PBLKEY field must be 0x5FA0. If the value written into this
field is not equal to 0x5FA0, any write operations on the PBLOCKR register will be
aborted. The result of a read operation on the PBLKEY field returns the GPIO Port
B Lock Status which indicates whether the GPIO Port B is locked or not. If the read
value of the PBLKEY field is 0, this indicates that the GPIO Port B Lock function is
disabled. Otherwise, it indicates that the GPIO Port B Lock function is enabled as the
read value is equal to 1.
[15:0]
PBLOCKn
GPIO Port B pin n Lock Control Bits (n=0~15)
0: Port B pin n is not locked
1: Port B pin n is locked
The PBLOCKn bits are used to lock the configurations of corresponding GPIO Pins
when the correct Lock Key is applied to the PBLKEY field. The locked configurations
including PBDIRn, PBINENn, PBPUn, PBPDn and PBODn setting in the related
GPIO registers. Additionally, the GPBCFGR field which is used to configure the
alternative function of the associated GPIO pin will also be locked. Note that the
PBLOCKR can only be written once which means that PBLKEY and PBLOCKn (lock
control bit) should be written together and can not be changed until a system reset or
GPIO Port B reset occurs.
Rev. 1.00
133 of 628
August 13, 2012
General Purpose I/O (GPIO)
PBLKEY
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Data Input Register – PBDINR
This register specifies the GPIO Port B input data.
Offset:
0x01C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBDIN
Type/Reset
RO
0
7
RO
0
RO
6
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
PBDIN
Type/Reset
RO
0
RO
0
RO
0
RO
0
RO
0
Bits
Field
Descriptions
[15:0]
PBDINn
GPIO Port B pin n Data Input Bits (n=0~15)
0: The input data of corresponding pin is 0
1: The input data of corresponding pin is 1
Rev. 1.00
134 of 628
RO
0
RO
0
RO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Output Data Register – PBDOUTR
This register specifies the GPIO Port B output data.
Offset:
0x020
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBDOUT
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PBDOUT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PBDOUTn
GPIO Port B pin n Data Output Bits (n=0~15)
0: Data to be output on pin n is 0
1: Data to be output on pin n is 1
Rev. 1.00
135 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Output Set/Reset Control Register – PBSRR
This register is used to set or reset the corresponding bit of the GPIO Port B output data.
Offset:
0x024
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
WO
0
23
WO
0
WO
22
0
21
WO
0
20
WO
0
19
WO
0
18
WO
0
17
WO
0
16
PBRST
Type/Reset
WO
0
15
WO
0
WO
14
0
13
WO
0
12
WO
0
11
WO
0
10
WO
0
9
WO
0
8
PBSET
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PBSET
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[31:16]
PBRSTn
GPIO Port B pin n Output Reset Control Bits (n=0~15)
0: No effect on the PBDOUTn bit
1: Reset the PBDOUTn bit
[15:0]
PBSETn
GPIO Port B pin n Output Set Control Bits (n=0~15)
0: No effect on the PBDOUTn bit
1: Set the PBDOUTn bit
Note that the function enabled by the PBSETn bit has the higher priority if both the
PBSETn and PBRSTn bits are set at the same time.
Rev. 1.00
136 of 628
August 13, 2012
General Purpose I/O (GPIO)
PBRST
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port B Output Reset Register – PBRR
This register is used to reset the corresponding bit of the GPIO Port B output data.
Offset:
0x028
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PBRST
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PBRST
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[15:0]
PBRSTn
GPIO Port B pin n Output Reset Bits (n=0~15)
0: No effect on the PBDOUTn bit
1: Reset the PBDOUTn bit
Rev. 1.00
137 of 628
WO
0
WO
0
WO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Data Direction Control Register – PCDIRCR
This register is used to control the direction of GPIO Port C pin as input or output.
Offset:
0x000
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCDIR
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PCDIR
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PCDIRn
GPIO Port C pin n Direction Control Bits (n=0~15)
0: Pin n is input mode
1: Pin n is output mode
Rev. 1.00
138 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
Reserved
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Input Function Enable Control Register – PCINER
This register is used to enable or disable the GPIO Port C input function.
Offset:
0x004
Reset value: 0x0000_0300
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCINEN
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
1
1
RW
1
0
PCINEN
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PCINENn
GPIO Port C pin n Input Enable Control Bits (n=0~15)
0: Pin n input function is disabled
1: Pin n input function is enabled
When the pin n input function is disabled, the input Schmitt trigger will be turned off
and the Schmitt trigger output will remain at a zero state.
Rev. 1.00
139 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Pull-Up Selection Register – PCPUR
This register is used to enable or disable the GPIO Port C pull-up function.
Offset:
0x008
Reset value: 0x0000_0300
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCPU
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
1
1
RW
1
0
PCPU
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PCPUn
GPIO Port C pin n Pull-Up Selection Control Bits (n=0~15)
0: Pin n pull-up function is disabled
1: Pin n pull-up function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
140 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Pull-Down Selection Register – PCPDR
This register is used to enable or disable the GPIO Port C pull-down function.
Offset:
0x00C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCPD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PCPD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PCPDn
GPIO Port C pin n Pull-Down Selection Control Bits (n=0~15)
0: Pin n pull-down function is disabled
1: Pin n pull-down function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
141 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Open Drain Selection Register – PCODR
This register is used to enable or disable the GPIO Port C open drain function.
Offset:
0x010
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCOD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PCOD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[15:0]
PCODn
GPIO Port C pin n Open Drain Selection Control Bits (n=0~15)
0: Pin n Open Drain output is disabled (The output type is CMOS output)
1: Pin n Open Drain output is enabled (The output type is open-drain output)
Rev. 1.00
142 of 628
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Lock Register – PCLOCKR
This register specifies the GPIO Port C lock configuration.
Offset:
0x018
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
RW
0
23
RW
0
RW
22
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
PCLKEY
Type/Reset
RW
0
15
RW
0
RW
14
0
13
RW
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
PCLOCK
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PCLOCK
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:16]
PCLKEY
GPIO Port C lock Key
0x5FA0: Port C Lock function is enable
Others: Port C Lock function is disable
To lock the Port C function, a value 0x5FA0 should be written into the PCLKEY field
in this register. To execute a successful write operation on this lock register, the
value written into the PCLKEY field must be 0x5FA0. If the value written into this
field is not equal to 0x5FA0, any write operations on the PCLOCKR register will be
aborted. The result of a read operation on the PCLKEY field returns the GPIO Port
C Lock Status which indicates whether the GPIO Port C is locked or not. If the read
value of the PCLKEY field is 0, this indicates that the GPIO Port C Lock function is
disabled. Otherwise, it indicates that the GPIO Port C Lock function is enabled as
the read value is equal to 1.
[15:0]
PCLOCKn
GPIO Port C pin n Lock Control Bits (n=0~15)
0: Port C pin n is not locked
1: Port C pin n is locked
The PCLOCKn bits are used to lock the configurations of corresponding GPIO Pins
when the correct Lock Key is applied to the PxCKEY field. The locked configurations
including PCDIRn, PCINENn, PCPUn, PCPDn and PCODn setting in the related
GPIO registers. Additionally, the GPCCFGR field which is used to configure the
alternative function of the associated GPIO pin will also be locked. Note that the
PCLOCKR can only be written once which means that PCLKEY and PCLOCKn (lock
control bit) should be written together and can not be changed until a system reset or
GPIO Port C reset occurs.
Rev. 1.00
143 of 628
August 13, 2012
General Purpose I/O (GPIO)
PCLKEY
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Data Input Register – PCDINR
This register specifies the GPIO Port C input data.
Offset:
0x01C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCDIN
Type/Reset
RO
0
7
RO
0
RO
6
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
PCDIN
Type/Reset
RO
0
RO
0
RO
0
RO
0
RO
0
Bits
Field
Descriptions
[15:0]
PCDINn
GPIO Port C pin n Data Input Bits (n=0~15)
0: The input data of corresponding pin is 0
1: The input data of corresponding pin is 1
Rev. 1.00
144 of 628
RO
0
RO
0
RO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Output Data Register – PCDOUTR
This register specifies the GPIO Port C output data.
Offset:
0x020
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCDOUT
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PCDOUT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PCDOUTn
GPIO Port C pin n Data Output Bits (n=0~15)
0: Data to be output on pin n is 0
1: Data to be output on pin n is 1
Rev. 1.00
145 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Output Set/Reset Control Register – PCSRR
This register is used to set or reset the corresponding bit of the GPIO Port C output data.
Offset:
0x024
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
WO
0
23
WO
0
WO
22
0
21
WO
0
20
WO
0
19
WO
0
18
WO
0
17
WO
0
16
PCRST
Type/Reset
WO
0
15
WO
0
WO
14
0
13
WO
0
12
WO
0
11
WO
0
10
WO
0
9
WO
0
8
PCSET
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PCSET
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[31:16]
PCRSTn
GPIO Port C pin n Output Reset Control Bits (n=0~15)
0: No effect on the PCDOUTn bit
1: Reset the PCDOUTn bit
[15:0]
PCSETn
GPIO Port C pin n Output Set Control Bits (n=0~15)
0: No effect on the PCDOUTn bit
1: Set the PCDOUTn bit
Note that the function enabled by the PCSETn bit has the higher priority if both the
PCSETn and PCRSTn bits are set at the same time.
Rev. 1.00
146 of 628
August 13, 2012
General Purpose I/O (GPIO)
PCRST
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port C Output Reset Register – PCRR
This register is used to reset the corresponding bit of the GPIO Port C output data.
Offset:
0x028
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PCRST
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PCRST
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[15:0]
PCRSTn
GPIO Port C pin n Output Reset Bits (n=0~15)
0: No effect on the PCDOUTn bit
1: Reset the PCDOUTn bit
Rev. 1.00
147 of 628
WO
0
WO
0
WO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Data Direction Control Register – PDDIRCR
This register is used to control the direction of GPIO Port D pin as input or output.
Offset:
0x000
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDDIR
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PDDIR
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PDDIRn
GPIO Port D pin n Direction Control Bits (n=0~15)
0: Pin n is input mode
1: Pin n is output mode
Rev. 1.00
148 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Input Function Enable Control Register – PDINER
This register is used to enable or disable the GPIO Port D input function.
Offset:
0x004
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDINEN
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PDINEN
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PDINENn
GPIO Port D pin n Input Enable Control Bits (n=0~15)
0: Pin n input function is disabled
1: Pin n input function is enabled
When the pin n input function is disabled, the input Schmitt trigger will be turned off
and the Schmitt trigger output will remain at a zero state.
Rev. 1.00
149 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Pull-Up Selection Register – PDPUR
This register is used to enable or disable the GPIO Port D pull-up function.
Offset:
0x008
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDPU
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PDPU
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PDPUn
GPIO Port D pin n Pull-Up Selection Control Bits (n=0~15)
0: Pin n pull-up function is disabled
1: Pin n pull-up function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
150 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Pull-Down Selection Register – PDPDR
This register is used to enable or disable the GPIO Port D pull-down function.
Offset:
0x00C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDPD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PDPD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PDPDn
GPIO Port D pin n Pull-Down Selection Control Bits (n=0~15)
0: Pin n pull-down function is disabled
1: Pin n pull-down function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
151 of 628
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Open Drain Selection Register – PDODR
This register is used to enable or disable the GPIO Port D open drain function.
Offset:
0x010
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDOD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PDOD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[15:0]
PDODn
GPIO Port D pin n Open Drain Selection Control Bits (n=0~15)
0: Pin n Open Drain output is disabled (The output type is CMOS output)
1: Pin n Open Drain output is enabled (The output type is open-drain output)
Rev. 1.00
152 of 628
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Lock Register – PDLOCKR
This register specifies the GPIO Port D lock configuration.
Offset:
0x018
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
RW
0
23
RW
0
RW
22
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
PDLKEY
Type/Reset
RW
0
15
RW
0
RW
14
0
13
RW 0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
PDLOCK
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PDLOCK
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:16]
PDLKEY
GPIO Port D Lock Key
0x5FA0: Port D Lock function is enable
Others: Port D Lock function is disable
To lock the Port D function, a value 0x5FA0 should be written into the PDLKEY field
in this register. To execute a successful write operation on this lock register, the
value written into the PDLKEY field must be 0x5FA0. If the value written into this
field is not equal to 0x5FA0, any write operations on the PDLOCKR register will be
aborted. The result of a read operation on the PDLKEY field returns the GPIO Port
D Lock Status which indicates whether the GPIO Port D is locked or not. If the read
value of the PDLKEY field is 0, this indicates that the GPIO Port D Lock function is
disabled. Otherwise, it indicates that the GPIO Port D Lock function is enabled as
the read value is equal to 1.
[15:0]
PDLOCKn
GPIO Port D pin n Lock Control Bits (n=0~15)
0: Port D pin n is not locked
1: Port D pin n is locked
The PDLOCKn bits are used to lock the configurations of corresponding GPIO Pins
when the correct Lock Key is applied to the PDLKEY field. The locked configurations
including PDDIRn, PDINENn, PDPUn, PDPDn and PDODn setting in the related
GPIO registers. Additionally, the GPDCFGR field which is used to configure the
alternative function of the associated GPIO pin will also be locked. Note that the
PDLOCKR can only be written once which means that PDLKEY and PDLOCKn (lock
control bit) should be written together and can not be changed until a system reset or
GPIO Port D reset occurs.
Rev. 1.00
153 of 628
August 13, 2012
General Purpose I/O (GPIO)
PDLKEY
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Data Input Register – PDDINR
This register specifies the GPIO Port D input data.
Offset:
0x01C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDDIN
Type/Reset
RO
0
7
RO
0
RO
6
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
PDDIN
Type/Reset
RO
0
RO
0
RO
0
RO
0
RO
0
Bits
Field
Descriptions
[15:0]
PDDINn
GPIO Port D pin n Data Input Bits (n=0~15)
0: The input data of corresponding pin is 0
1: The input data of corresponding pin is 1
Rev. 1.00
154 of 628
RO
0
RO
0
RO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Output Data Register – PDDOUTR
This register specifies the GPIO Port D output data.
Offset:
0x020
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDDOUT
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PDDOUT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PDDOUTn
GPIO Port D pin n Data Output Bits (n=0~15)
0: Data to be output on pin n is 0
1: Data to be output on pin n is 1
Rev. 1.00
155 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Output Set/Reset Control Register – PDSRR
This register is used to set or reset the corresponding bit of the GPIO Port D output data.
Offset:
0x024
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
WO
0
23
WO
0
WO
22
0
21
WO
0
20
WO
0
19
WO
0
18
WO
0
17
WO
0
16
PDRST
Type/Reset
WO
0
15
WO
0
WO
14
0
13
WO
0
12
WO
0
11
WO
0
10
WO
0
9
WO
0
8
PDSET
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PDSET
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[31:16]
PDRSTn
GPIO Port D pin n Output Reset Control Bits (n=0~15)
0: No effect on the PDDOUTn bit
1: Reset the PDDOUTn bit
[15:0]
PDSETn
GPIO Port D pin n Output Set Control Bits (n=0~15)
0: No effect on the PDDOUTn bit
1: Set the PDDOUTn bit
Note that the function enabled by the PDSETn bit has the higher priority if both the
PDSETn and PDRSTn bits are set at the same time.
Rev. 1.00
156 of 628
August 13, 2012
General Purpose I/O (GPIO)
PDRST
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port D Output Reset Register – PDRR
This register is used to reset the corresponding bit of the GPIO Port D output data.
Offset:
0x028
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PDRST
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PDRST
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[15:0]
PDRSTn
GPIO Port D pin n Output Reset Bits (n=0~15)
0: No effect on the PDDOUTn bit
1: Reset the PDDOUTn bit
Rev. 1.00
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WO
0
WO
0
WO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Data Direction Control Register – PEDIRCR
This register is used to control the direction of GPIO Port E pin as input or output.
Offset:
0x000
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PEDIR
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PEDIR
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PEDIRn
GPIO Port E pin n Direction Control Bits (n=0~15)
0: Pin n is input mode
1: Pin n is output mode
Rev. 1.00
158 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Input Function Enable Control Register – PEINER
This register is used to enable or disable the GPIO Port E input function.
Offset:
0x004
Reset value: 0x0000_D000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PEINEN
Type/Reset
RW
1
7
RW
1
RW
6
0
5
RW
1
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PEINEN
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PEINENn
GPIO Port E pin n Input Enable Control Bits (n=0~15)
0: Pin n input function is disabled
1: Pin n input function is enabled
When the pin n input function is disabled, the input Schmitt trigger will be turned off
and the Schmitt trigger output will remain at a zero state.
Rev. 1.00
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August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Pull-Up Selection Register – PEPUR
This register is used to enable or disable the GPIO Port E pull-up function.
Offset:
0x008
Reset value: 0x0000_E000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PEPU
Type/Reset
RW
1
7
RW
1
RW
6
1
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PEPU
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PEPUn
GPIO Port E pin n Pull-Up Selection Control Bits (n=0~15)
0: Pin n pull-up function is disabled
1: Pin n pull-up function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
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August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Pull-Down Selection Register – PEPDR
This register is used to enable or disable the GPIO Port E pull-down function.
Offset:
0x00C
Reset value: 0x0000_1000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PEPD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
1
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PEPD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PEPDn
GPIO Port E pin n Pull-Down Selection Control Bits (n=0~15)
0: Pin n pull-down function is disabled
1: Pin n pull-down function is enabled
Note: When the pull-up and pull-down functions are both enabled, the pull-up
function will have the higher priority and therefore the pull-down function will
be blocked and disabled.
Rev. 1.00
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August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Open Drain Selection Register – PEODR
This register is used to enable or disable the GPIO Port E open drain function.
Offset:
0x010
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PEOD
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PEOD
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[15:0]
PEODn
GPIO Port E pin n Open Drain Selection Control Bits (n=0~15)
0: Pin n Open Drain output is disabled (The output type is CMOS output)
1: Pin n Open Drain output is enabled (The output type is open-drain output)
Rev. 1.00
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0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Output Current Drive Selection Register – PEDRVR
This register specifies the GPIO Port E output driving current.
Offset:
0x014
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
18
17
16
10
9
8
General Purpose I/O (GPIO)
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
PEDV
Type/Reset
7
6
5
4
3
2
PEDV
Type/Reset
RW
0
RW
0
1
0
Reserved
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[10:5]
PEDVn
GPIO Port E pin n Output Current Drive Selection Control Bits (n=5~10)
0: 4mA source/sink current
1: 8mA source/sink current
Rev. 1.00
163 of 628
RW
0
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Lock Register – PELOCKR
This register specifies the GPIO Port E lock configuration.
Offset:
0x018
Reset value:
0x0000_0000
31
30
29
28
27
26
25
24
RW
0
23
RW
0
RW
22
0
21
RW
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
PELKEY
Type/Reset
RW
0
15
RW
0
RW
14
0
13
RW
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
PELOCK
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PELOCK
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:16]
PELKEY
GPIO Port E Lock Key
0x5FA0: Port E Lock function is enable
Others: Port E Lock function is disable
To lock the Port E function, a value 0x5FA0 should be written into the PELKEY field
in this register. To execute a successful write operation on this lock register, the
value written into the PELKEY field must be 0x5FA0. If the value written into this
field is not equal to 0x5FA0, any write operations on the PELOCKR register will be
aborted. The result of a read operation on the PELKEY field returns the GPIO Port
E Lock Status which indicates whether the GPIO Port E is locked or not. If the read
value of the PELKEY field is 0, this indicates that the GPIO Port E Lock function is
disabled. Otherwise, it indicates that the GPIO Port E Lock function is enabled as the
read value is equal to 1.
[15:0]
PELOCKn
GPIO Port E pin n Lock Control Bits (n=0~15)
0: Port E pin n is not locked
1: Port E pin n is locked
The PELOCKn bits are used to lock the configurations of corresponding GPIO Pins
when the correct Lock Key is applied to the PELKEY field. The locked configurations
including PEDIRn, PEINENn, PEPUn, PEPDn, PEODn and PEDVn setting in the
related GPIO registers. Additionally, the GPECFGR field which is used to configure
the alternative function of the associated GPIO pin will also be locked. Note that the
PELOCKR can only be written once which means that PELKEY and PELOCKn (lock
control bit) should be written together and can not be changed until a system reset or
GPIO Port E reset occurs.
Rev. 1.00
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August 13, 2012
General Purpose I/O (GPIO)
PELKEY
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Data Input Register – PEDINR
This register specifies the GPIO Port E input data.
Offset:
0x01C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PEDIN
Type/Reset
RO
0
7
RO
0
RO
6
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
PEDIN
Type/Reset
RO
0
RO
0
RO
0
RO
0
RO
0
Bits
Field
Descriptions
[15:0]
PEDINn
GPIO Port E pin n Data Input Bits (n=0~15)
0: The input data of corresponding pin is 0
1: The input data of corresponding pin is 1
Rev. 1.00
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RO
0
RO
0
RO
0
August 13, 2012
General Purpose I/O (GPIO)
26
Reserved
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Output Data Register – PEDOUTR
This register specifies the GPIO Port E input data.
Offset:
0x020
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PEDOUT
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
1
RW
0
0
PEDOUT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15:0]
PEDOUTn
GPIO Port E pin n Data Output Bits (n=0~15)
0: Data to be output on pin n is 0
1: Data to be output on pin n is 1
Rev. 1.00
166 of 628
RW
0
RW
0
RW
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Output Set/Reset Control Register – PESRR
This register is used to set or reset the corresponding bit of the GPIO Port E output data.
Offset:
0x024
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
WO
0
23
WO
0
WO
22
0
21
WO
0
20
WO
0
19
WO
0
18
WO
0
17
WO
0
16
PERST
Type/Reset
WO
0
15
WO
0
WO
14
0
13
WO
0
12
WO
0
11
WO
0
10
WO
0
9
WO
0
8
PESET
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PESET
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[31:16]
PERSTn
GPIO Port E pin n Output Reset Control Bits (n=0~15)
0: No effect on the PEDOUTn bit
1: Reset the PEDOUTn bit
[15:0]
PESETn
GPIO Port E pin n Output Set Control Bits (n=0~15)
0: No effect on the PEDOUTn bit
1: Set the PEDOUTn bit
Note that the function enabled by the PESETn bit has the higher priority if both the
PESETn and PERSTn bits are set at the same time.
Rev. 1.00
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August 13, 2012
General Purpose I/O (GPIO)
PERST
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Port E Output Reset Register – PERR
This register is used to reset the corresponding bit of the GPIO Port E output data.
Offset:
0x028
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
PERST
Type/Reset
WO
0
7
WO
0
WO
6
0
5
WO
0
4
WO
0
3
WO
0
2
WO
0
1
WO
0
0
PERST
Type/Reset
WO
0
WO
0
WO
0
WO
0
WO
0
Bits
Field
Descriptions
[15:0]
PERSTn
GPIO Port E pin n Output Reset Bits (n=0~15)
0: No effect on the PEDOUTn bit
1: Reset the PEDOUTn bit
Rev. 1.00
168 of 628
WO
0
WO
0
WO
0
August 13, 2012
General Purpose I/O (GPIO)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
9
Alternate Function I/O Control Unit (AFIO)
Introduction
APB
APBinterface
interface
AFi
AFi
(from peripheral i)
(from peripheral i)
AFIO configuration
AFIO configuration
registers
registers
Alternate Function
Alternate Function
Outputs Selections
Outputs Selections
AFj
AFj
(from peripheral j)
(from peripheral j)
AF control
AF control
signals
signals
GPIO
GPIO
Module
Module
GPIOx
GPIOx
GPIO
GPIO
Module
Module
GPIOx
GPIOx
AF output
AF output
signals
signals
APB
APBinterface
interface
Alternate function output through GPIO
Alternate function output through GPIO
AFIO configuration
AFIO configuration
registers
registers
Peripheral m
Peripheral m
Peripheral n
Peripheral n
AF control
AF control
signals
signals
AFm
AFm
AFn
AFn
Alternate function input through GPIO
Alternate function input through GPIO
Figure 20. AFIO Block Diagram
Rev. 1.00
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August 13, 2012
Alternate Function I/O Control Unit (AFIO)
In order to expand the flexibility of the GPIO or the usage of peripheral functions, each I/O pin can
be configured to have up to four different functions such as GPIO or IP functions by setting the
GPxCFGR register where x is the different port name. According to the usage of the IP resource
and application requirements, suitable pin-out locations can be selected by using the peripheral I/O
remapping mechanism. Additionally, various GPIO pins can be selected to be the EXTI interrupt
line by setting the EXTInPIN [3:0] field in the ESSRn register to trigger an interrupt or event.
Please refer to the EXTI section for more details.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Features
▀ APB slave interface for register access
▀ EXTI source selection
▀ Configurable pin function for each GPIO, up to four alternative functions on each pin
Functional Descriptions
The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure. For
example, the user can set the EXTI0PIN [3:0] field in the ESSR0 register to b0000 to select the
GPIO PA0 pin as EXTI line 0 input. Since not all the pins of the Port A~E pins are available in all
package types, please refer to the pin assignment section for detailed pin information. The setting
of the EXTInPIN [3:0] field is invalid when the corresponding pin is not available.
EXTIx Pin Selection
EXTI 0 PIN
PA0
PB0
PC0
PD0
PE0
000
001
010
EXTI 0
011
100
EXTI 15 PIN
PA15
PB15
PC15
PD15
PE15
000
001
010
EXTI 15
011
100
Figure 21. EXTI Channel Input Selection
Rev. 1.00
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August 13, 2012
Alternate Function I/O Control Unit (AFIO)
External Interrupt Pin Selection
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Alternate Function
Up to four alternative functions can be chosen for each I/O pad by setting the PxCFGn [1:0] field
in the GPxCFGR (x=A~E) register. Refer to the register description section for detailed AFIO
assignments. The following description shows the setting of the PxCFGn [1:0] field. Note that if the
Operational Amplifier/Comparator is active, then pins PE [7:5] or PE [10:8] can not be set as other
AFIO functional pins simultaneously.
PxCFGn [1:0]=00: The default alternated function (after reset).
PxCFGn [1:0]=01: Alternate Function 1
PxCFGn [1:0]=10: Alternate Function 2
PxCFGn [1:0]=11: Alternate Function 3
Register Map
The following table shows the AFIO register and reset value.
Table 22. AFIO Register Map
Register
Offset
Description
Reset Value
AFIO Base Address=0x4002_2000
Rev. 1.00
ESSR0
0x000
EXTI Source Selection Register 0
0x0000_0000
ESSR1
0x004
EXTI Source Selection Register 1
0x0000_0000
GPACFGR
0x008
GPIO Port A Configuration Register
0x0000_0000
GPBCFGR
0x00C
GPIO Port B Configuration Register
0x0000_0000
GPCCFGR
0x010
GPIO Port C Configuration Register
0x0000_0000
GPDCFGR
0x014
GPIO Port D Configuration Register
0x0000_0000
GPECFGR
0x018
GPIO Port E Configuration Register
0x0000_0000
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August 13, 2012
Alternate Function I/O Control Unit (AFIO)
▀
▀
▀
▀
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
EXTI Source Selection Register 0 – ESSR0
This register specifies the I/O selection of EXTI0~EXTI7.
Offset:
0x000
Reset value: 0x0000_0000
30
29
28
27
26
25
EXTI7PIN
Type/Reset
RW
0
23
RW
0
22
RW
0
21
EXTI6PIN
RW
0
20
RW
0
19
RW
0
18
RW
0
15
RW
0
14
RW
0
13
RW
0
7
RW
0
6
RW
RW
0
12
0
5
RW
0
11
RW
0
10
RW
0
RW
0
RW
0
RW
0
RW
0
8
EXTI2PIN
RW
0
4
0
RW
16
9
RW
0
3
RW
0
2
RW
0
1
EXTI1PIN
Type/Reset
0
EXTI4PIN
EXTI3PIN
Type/Reset
RW
17
EXTI5PIN
Type/Reset
24
RW
0
0
EXTI0PIN
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
[31:0]
EXTInPIN[3:0] EXTIn Pin Selection (n=0~7)
0000: PA Bit n is selected as EXTIn source signal
0001: PB Bit n is selected as EXTIn source signal
0010: PC Bit n is selected as EXTIn source signal
0011: PD Bit n is selected as EXTIn source signal
0100: PE Bit n is selected as EXTIn source signal
Others: Reserved
Note: Since not all GPIO pins are available in all products and package types, refer
to the pin assignment section for detailed pin information. The EXTInPIN [3:0]
field setting is invalid when the corresponding pin is not available.
Rev. 1.00
Descriptions
172 of 628
August 13, 2012
Alternate Function I/O Control Unit (AFIO)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Source Selection Register 1 – ESSR1
This register specifies the I/O selection of EXTI8~EXTI15.
Offset:
0x004
Reset value: 0x0000_0000
31
30
29
28
27
26
25
RW
0
RW
23
0
22
RW
0
21
EXTI14PIN
RW
0
20
RW
0
19
RW
0
18
RW
0
RW
15
0
14
RW
0
13
RW
0
RW
7
0
6
RW
0
12
0
5
RW
0
11
RW
0
10
RW
0
RW
0
RW
RW
0
RW
0
8
EXTI10PIN
RW
0
4
0
0
16
9
RW
0
3
RW
0
2
RW
0
1
EXTI9PIN
Type/Reset
RW
EXTI12PIN
RW
EXTI11PIN
Type/Reset
0
17
EXTI13PIN
Type/Reset
RW
RW
0
0
EXTI8PIN
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31:0]
EXTInPIN[3:0]
EXTIn Pin Selection (n=8~15)
0000: PA Bit n is selected as EXTIn source signal
0001: PB Bit n is selected as EXTIn source signal
0010: PC Bit n is selected as EXTIn source signal
0011: PD Bit n is selected as EXTIn source signal
0100: PE Bit n is selected as EXTIn source signal
Others: Reserved
Note: Since not all Port GPIO pins are available in all products and package
types, please refer to the pin assignment section for detailed pin
information. The EXTInPIN [3:0] field setting is invalid when the
corresponding pin is not available.
Rev. 1.00
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August 13, 2012
Alternate Function I/O Control Unit (AFIO)
EXTI15PIN
Type/Reset
24
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
GPIO A Configuration Register – GPACFGR
This register specifies the GPIO Port A pin alternative function.
Offset:
0x008
Reset value: 0x0000_0000
31
30
29
28
Type/Reset
RW
0
23
RW
0
22
RW
0
21
RW
0
15
RW
0
14
RW
0
7
RW
RW
0
13
0
6
Rev. 1.00
RW
0
RW
RW
0
19
RW
0
12
RW
0
5
0
0
RW
4
RW
0
0
RW
174 of 628
0
RW
0
17
RW
0
10
RW
0
3
0
24
PACFG12
RW
2
RW
0
0
RW
0
8
RW
0
1
0
RW
PACFG4
RW
0
0
PACFG1
RW
0
16
9
0
RW
PACFG8
PACFG5
PACFG2
RW
RW
18
11
0
25
PACFG9
PACFG6
PACFG3
Type/Reset
26
PACFG13
PACFG10
PACFG7
Type/Reset
RW
20
PACFG11
Type/Reset
27
PACFG14
PACFG0
RW
0
RW
0
August 13, 2012
Alternate Function I/O Control Unit (AFIO)
PACFG15
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[31:30]
PACFG15
Port A pin 15 AFIO Configuration
PACFG14
Function
00
PA15
01
GT1_CH3
10
Reserved
11
Reserved
Port A pin 14 AFIO Configuration
PACFG14 [1:0]
[27:26]
[25:24]
PACFG13
PACFG12
Function
00
PA14
01
GT1_CH2
10
Reserved
11
Reserved
Port A pin 13 AFIO Configuration
PACFG13 [1:0]
Function
00
PA13
01
GT1_CH1
10
Reserved
11
Reserved
Port A pin 12 AFIO Configuration
PACFG12 [1:0]
[23:22]
[21:20]
Rev. 1.00
PACFG11
PACFG10
Alternate Function I/O Control Unit (AFIO)
[29:28]
PACFG15 [1:0]
Function
00
PA12
01
GT1_CH0
10
Reserved
11
Reserved
Port A pin 11 AFIO Configuration
PACFG11 [1:0]
Function
00
PA11
01
SPI1_MISO
10
UR0_RX
11
Reserved
Port A pin 10 AFIO Configuration
PACFG10 [1:0]
Function
00
PA10
01
SPI1_MOSI
10
UR0_TX
11
Reserved
175 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[19:18]
PACFG9
Port A pin 9 AFIO Configuration
PACFG8
Function
00
PA9
01
SPI1_SCK
10
UR0_CTS/SCK
11
Reserved
Port A pin 8 AFIO Configuration
PACFG8 [1:0]
[15:14]
[13:12]
PACFG7
PACFG6
Function
00
PA8
01
SPI1_SEL
10
UR0_RTS/TXE
11
Reserved
Port A pin 7 AFIO Configuration
PACFG7 [1:0]
Function
00
PA7
01
ADC_IN7
10
UR1_RX
11
SPI1_MISO
Port A pin 6 AFIO Configuration
PACFG6 [1:0]
[11:10]
[9:8]
PACFG5
PACFG4
Function
00
PA6
01
ADC_IN6
10
UR1_TX
11
SPI1_MOSI
Port A pin 5 AFIO Configuration
PACFG5 [1:0]
Function
00
PA5
01
ADC_IN5
10
UR1_CTS/SCK
11
SPI1_SCK
Port A pin 4 AFIO Configuration
PACFG4 [1:0]
Rev. 1.00
Alternate Function I/O Control Unit (AFIO)
[17:16]
PACFG9 [1:0]
Function
00
PA4
01
ADC_IN4
10
UR1_RTS/TXE
11
SPI1_SEL
176 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[7:6]
PACFG3
Port A pin 3 AFIO Configuration
PACFG2
Function
00
PA3
01
ADC_IN3
10
UR0_RX
11
GT1_CH3
Port A pin 2 AFIO Configuration
PACFG2 [1:0]
[3:2]
[1:0]
PACFG1
PACFG0
Function
00
PA2
01
ADC_IN2
10
UR0_TX
11
GT1_CH2
Port A pin 1 AFIO Configuration
PACFG1 [1:0]
Function
00
PA1
01
ADC_IN1
10
SCI_DIO
11
GT1_CH1
Port A pin 0 AFIO Configuration
PACFG0 [1:0]
Rev. 1.00
Alternate Function I/O Control Unit (AFIO)
[5:4]
PACFG3 [1:0]
Function
00
PA0
01
ADC_IN0
10
SCI_CLK
11
GT1_CH0
177 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
GPIO B Configuration Register – GPBCFGR
This register specifies the GPIO Port B pin alternative function.
Offset:
0x00C
Reset value: 0x0000_0000
31
30
29
28
RW
0
23
RW
0
22
PBCFG14
RW
0
21
RW
0
15
RW
0
14
RW
0
7
RW
0
13
0
6
Rev. 1.00
RW
0
RW
0
0
0
RW
4
0
0
RW
178 of 628
PBCFG12
RW
0
17
RW
0
0
RW
2
0
0
RW
0
PBCFG4
RW
0
1
0
RW
8
RW
0
0
PBCFG1
RW
0
PBCFG8
RW
9
0
RW
16
PBCFG5
RW
3
0
0
10
PBCFG2
RW
24
PBCFG9
RW
11
0
RW
18
PBCFG6
RW
5
0
RW
25
PBCFG13
RW
19
12
PBCFG3
Type/Reset
0
PBCFG10
RW
PBCFG7
Type/Reset
RW
20
PBCFG11
Type/Reset
26
PBCFG0
RW
0
RW
0
August 13, 2012
Alternate Function I/O Control Unit (AFIO)
PBCFG15
Type/Reset
27
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[31:30]
PBCFG15
Port B pin 15 AFIO Configuration
PBCFG14
Function
00
PB15
01
UR1_RTS/TXE
10
Reserved
11
Reserved
Port B pin 14 AFIO Configuration
PBCFG14 [1:0]
[27:26]
[25:24]
[23:22]
[21:20]
Rev. 1.00
PBCFG13
PBCFG12
PBCFG11
PBCFG10
Alternate Function I/O Control Unit (AFIO)
[29:28]
PBCFG15 [1:0]
Function
00
PB14
01
UR1_CTS/SCK
10
GT1_ETI
11
Reserved
Port B pin 13 AFIO Configuration
PBCFG13 [1:0]
Function
00
PB13
01
UR0_RX
10
Reserved
11
Reserved
Port B pin 12 AFIO Configuration
PBCFG12 [1:0]
Function
00
XTALOUT
01
PB12
10
Reserved
11
Reserved
Port B pin 11 AFIO Configuration
PBCFG11 [1:0]
Function
00
XTALIN
01
PB11
10
Reserved
11
Reserved
Port B pin 10 AFIO Configuration
PBCFG10 [1:0]
Function
00
PB10
01
UR0_TX
10
Reserved
11
Reserved
179 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[19:18]
PBCFG9
Port B pin 9 AFIO Configuration
PBCFG8
Function
00
PB9
01
UR0_CTS/SCK
10
Reserved
11
Reserved
Port B pin 8 AFIO Configuration
PBCFG8 [1:0]
[15:14]
[13:12]
PBCFG7
PBCFG6
Function
00
PB8
01
UR0_RTS/TXE
10
Reserved
11
Reserved
Port B pin 7 AFIO Configuration
PBCFG7 [1:0]
Function
00
PB7
01
GT0_ETI
10
I2C1_SDA
11
UR0_DTR
Port B pin 6 AFIO Configuration
PBCFG6 [1:0]
[11:10]
[9:8]
Rev. 1.00
PBCFG5
PBCFG4
Alternate Function I/O Control Unit (AFIO)
[17:16]
PBCFG9 [1:0]
Function
00
RTCOUT
01
PB6_WAKEUP
10
Reserved
11
Reserved
Port B pin 5 AFIO Configuration
PBCFG5 [1:0]
Function
00
XTAL32KOUT
01
PB5
10
Reserved
11
Reserved
Port B pin 4 AFIO Configuration
PBCFG4 [1:0]
Function
00
XTAL32KIN
01
PB4
10
Reserved
11
Reserved
180 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[7:6]
PBCFG3
Port B pin 3 AFIO Configuration
PBCFG2
Function
00
PB3
01
GT0_CH3
10
UR1_RX
11
SPI0_MISO
Port B pin 2 AFIO Configuration
PBCFG2 [1:0]
[3:2]
[1:0]
PBCFG1
PBCFG0
Function
00
PB2
01
GT0_CH2
10
UR1_TX
11
SPI0_MOSI
Port B pin 1 AFIO Configuration
PBCFG1 [1:0]
Function
00
PB1
01
GT0_CH1
10
UR1_CTS/SCK
11
SPI0_SCK
Port B pin 0 AFIO Configuration
PACFG0 [1:0]
Rev. 1.00
Alternate Function I/O Control Unit (AFIO)
[5:4]
PBCFG3 [1:0]
Function
00
PB0
01
GT0_CH0
10
UR1_RTS/TXE
11
SPI0_SEL
181 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
GPIO C Configuration Register – GPCCFGR
This register specifies the GPIO Port C pin alternative function.
Offset:
0x010
Reset value: 0x0000_0000
31
30
29
28
RW
0
23
RW
0
22
PCCFG14
RW
0
21
RW
0
15
RW
0
14
RW
0
7
RW
0
13
0
6
Rev. 1.00
RW
0
RW
0
0
0
RW
4
0
0
RW
182 of 628
PCCFG12
RW
0
17
RW
0
0
RW
2
0
0
RW
0
PCCFG4
RW
0
1
0
RW
8
RW
0
0
PCCFG1
RW
0
PCCFG8
RW
9
0
RW
16
PCCFG5
RW
3
0
0
10
PCCFG2
RW
24
PCCFG9
RW
11
0
RW
18
PCCFG6
RW
5
0
RW
25
PCCFG13
RW
19
12
PCCFG3
Type/Reset
0
PCCFG10
RW
PCCFG7
Type/Reset
RW
20
PCCFG11
Type/Reset
26
PCCFG0
RW
0
RW
0
August 13, 2012
Alternate Function I/O Control Unit (AFIO)
PCCFG15
Type/Reset
27
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[31:30]
PCCFG15
Port C pin 15 AFIO Configuration
PCCFG14
Function
00
PC15
01
SCI_DET
10
GT0_ETI
11
UR0_DSR
Port C pin 14 AFIO Configuration
PCCFG14 [1:0]
[27:26]
[25:24]
PCCFG13
PCCFG12
PC14
01
SCI_DIO
10
MT_CH0N
11
UR1_CTS/SCK
Port C pin 13 AFIO Configuration
PCCFG13 [1:0]
Function
00
PC13
01
SCI_CLK
10
MT_CH0
11
UR1_RTS/TXE
Port C pin 12 AFIO Configuration
Function
HT32F1755/HT32F1765
00
PC12
01
I C0_SDA
10
MT_CH1N
11
PCCFG11
Function
00
PCCFG12 [1:0]
[23:22]
2
UR0_CTS/SCK
HT32F1755/HT32F1765
00
PC11
01
I2C0_SCL
11
HT32F2755
MT_CH1
UR0_RTS/TXE
CSIF_PCK
Port C pin 10 AFIO Configuration
PCCFG10 [1:0]
Rev. 1.00
CSIF_MCK
Function
10
PCCFG10
HT32F2755
Port C pin 11 AFIO Configuration
PCCFG11 [1:0]
[21:20]
Alternate Function I/O Control Unit (AFIO)
[29:28]
PCCFG15 [1:0]
Function
00
PC10
01
SCI_DET
10
MT_ETI
11
UR0_RX
183 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[19:18]
PCCFG9
Port C pin 9 AFIO Configuration
[15:14]
PCCFG8
PCCFG7
Function
00
PC9_BOOT1
01
Reserved
10
Reserved
11
Reserved
Port C pin 8 AFIO Configuration
PCCFG8 [1:0]
Function
00
PC8_BOOT0
01
CKOUT
10
Reserved
11
UR0_TX
Port C pin 7 AFIO Configuration
PCCFG7 [1:0]
[13:12]
PCCFG6
Function
00
PC7
01
I C1_SDA
10
SCI_DIO
11
Reserved
2
Port C pin 6 AFIO Configuration
PCCFG6 [1:0]
[11:10]
[9:8]
PCCFG5
PCCFG4
Function
00
PC6
01
I2C1_SCL
10
SCI_CLK
11
Reserved
Port C pin 5 AFIO Configuration
PCCFG5 [1:0]
Function
00
PC5
01
UR1_RX
10
I2C0_SDA
11
Reserved
Port C pin 4 AFIO Configuration
PCCFG4 [1:0]
Rev. 1.00
Alternate Function I/O Control Unit (AFIO)
[17:16]
PCCFG9 [1:0]
Function
00
PC4
01
UR1_TX
10
I2C0_SCL
11
Reserved
184 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[7:6]
PCCFG3
Port C pin 3 AFIO Configuration
PCCFG2
Function
00
PC3
01
SPI1_MISO
10
GT1_CH3
11
UR0_DCD
Port C pin 2 AFIO Configuration
PCCFG2 [1:0]
[3:2]
[1:0]
PCCFG1
PCCFG0
Function
00
PC2
01
SPI1_MOSI
10
GT1_CH2
11
UR0_RI
Port C pin 1 AFIO Configuration
PCCFG1 [1:0]
Function
00
PC1
01
SPI1_SCK
10
GT1_CH1
11
I2C1_SDA
Port C pin 0 AFIO Configuration
PCCFG0 [1:0]
Rev. 1.00
Alternate Function I/O Control Unit (AFIO)
[5:4]
PCCFG3 [1:0]
Function
00
PC0
01
SPI1_SEL
10
GT1_CH0
11
I2C1_SCL
185 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
GPIO D Configuration Register – GPDCFGR
This register specifies the GPIO Port D pin alternative function.
Offset:
0x014
Reset value: 0x0000_0000
31
30
29
28
RW
0
23
RW
0
22
PDCFG14
RW
0
21
RW
0
15
RW
0
14
RW
0
7
RW
0
13
0
6
Rev. 1.00
RW
0
RW
0
0
0
RW
4
0
0
RW
186 of 628
PDCFG12
RW
0
17
RW
0
0
RW
2
0
0
RW
0
PDCFG4
RW
0
1
0
RW
8
RW
0
0
PDCFG1
RW
0
PDCFG8
RW
9
0
RW
16
PDCFG5
RW
3
0
0
10
PDCFG2
RW
24
PDCFG9
RW
11
0
RW
18
PDCFG6
RW
5
0
RW
25
PDCFG13
RW
19
12
PDCFG3
Type/Reset
0
PDCFG10
RW
PDCFG7
Type/Reset
RW
20
PDCFG11
Type/Reset
26
PDCFG0
RW
0
RW
0
August 13, 2012
Alternate Function I/O Control Unit (AFIO)
PDCFG15
Type/Reset
27
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[31:30]
PDCFG15
Port D pin 15 AFIO Configuration
PDCFG14
Function
00
PD15
01
MT_CH1N
10
SCI_DIO
11
Reserved
Port D pin 14 AFIO Configuration
PDCFG14 [1:0]
[27:26]
[25:24]
[23:22]
PDCFG13
PDCFG12
PDCFG11
PD14
01
MT_CH1
10
SCI_CLK
11
Reserved
Port D pin 13 AFIO Configuration
PDCFG13 [1:0]
Function
00
PD13
01
MT_CH0N
10
I2C0_SDA
11
GT0_ETI
Port D pin 12 AFIO Configuration
PDCFG12 [1:0]
Function
00
PD12
01
MT_CH0
10
I2C0_SCL
11
GT1_ETI
Port D pin 11 AFIO Configuration
HT32F1755/HT32F1765
PD11
01
SPI0_MISO
10
MT_BRK
GT1_CH3
HT32F2755
CSIF_D3
Port D pin 10 AFIO Configuration
PDCFG10 [1:0]
Function
HT32F1755/HT32F1765
00
PD10
01
SPI0_MOSI
10
MT_CH3
11
Rev. 1.00
Function
00
11
PDCFG10
Function
00
PDCFG11 [1:0]
[21:20]
Alternate Function I/O Control Unit (AFIO)
[29:28]
PDCFG15 [1:0]
GT1_CH2
187 of 628
HT32F2755
CSIF_D2
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[19:18]
PDCFG9
Port D pin 9 AFIO Configuration
PDCFG9 [1:0]
PD9
01
SPI0_SCK
10
MT_CH2N
[13:12]
[11:10]
[9:8]
Rev. 1.00
PDCFG6
PDCFG5
PDCFG4
Function
HT32F1755/HT32F1765
00
PD8
01
SPI0_SEL
10
MT_CH2
11
PDCFG7
CSIF_D1
Port D pin 8 AFIO Configuration
PDCFG8 [1:0]
[15:14]
GT1_CH1
HT32F2755
Alternate Function I/O Control Unit (AFIO)
PDCFG8
HT32F1755/HT32F1765
00
11
[17:16]
Function
GT1_CH0
HT32F2755
CSIF_D0
Port D pin 7 AFIO Configuration
PDCFG7 [1:0]
Function
00
PD7
01
SPI1_MISO
10
Reserved
11
Reserved
Port D pin 6 AFIO Configuration
PDCFG6 [1:0]
Function
00
PD6
01
SPI1_MOSI
10
Reserved
11
Reserved
Port D pin 5 AFIO Configuration
PDCFG5 [1:0]
Function
00
PD5
01
SPI1_SCK
10
Reserved
11
Reserved
Port D pin 4 AFIO Configuration
PDCFG4 [1:0]
Function
00
PD4
01
SPI1_SEL
10
Reserved
11
Reserved
188 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[7:6]
PDCFG3
Port D pin 3 AFIO Configuration
PDCFG2
Function
00
PD3
01
GT0_CH3
10
SPI0_MISO
11
Reserved
Port D pin 2 AFIO Configuration
PDCFG2 [1:0]
[3:2]
[1:0]
PDCFG1
PDCFG0
Function
00
PD2
01
GT0_CH2
10
SPI0_MOSI
11
UR0_DCD
Port D pin 1 AFIO Configuration
PDCFG1 [1:0]
Function
00
PD1
01
GT0_CH1
10
SPI0_SCK
11
UR0_RI
Port D pin 0 AFIO Configuration
PDCFG0 [1:0]
Rev. 1.00
Alternate Function I/O Control Unit (AFIO)
[5:4]
PDCFG3 [1:0]
Function
00
PD0
01
GT0_CH0
10
SPI0_SEL
11
UR0_DTR
189 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
GPIO E Configuration Register – GPECFGR
This register specifies the GPIO Port E pin alternative function.
Offset:
0x018
Reset value: 0x0000_0000
31
30
29
28
RW
0
23
RW
0
22
PECFG14
RW
0
21
RW
0
15
RW
0
14
RW
0
7
RW
0
13
0
6
Rev. 1.00
RW
0
RW
0
0
0
RW
4
0
0
RW
190 of 628
PECFG12
RW
0
17
RW
0
0
RW
2
0
0
RW
0
PECFG4
RW
0
1
0
RW
8
RW
0
0
PECFG1
RW
0
PECFG8
RW
9
0
RW
16
PECFG5
RW
3
0
0
10
PECFG2
RW
24
PECFG9
RW
11
0
RW
18
PECFG6
RW
5
0
RW
25
PECFG13
RW
19
12
PECFG3
Type/Reset
0
PECFG10
RW
PECFG7
Type/Reset
RW
20
PECFG11
Type/Reset
26
PECFG0
RW
0
RW
0
August 13, 2012
Alternate Function I/O Control Unit (AFIO)
PECFG15
Type/Reset
27
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[31:30]
PECFG15
Port E pin 15 AFIO Configuration
PECFG15 [1:0]
00
JTRST
PE15
10
MT_CH0N
UR1_RX
Function
HT32F1755/HT32F1765
00
[25:24]
[23:22]
[21:20]
PECFG12
PECFG11
PECFG10
JTDI
PE14
10
MT_CH0
UR1_TX
CSIF_HSYNC
Port E pin 13 AFIO Configuration
PECFG13 [1:0]
Function
00
JTMS_SWDIO
01
PE13
10
Reserved
11
Reserved
Port E pin 12 AFIO Configuration
PECFG12 [1:0]
Function
00
JTCK_SWCLK
01
PE12
10
Reserved
11
Reserved
Port E pin 11 AFIO Configuration
PECFG11 [1:0]
Function
00
JTDO_TRACESWO
01
PE11
10
Reserved
11
Reserved
Port E pin 10 AFIO Configuration
PECFG10 [1:0]
Rev. 1.00
HT32F2755
01
11
PECFG13
CSIF_VSYNC
Port E pin 14 AFIO Configuration
PECFG14 [1:0]
[27:26]
HT32F2755
Alternate Function I/O Control Unit (AFIO)
PECFG14
HT32F1755/HT32F1765
01
11
[29:28]
Function
Function
00
PE10
01
AOUT1
10
GT1_ETI
11
I2C1_SDA
191 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[19:18]
PECFG9
Port E pin 9 AFIO Configuration
PECFG8
Function
00
PE9
01
CP1
10
GT0_ETI
11
I2C1_SCL
Port E pin 8 AFIO Configuration
PECFG8 [1:0]
Function
HT32F1755/HT32F1765
00
PE8
01
CN1
10
11
[15:14]
PECFG7
GT0_CH3
SPI1_MISO
HT32F1755/HT32F1765
00
PE7
01
AOUT0
11
CSIF_D6
Function
HT32F1755/HT32F1765
PE6
01
CP0
10
GT0_CH1
SPI1_SCK
HT32F2755
CSIF_D5
Port E pin 5 AFIO Configuration
PECFG5 [1:0]
Function
HT32F1755/HT32F1765
00
PE5
01
CN0
10
GT0_CH0
11
Rev. 1.00
GT0_CH2
SPI1_MOSI
00
11
PECFG5
HT32F2755
Port E pin 6 AFIO Configuration
PECFG6 [1:0]
[11:10]
CSIF_D7
Function
10
PECFG6
HT32F2755
Port E pin 7 AFIO Configuration
PECFG7 [1:0]
[13:12]
Alternate Function I/O Control Unit (AFIO)
[17:16]
PECFG9 [1:0]
SPI1_SEL
192 of 628
HT32F2755
CSIF_D4
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Bits
Field
Descriptions
[9:8]
PECFG4
Port E pin 4 AFIO Configuration
PECFG3
Function
00
PE4
01
MT_ETI
10
Reserved
11
Reserved
Port E pin 3 AFIO Configuration
PECFG3 [1:0]
[5:4]
[3:2]
PECFG2
PECFG1
Function
00
PE3
01
MT_BRK
10
Reserved
11
Reserved
Port E pin 2 AFIO Configuration
PECFG2 [1:0]
Function
00
PE2
01
MT_CH3
10
Reserved
11
Reserved
Port E pin 1 AFIO Configuration
PECFG1 [1:0]
[1:0]
Rev. 1.00
PECFG0
Alternate Function I/O Control Unit (AFIO)
[7:6]
PECFG4 [1:0]
Function
00
PE1
01
MT_CH2N
10
Reserved
11
Reserved
Port E pin 0 AFIO Configuration
PECFG0 [1:0]
Function
00
PE0
01
MT_CH2
10
Reserved
11
Reserved
193 of 628
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
10
Nested Vectored Interrupt Controller (NVIC)
Introduction
Additionally, an integrated simple, 24-bit down count timer (SysTick) is provided by the
CortexTM-M3 to be used as a tick timer for the Real Timer Operation System (RTOS) or as a simple
counter. The SysTick counts down from the preloaded value and generates a system interrupt when
it reached zero.
The accompanying table lists the 16 system exception types and a variety of peripheral interrupts.
Table 23. Exception Types
Exception type
—
Reset
Interrupt Exception Vector
Number Number Address
Priority
Description
—
—
0
0x000
Initial Stack Point value
-3 (Highest)
—
1
0x004
Reset
NMI
-2
—
2
0x008
Non-Maskable Interrupt. The clock
stuck interrupt signal (clock monitor
function provided by Clock Control Unit)
is connected to the NMI input
Hard Fault
-1
—
3
0x00C
All fault classes
Memory
Management
Configurable(1)
—
4
0x010
Memory Protection Unit (MPU)
mismatch, including access violation
and no match
Bus Fault
Configurable(1)
—
5
0x014
Pre-fetch fault, memory access fault
and other address/memory related
Usage Fault
Configurable(1)
—
6
0x018
Usage fault, such as undefined
executed instruction or illegal attempt of
state transition
—
—
—
7
0x01C
Reserved
—
—
—
8
0x020
Reserved
—
—
—
9
0x024
Reserved
—
—
—
10
0x028
Reserved
SVCCall
Configurable
(1)
—
11
0x02C
SVC instruction System service call
Debug Monitor
Configurable(1)
—
12
0x030
Debug monitor, when not halted
—
Configurable
(1)
—
13
0x034
Reserved
PendSV
Configurable
(1)
—
14
0x038
System Service Pendable request
SySTick
Configurable(1)
—
15
0x03C
SysTick timer decremented to zero
CKRDY
Configurable(2)
0
16
0x040
Clock ready interrupt
(HSE, HSI, LSE, LSI, or PLL)
LVD
Configurable(2)
1
17
0x044
Low voltage detection interrupt
Rev. 1.00
194 of 628
August 13, 2012
Nested Vectored Interrupt Controller (NVIC)
In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled
integrated section, which is named as Nested Vectored Interrupt Controller (NVIC), is provided
by the CortexTM-M3. The NVIC controls the system exceptions and the peripheral interrupts
which include functions such as the enable/disable control, priority, clear-pending, active status
report, software trigger and vector table remapping. Refer to the Technical Reference Manual of
CortexTM-M3 for more details.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Exception type
Interrupt Exception Vector
Number Number Address
Priority
Description
Configurable(2)
2
18
0x048
Brown-out detection interrupt
WDT
Configurable
(2)
3
19
0x04C
Watchdog timer global interrupt
RTC
Configurable(2)
4
20
0x050
RTC global interrupt
FMC
Configurable
(2)
5
21
0x054
FMC global interrupt
EVWUP
Configurable
(2)
6
22
0x058
EXTI event wake up interrupt
LPWUP
Configurable(2)
7
23
0x05C
WAKEUP pin interrupt
EXTI0
Configurable
(2)
8
24
0x060
EXTI Line 0 interrupt
EXTI1
Configurable
(2)
9
25
0x064
EXTI Line 1 interrupt
EXTI2
Configurable(2)
10
26
0x068
EXTI Line 2 interrupt
EXTI3
Configurable
(2)
11
27
0x06C
EXTI Line 3 interrupt
EXTI4
Configurable
(2)
12
28
0x070
EXTI Line 4 interrupt
EXTI5
Configurable(2)
13
29
0x074
EXTI Line 5 interrupt
EXTI6
Configurable
(2)
14
30
0x078
EXTI Line 6 interrupt
EXTI7
Configurable
(2)
15
31
0x07C
EXTI Line 7 interrupt
EXTI8
Configurable(2)
16
32
0x080
EXTI Line 8 interrupt
EXTI9
Configurable
(2)
17
33
0x084
EXTI Line 9 interrupt
EXTI10
Configurable
(2)
18
34
0x088
EXTI Line 10 interrupt
EXTI11
Configurable(2)
19
35
0x08C
EXTI Line 11 interrupt
EXTI12
Configurable
(2)
20
36
0x090
EXTI Line 12 interrupt
EXTI13
Configurable
(2)
21
37
0x094
EXTI Line 13 interrupt
EXTI14
Configurable(2)
22
38
0x098
EXTI Line 14 interrupt
EXTI15
Configurable
(2)
23
39
0x09C
EXTI Line 15 interrupt
COMP
Configurable
(2)
24
40
0x0A0
Comparator global interrupt
ADC
Configurable(2)
25
41
0x0A4
ADC global interrupt
—
—
26
42
0x0A8
Reserved
MCTM_BRK
Configurable
(2)
27
43
0x0AC
MCTM break interrupt
MCTM_UP
Configurable(2)
28
44
0x0B0
MCTM update interrupt
MCTM_TR_UP2
Configurable
(2)
29
45
0x0B4
MCTM trigger/update event 2 interrupt
MCTM_CC
Configurable
(2)
30
46
0x0B8
MCTM capture/compare interrupt
—
—
31
47
0x0BC
Reserved
—
—
32
48
0x0C0
Reserved
—
—
33
49
0x0C4
Reserved
—
—
34
50
0x0C8
Reserved
35
51
0x0CC
GPTM0 global interrupt
GPTM0
Configurable
(2)
GPTM1
Configurable
(2)
36
52
0x0D0
GPTM1 global interrupt
—
—
37
53
0x0D4
Reserved
—
—
38
54
0x0D8
Reserved
—
—
39
55
0x0DC
Reserved
—
—
40
56
0x0E0
Reserved
41
57
0x0E4
BFTM0 global interrupt
BFTM0
Rev. 1.00
Configurable
(2)
195 of 628
August 13, 2012
Nested Vectored Interrupt Controller (NVIC)
BOD
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Exception type
Interrupt Exception Vector
Number Number Address
Priority
Description
Configurable(2)
42
58
0x0E8
BFTM1 global interrupt
I C0
Configurable
(2)
43
59
0x0EC
I2C0 global interrupt
I2C1
Configurable(2)
44
60
0x0F0
I2C1 global interrupt
SPI0
Configurable
(2)
45
61
0x0F4
SPI0 global interrupt
SPI1
Configurable
(2)
46
62
0x0F8
SPI1 global interrupt
USART0
Configurable(2)
47
63
0x0FC
USART0 global interrupt
USART1
Configurable
48
64
0x100
USART1 global interrupt
2
(2)
—
—
49
65
0x104
Reserved
—
—
50
66
0x108
Reserved
51
67
0x10C
SCI global interrupt
SCI
—
USB
—
Configurable
(2)
—
52
68
0x110
Reserved
Configurable(2)
53
69
0x114
USB global interrupt
—
54
70
0x118
Reserved
PDMA_CH0
Configurable
(2)
55
71
0x11C
PDMA channel 0 global interrupt
PDMA_CH1
Configurable(2)
56
72
0x120
PDMA channel 1 global interrupt
PDMA_CH2
Configurable
(2)
57
73
0x124
PDMA channel 2 global interrupt
PDMA_CH3
Configurable
(2)
58
74
0x128
PDMA channel 3 global interrupt
PDMA_CH4
Configurable(2)
59
75
0x12C
PDMA channel 4 global interrupt
PDMA_CH5
Configurable
(2)
60
76
0x130
PDMA channel 5 global interrupt
PDMA_CH6
Configurable
(2)
61
77
0x134
PDMA channel 6 global interrupt
PDMA_CH7
Configurable(2)
62
78
0x138
PDMA channel 7 global interrupt
PDMA_CH8
Configurable
(2)
63
79
0x13C
PDMA channel 8 global interrupt
PDMA_CH9
Configurable
(2)
64
80
0x140
PDMA channel 9 global interrupt
PDMA_CH10
Configurable(2)
65
81
0x144
PDMA channel 10 global interrupt
PDMA_CH11
Configurable
(2)
66
82
0x148
PDMA channel 11 global interrupt
CSIF
Configurable
(2)
67
83
0x14C
CSIF global interrupt
Note 1: The exception priority can be changed using the NVIC System Handler Priority Registers. For more
information, refer to the ARM “Technical Reference Manual of Cortex™-M3” document.
2: The interrupt priority can be changed using the NVIC Interrupt Priority Registers. For more information,
refer to the ARM “Technical Reference Manual of Cortex™-M3” document.
Rev. 1.00
196 of 628
August 13, 2012
Nested Vectored Interrupt Controller (NVIC)
BFTM1
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Features
16 system CortexTM-M3 exceptions
Up to 55 maskable peripheral interrupts
16 programmable priority levels – 4 bit interrupt priority setup
Non-Maskable interrupt
Low-latency exception and interrupt handling
Vector table remapping capability
● Integrated simple, 24-bit system timer, SysTick
● 24-bit down counter
● Auto-reloading capability
● Maskable system interrupt generation when counter decrements to 0
● SysTick clock source derived from the HCLK or AHB clock divided by 8
Functional Descriptions
SysTick Calibration
The SysTick Calibration Value Register (SCALIB) is provided by the NVIC to give a reference time
base of 1ms for the RTOS tick timer or other purpose. The TENMS field in the SCALIB register has
a fixed value of 9000 which is the counter reload value to indicate 1 ms when the clock source comes
from the SysTick reference input clock STCLK with a frequency of 9MHz (72MHz divide by 8).
Register Map
The following table shows the NVIC registers and reset values.
Table 24. NVIC Register Map
Register
Offset
Description
Reset Value
NVIC Base Address=0xE000_E000
ICTR
0x004
Interrupt Control Type Register
0x0000_0001
SCTRL
0x010
SysTick Control and Status Register
0x0000_0000
SLOAD
0x014
SysTick Reload Value Register
Unpredictable
SVAL
0x018
SysTick Current Value Register
Unpredictable
SCALIB
0x01C
SysTick Calibration Value Register
0x4000_2328
ISER0_31
0x100
Irq 0 to 31 Set Enable Register
0x0000_0000
ISER32_63
0x104
Irq 32 to 63 Set Enable Register
0x0000_0000
ISER64_95
0x108
Irq 64 to 95 Set Enable Register
0x0000_0000
ICER0_31
0x180
Irq 0 to 31 Clear Enable Register
0x0000_0000
ICER32_63
0x184
Irq 32 to 63 Clear Enable Register
0x0000_0000
ICER64_95
0x188
Irq 64 to 95 Clear Enable Register
0x0000_0000
ISPR0_31
0x200
Irq 0 to 31 Set Pending Register
0x0000_0000
ISPR32_63
0x204
Irq 32 to 63 Set Pending Register
0x0000_0000
ISPR64_95
0x208
Irq 64 to 95 Set Pending Register
0x0000_0000
ICPR0_31
0x280
Irq 0 to 31 Clear Pending Register
0x0000_0000
ICPR32_63
0x284
Irq 32 to 63 Clear Pending Register
0x0000_0000
ICPR64_95
0x288
Irq 64 to 95 Clear Pending Register
0x0000_0000
Rev. 1.00
197 of 628
August 13, 2012
Nested Vectored Interrupt Controller (NVIC)
▀
▀
▀
▀
▀
▀
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register
Offset
Description
Reset Value
0x300
Irq 0 to 31 Active Bit Register
0x0000_0000
IABR32_63
0x304
Irq 32 to 63 Active Bit Register
0x0000_0000
IABR64_95
0x308
Irq 64 to 95 Active Bit Register
0x0000_0000
IRQ0_3
0x400
Irq 0 to 3 Priority Register
0x0000_0000
IRQ4_7
0x404
Irq 4 to 7 Priority Register
0x0000_0000
IRQ8_11
0x408
Irq 8 to 11 Priority Register
0x0000_0000
IRQ12_15
0x40C
Irq 12 to 15 Priority Register
0x0000_0000
IRQ16_19
0x410
Irq 16 to 19 Priority Register
0x0000_0000
IRQ20_23
0x414
Irq 20 to 23 Priority Register
0x0000_0000
IRQ24_27
0x418
Irq 24 to 27 Priority Register
0x0000_0000
IRQ28_31
0x41C
Irq 28 to 31 Priority Register
0x0000_0000
IRQ32_35
0x420
Irq 32 to 35 Priority Register
0x0000_0000
IRQ36_39
0x424
Irq 36 to 39 Priority Register
0x0000_0000
IRQ40_43
0x428
Irq 40 to 43 Priority Register
0x0000_0000
IRQ44_47
0x42C
Irq 44 to 47 Priority Register
0x0000_0000
IRQ48_51
0x430
Irq 48 to 51 Priority Register
0x0000_0000
IRQ52_55
0x434
Irq 52 to 55 Priority Register
0x0000_0000
IRQ56_59
0x438
Irq 56 to 59 Priority Register
0x0000_0000
IRQ60_63
0x43C
Irq 60 to 63 Priority Register
0x0000_0000
IRQ64_67
0x440
Irq 64 to 67 Priority Register
0x0000_0000
ICSR
0xD04
Interrupt Control State Register
0x0000_0000
VTOR
0xD08
Vector Table Offset Register
0x0000_0000
AIRCR
0xD0C
Application Interrupt/Reset Control Register
0xFA05_0000
SCR
0xD10
System Control Register
0x0000_0000
CCR
0xD14
Configuration Control Register
0x0000_0000
SHPR4-7
0xD18
System Handlers 4-7 Priority Register
0x0000_0000
SHPR8_11
0xD1C
System Handlers 8-11 Priority Register
0x0000_0000
SHPR12_15
0xD20
System Handlers 12-15 Priority Register
0x0000_0000
SHCSR
0xD24
System Handler Control and State Register
0x0000_0000
CFSR
0xD28
Configurable Fault Status Registers
0x0000_0000
HFSR
0xD2C
Hard Fault Status Register
0x0000_0000
DFSR
0xD30
Debug Fault Status Register
0x0000_0000
MMFAR
0xD34
Mem Manage Address Register
Unpredictable
BFAR
0xD38
Bus Fault Address Register
Unpredictable
AFSR
0xD3C
Auxiliary Fault Status Register
0x0000_0000
STIR
0xF00
Software Trigger Interrupt Register
0x0000_0000
Note: For more information of the above detail register descriptions, please refer to the “Technical Reference
Manual of Cortex™-M3” document from ARM.
Rev. 1.00
198 of 628
August 13, 2012
Nested Vectored Interrupt Controller (NVIC)
IABR0_31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
11
External Interrupt/Event Controller (EXTI)
Introduction
EXTInSC
Software
Activate
Interrupt
Edge/Level
Control
(SRCnTYPE[2:0])
DBnEN
16
Debounce
16
16
Edge/Level
detection
16
16
Interrupt
control &
Status
16
External I/O
Interrupt
(To NVIC control unit)
High or Low levels or
Positive or Negative or Both edges
DBnCNT[27:0]
~
EXTI0
16
Interrupt enable bits
& Interrupt flags
EXTI15
High or Low level
Deglitch
16
Polarity
detection
16
16
Polarity
Control
Event control
& Status
Event enable bits
& Event flags
16
External I/O
Event
(To NVIC control unit)
(To clock control unit)
(EXTInPOL)
Figure 22. EXTI Block Diagram
Features
▀ Up to 16 EXTI lines with configurable trigger sources and types
● All GPIO pins can be selected as an EXTI trigger source
● Source trigger type includes high level, low level, negative edge, positive edge, or both edge
Individual
interrupt enable, wake-up enable and status bits for each EXTI line
▀
▀ Software interrupt trigger mode for each EXTI line
▀ Integrated deglitch filter for short pulse blocking
Rev. 1.00
199 of 628
August 13, 2012
External Interrupt/Event Controller (EXTI)
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate
a wake-up event or interrupt requests independently. In interrupt mode there are five trigger types
which can be selected as the external interrupt trigger type, low level, high level, negative edge,
positive edge and both edges, selectable using the SRCnTYPE field in the EXTICFGRn register. In
the wake-up event mode, the wake-up event polarity can be configured by setting the EXTInPOL
field in the EXTIWAKUPPOLR register. If the EVWUPIEN bit in the EXTIWAKUPCR Register
is set, the EVWUP interrupt can be generated when the associated wake-up event occurs and the
corresponding EXTI wake-up enable bit is set. Each EXTI line can also be masked independently.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Functional Descriptions
Wake-up Event Management
EXTIn
16
16
1
0
16
16
High / Low
level Detector
16
EXTInWFL
16
EVWUP Interrupt
(NVIC)
16
EXTInPOL
EXTInWEN
EVWUPIEN
16
RTC
16
HSI/HSE/PLL
Wakeup (CKCU)
16
RTC_WAKEUP
Set Event
(NVIC)
PWRCU
LVD_WAKEUP
WAKEUP
WUPF
EXTI Wakeup Event
Management
SLEEPING
(NVIC)
Figure 23. EXTI Wake-up Event Management
External Interrupt/Event Line Mapping
All GPIO pins can be selected as EXTI trigger sources by configuring the EXTInPIN [3:0] field in the
AFIO ESSRn register to trigger an interrupt or event. Refer to the AFIO section for more details.
Interrupt and Debounce
The application software can set the DBnEN bit in the EXTIn Interrupt Configuration Register
EXTICFGRn to enable the corresponding pin de-bounce function and configure the DBnCNT field
in the EXTICFGRn so as to select an appropriate de-bounce time for specific applications. The
interrupt signal will however be delayed due to the de-bounce function. When the device is woken
up from the power saving mode by an external interrupt, an interrupt request will be generated by
the EXTI wake-up flag. After the device has been woken up and the clock has recovered, the EXTI
wake-up flag that was triggered by the EXTI line must be read and then cleared by application
software. The accompanying diagram shows the relationship between the EXTI input signal and
the EXTI interrupt/event request signal.
Rev. 1.00
200 of 628
August 13, 2012
External Interrupt/Event Controller (EXTI)
In order to wake-up the system from the power saving mode, the EXTI controller provides a function
which can monitor external events and send them to the CortexTM-M3 core and the Clock Control
Unit, CKCU. These external events include EXTI events, Low Voltage Detection, WAKEUP input
pin and RTC wake-up functions. By configuring the wake-up event enable bit in the corresponding
peripheral, the wake-up signal will be sent to the CortexTM-M3 and the CKCU via the EXTI controller
when the corresponding wake-up event occurs. Additionally, the software can enable the event wakeup interrupt function by setting the EVWUPIEN bit in the EXTIWAKUPCR register and the EXTI
controller will then assert an interrupt when the wake-up event occurs.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Input pulse is shorter
than debounce time
Debounce
time delay
EXTIn input
No request signal
is generated
Figure 24. EXTI Debounce Function
Register Map
The following table shows the EXTI registers and reset values.
Table 25. EXTI Register Map
Register
Offset
Description
Reset Value
EXTI Base Address=0x4002_4000
EXTICFGR0
0x000
EXTI Interrupt 0 Configuration Register
0x0000_0000
EXTICFGR1
0x004
EXTI Interrupt 1 Configuration Register
0x0000_0000
EXTICFGR2
0x008
EXTI Interrupt 2 Configuration Register
0x0000_0000
EXTICFGR3
0x00C
EXTI Interrupt 3 Configuration Register
0x0000_0000
EXTICFGR4
0x010
EXTI Interrupt 4 Configuration Register
0x0000_0000
EXTICFGR5
0x014
EXTI Interrupt 5 Configuration Register
0x0000_0000
EXTICFGR6
0x018
EXTI Interrupt 6 Configuration Register
0x0000_0000
EXTICFGR7
0x01C
EXTI Interrupt 7 Configuration Register
0x0000_0000
EXTICFGR8
0x020
EXTI Interrupt 8 Configuration Register
0x0000_0000
EXTICFGR9
0x024
EXTI Interrupt 9 Configuration Register
0x0000_0000
EXTICFGR10
0x028
EXTI Interrupt 10 Configuration Register
0x0000_0000
EXTICFGR11
0x02C
EXTI Interrupt 11 Configuration Register
0x0000_0000
EXTICFGR12
0x030
EXTI Interrupt 12 Configuration Register
0x0000_0000
EXTICFGR13
0x034
EXTI Interrupt 13 Configuration Register
0x0000_0000
EXTICFGR14
0x038
EXTI Interrupt 14 Configuration Register
0x0000_0000
EXTICFGR15
0x03C
EXTI Interrupt 15 Configuration Register
0x0000_0000
EXTICR
0x040
EXTI Interrupt Control Register
0x0000_0000
EXTIEDGEFLGR
0x044
EXTI Interrupt Edge Flag Register
0x0000_0000
EXTIEDGESR
0x048
EXTI Interrupt Edge Status Register
0x0000_0000
EXTISSCR
0x04C
EXTI Interrupt Software Set Command Register
0x0000_0000
EXTIWAKUPCR
0x050
EXTI Interrupt Wake-up Control Register
0x0000_0000
EXTIWAKUPPOLR 0x054
EXTI Interrupt Wake-up Polarity Register
0x0000_0000
EXTIWAKUPFLG
EXTI Interrupt Wake-up Flag Register
0x0000_0000
Rev. 1.00
0x058
201 of 628
August 13, 2012
External Interrupt/Event Controller (EXTI)
EXTIn interrupt
request signal
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
EXTI Interrupt Configuration Register n – EXTICFGRn, n=0~15
This register is used to specify the debounce function and select the trigger type.
Offset:
0x000 (EXTICFGR0)~0x03C (EXTICFGR15)
Reset value: 0x0000_0000
30
29
DBnEN
Type/Reset
RW
0
23
28
27
26
25
SRCnTYPE
RW
0
RW
22
24
DBnCNT
0
RW
21
0
20
RW
0
19
RW
0
18
RW
0
17
RW
0
16
DBnCNT
Type/Reset
RW
0
15
RW
0
RW
14
0
RW
13
0
12
RW
0
11
RW
0
10
RW
0
9
RW
0
8
DBnCNT
Type/Reset
RW
0
7
RW
0
RW
6
0
RW
5
0
4
RW
0
RW
3
0
2
RW
0
1
RW
0
0
DBnCNT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[31]
DBnEN
EXTIn De-bounce Circuit Enable Bit (n=0~15)
0: De-bounce circuit disabled
1: De-bounce circuit enabled
[30:28]
SRCnTYPE EXTIn Interrupt Source Trigger Type (n=0~15)
SRCnTYPE [2:0]
[27:0]
Rev. 1.00
DBnCNT
RW
0
RW
0
RW
0
Interrupt Source Type
0
0
0
Low-level Sensitive
0
0
1
High-level Sensitive
0
1
0
Negative-edge Triggered
0
1
1
Positive-edge Triggered
1
X
X
Both-edge Triggered
EXTIn De-bounce Counter (n=0~15)
The de-bounce time is calculated with DBnCNT x APB clock period and should be
long enough to take effect on the input signal.
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August 13, 2012
External Interrupt/Event Controller (EXTI)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Interrupt Control Register – EXTICR
This register is used to control the EXTI interrupt.
Offset:
0x040
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN
Type/Reset
RW
0
7
RW
0
RW
6
EXTI7EN
Type/Reset
RW
0
5
EXTI6EN
RW
0
0
0
4
EXTI5EN
RW
RW
0
0
Bits
Field
Descriptions
[15:0]
EXTInEN
EXTIn Interrupt Enable Bit (n=0~15)
0: EXTI line n interrupt disabled
1: EXTI line n interrupt enabled
Rev. 1.00
0
3
EXTI4EN
RW
RW
203 of 628
0
2
EXTI3EN
RW
RW
0
RW
0
1
EXTI2EN
RW
EXTI9EN
0
RW
0
0
EXTI1EN
RW
EXTI8EN
0
EXTI0EN
RW
0
August 13, 2012
External Interrupt/Event Controller (EXTI)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR
This register is used to indicate if an EXTI edge has been detected.
Offset:
0x044
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF
Type/Reset
WC
0
7
WC
0
WC
6
0
5
WC
0
4
WC
0
3
WC
0
2
WC
0
1
WC
0
0
EXTI7EDF EXTI6EDF EXTI5EDF EXTI4EDF EXTI3EDF EXTI2EDF EXTI1EDF EXTI0EDF
Type/Reset
WC
0
WC
0
WC
0
WC
0
WC
0
WC
0
WC
0
WC
0
Bits
Field
Descriptions
[15:0]
EXTInEDF
EXTIn Edge Detection Flag (n=0~15)
0: No edge is detected
1: Positive or negative edge is detected
This bit is set by the hardware circuitry when a positive or negative edge is detected
on the corresponding EXTI line. Software should write 1 to clear it.
Rev. 1.00
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August 13, 2012
External Interrupt/Event Controller (EXTI)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Interrupt Edge Status Register – EXTIEDGESR
This register indicates the polarity of a detected EXTI edge.
Offset:
0x048
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS
Type/Reset
WC
0
7
WC
0
WC
6
0
5
WC
0
4
WC
0
3
WC
0
2
WC
0
1
WC
0
0
EXTI7EDS EXTI6EDS EXTI5EDS EXTI4EDS EXTI3EDS EXTI2EDS EXTI1EDS EXTI0EDS
Type/Reset
WC
0
WC
0
WC
0
WC
0
Bits
Field
Descriptions
[15:0]
EXTInEDS
EXTIn Edge Detection Status (n=0~15)
0: Negative edge detected
1: Positive edge detected
Software should write 1 to clear it.
Rev. 1.00
205 of 628
WC
0
WC
0
WC
0
WC
0
August 13, 2012
External Interrupt/Event Controller (EXTI)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Interrupt Software Set Command Register – EXTISSCR
This register is used to activate the EXTI interrupt.
Offset:
0x04C
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
EXTI15SC EXTI14SC EXTI13SC EXTI12SC EXTI11SC EXTI10SC
Type/Reset
RW
0
7
RW
0
6
EXTI7SC
Type/Reset
RW
0
0
5
EXTI6SC
RW
RW
0
0
4
EXTI5SC
RW
RW
0
0
RW
Field
Descriptions
[15:0]
EXTInSC
EXTIn Software Set Command (n=0~15)
0: Deactivates the EXTIn interrupt
1: Activates the EXTIn interrupt
206 of 628
RW
0
2
EXTI3SC
Bits
Rev. 1.00
0
3
EXTI4SC
RW
RW
0
RW
0
1
EXTI2SC
RW
EXTI9SC
0
RW
0
0
EXTI1SC
RW
EXTI8SC
0
EXTI0SC
RW
0
August 13, 2012
External Interrupt/Event Controller (EXTI)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Interrupt Wake-up Control Register – EXTIWAKUPCR
This register is used to control the EXTI interrupt and wake-up function.
Offset:
0x050
Reset value: 0x0000_0000
31
30
29
28
27
RW
25
24
18
17
16
10
9
8
Reserved
0
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
RW
4
0
3
RW
0
2
RW
0
1
RW
0
0
EXTI7WEN EXTI6WEN EXTI5WEN EXTI4WEN EXTI3WEN EXTI2WEN EXTI1WEN EXTI0WEN
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
[31]
EVWUPIEN EXTI Event Wake-up Interrupt Enable Bit
0: EVWUP interrupt disabled
1: EVWUP interrupt enabled
[15:0]
EXTInWEN
Rev. 1.00
0
RW
0
RW
0
RW
0
Descriptions
EXTIn Wake-up Enable Bit (n=0~15)
0: EXTIn wake-up disabled
1: EXTIn wake-up enabled
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August 13, 2012
External Interrupt/Event Controller (EXTI)
EVWUPIEN
Type/Reset
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Interrupt Wake-up Polarity Register – EXTIWAKUPPOLR
This register is used to select the EXTI line interrupt wake-up polarity.
Offset:
0x054
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
EXTI15POL EXTI14POL EXTI13POL EXTI12POL EXTI11POL EXTI10POL EXTI9POL EXTI8POL
Type/Reset
RW
0
7
RW
0
RW
6
0
5
RW
0
RW
4
0
3
RW
0
2
RW
0
1
RW
0
0
EXTI7POL EXTI6POL EXTI5POL EXTI4POL EXTI3POL EXTI2POL EXTI1POL EXTI0POL
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[15:0]
EXTInPOL
EXTIn Wake-up Polarity (n=0~15)
0: EXTIn wake-up is high level active
1: EXTIn wake-up is low level active
Rev. 1.00
208 of 628
0
RW
0
RW
0
RW
0
August 13, 2012
External Interrupt/Event Controller (EXTI)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
EXTI Interrupt Wake-up Flag Register – EXTIWAKUPFLG
This register indicates if the system has been woken up by the EXTI line.
Offset:
0x058
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
EXTI15WFL EXTI14WFL EXTI13WFL EXTI12WFL EXTI11WFL EXTI10WFL EXTI9WFL EXIT8WFL
Type/Reset
WC
0
7
WC
0
WC
6
0
5
WC
0
4
WC
0
3
WC
0
2
WC
0
1
WC
0
0
EXTI7WFL EXTI6WFL EXTI5WFL EXTI4WFL EXTI3WFL EXTI2WFL EXTI1WFL EXTI0WFL
Type/Reset
WC
0
WC
0
WC
0
WC
0
Bits
Field
Descriptions
[15:0]
EXTInWFL
EXTIn Wake-up Flag (n=0~15)
0: No wake-up occurs
1: System is woken up by EXTIn
Software should write 1 to clear it.
Rev. 1.00
209 of 628
WC
0
WC
0
WC 0
WC
0
August 13, 2012
External Interrupt/Event Controller (EXTI)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
12
Analog to Digital Converter (ADC)
Introduction
EXTI[15:0]
MTO
CH0O
CH1O
CH2O
CH3O
ADnSC
ADCTSR[31:0]
Start Trigger
(Regular)
ADCTCR[2:0]
From ADC Prescaler
ADC_IN0
ADC_IN1
.
.
A/D Converter
GPIO
Regular
groups
ADC_INn
Regular DATA Register
( n x 16 bits)
VDDA
VREF+
VREFVSSA
VSS33
VLDOOUT
Address/data bus
Analog Watchdog
High Threshold (12 bits)
PDMA Request
(* It is only available for PDMA device)
Low Threshold (12 bits)
Analog Watchdog Event
EOC of Regular
Analog Watchdog
Interrupt
EOC
Interrupt
Generator
ADC Interrupt to
NVIC
Figure 25. ADC Block Diagram
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are a total
of 10 multiplexed channels including 8 external channels on which the external analog signal can
be measured and 2 internal channels. If the input voltage is required to remain within a specific
threshold window, the Analog Watchdog function will monitor and detect the signal. An interrupt
will then be generated to inform that the input voltage is higher or lower than the set thresholds.
There are three conversion modes to convert an analog signal to digital data. The A/D converter
can be operated in one shot, continuous and discontinuous conversion mode. A right-aligned 16-bit
data register is provided to store the data after conversion.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Features
Rev. 1.00
211 of 628
Analog to Digital Converter (ADC)
▀ 12-bit SAR ADC engine
▀ Up to 1 MSPS conversion rate
● 1μs at 56MHz, 1.17μs at 72MHz
▀ 8 external analog input channels
▀ 2 internal reference voltage detect analog input channel – VSSA and VDDA
▀ Individual programmable sampling time for each channel
▀ Three conversion modes
● One shot conversion mode
● Continuous conversion mode
● Discontinuous conversion mode
Up
to 8 dedicated sequencer and data registers for conversion
▀
● Data format: unsigned right-aligned format
Analog
watchdog for predefined voltage range monitor
▀
● Lower/upper threshold register
● Interrupt generation
▀ Various trigger start source for conversion modes
● Software trigger
● EXTI – external interrupt input pin
● GPTM or MCTM trigger output – MTO and PWM CHnO
● BFTM trigger
▀ Multiple generated interrupts
● Single conversion end
● Subgroup conversion end
● Cycle conversion end
● Analog Watchdog
● Data register overwrite
PDMA
request on end of conversion occurrence
▀
August 13, 2012
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Functional Description
ADC Clock Setup
The ADC clock, CK_ADC, is provided by the Clock Controller which is synchronous with the
APB clock known as PCLK. Refer to the Clock Control Unit chapter for more details.
Channel Selection
A regular group is composed of up to 8 conversions. The selected channels of the regular group
conversion can be specified in the ADCLST0~ADCLST1 registers. The total conversion sequence
length is setup using the ADSEQL [2:0] bits in the ADCCONV register.
Modifying the ADCCONV register during a conversion process will reset the current conversion,
after which a new start pulse is required to restart a new conversion.
Conversion Mode
The A/D has three operating conversion modes. The conversion modes are One Shot Conversion
Mode, Continuous Conversion Mode and Discontinuous Conversion mode. Details are provided later.
Rev. 1.00
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Analog to Digital Converter (ADC)
The A/D converter supports 8 multiplexed channels and organizes the conversion results into the
regular group. A regular group can organize a conversions sequence which can be implemented on
the channel arranged in a specific conversion sequence length from 1 to 8. For example, conversion
can be carried out with the following channel sequence: CH2, CH4, CH7, CH5, CH6, CH3, CH1
and CH0 one after another.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
One Shot Conversion Mode
In one shot conversion mode, the A/D Converter will perform conversion cycles on the channels
specified in the A/D conversion list registers ADCLSTn with a specific sequence when an A/D
converter event occurs. When the A/D conversion mode field ADMODE [1:0] is set to 0x0, the
A/D converter will operate in the One Shot Conversion Mode. This mode can be started by a
software trigger, an external EXTI event or a TM event determined by the Trigger Control Register
ADCTCR and the Trigger Source Register ADCTSR.
One Shot Conversion Mode
(ex: Sequence Length=8)
Cycle
Cycle
CH2
CH4
CH7
CH5
CH6
CH3
CH0
CH1
CH2
CH4
CH7
CH5
CH6
Start of
Conversion
Single sample
End of
Conversion
Cycle End of
Conversion
Figure 26. One Shot Conversion Mode
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
▀ The converted data will be stored in the 16-bit ADCDRn (n=0~7) registers.
▀ The ADC regular single sample end of conversion event raw status flag, ADIRAWS, in the
ADCIRAW register will be set when the single sample conversion is finished.
▀ An interrupt will be generated after a single sample end of conversion if the ADIMS bit in the
ADCIMR register is not masked.
An
interrupt will be generated after a regular group cycle end of conversion if the ADIMC bit in
▀
the ADCIMR register is not masked.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Continuous Conversion Mode
In Continuous Conversion Mode, repeat conversion cycle will start automatically without requiring
additional A/D start trigger signals after a channel group conversion has completed. When the
A/D conversion mode field ADMODE [1:0] is set to 0x2, the A/D converter will operate in the
Continuous Conversion Mode which can be started by a software trigger, an external EXTI event
or a TM event determined by the Trigger Control Register ADCTCR and the Trigger Source
Register ADCTSR.
▀ The converted data will be stored in the 16-bit ADCDRn (n=0~7) registers.
▀ The ADC regular group cycle end of conversion event raw status flag, ADIRAWC, in the
ADCIRAW register will be set when the conversion cycle is finished.
▀ An interrupt will be generated after a single sample end of conversion if the ADIMS bit in the
ADCIMR register is not masked.
An
interrupt will be generated after a regular group cycle end of conversion if the ADIMC bit in
▀
the ADCIMR register is not masked.
Continuous Conversion Mode
(ex: Sequence Length=8)
Cycle
Cycle
CH2
CH5
CH4
CH7
CH7
CH5
CH6
CH6
CH2
CH5
CH4
CH7
CH7
CH5
Start of
Conversion
Single sample
End of
Conversion
Cycle End of
Conversion
Figure 27. Continuous Conversion Mode
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
After each conversion:
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
In the Discontinuous Conversion Mode, the A/D Converter will start to convert the next n
conversions where the number n is the subgroup length defined by the ADSUBL field. When a
trigger event occurs, the channels to be converted with a specific sequence are specified in the
ADCLSTn registers. After n conversions have completed, the regular subgroup EOC interrupt
raw flag ADIRAWG in the ADCIRAW register will be asserted. The A/D converter will now not
continue to perform the next n conversions until the next trigger event occurs. The conversion
cycle will end after all the regular group channels, of which the total number is defined by the
ADSEQL [2:0] bits in the ADCCONV register, have finished their conversion, at which point the
regular cycle EOC interrupt raw flag ADIRAWC in the ADCIRAW register will be asserted. If a
new trigger event occurs after all the subgroup channels have all been converted, i.e., a complete
conversion cycle has been finished, the conversion will restart from the first subgroup.
Example:
▀ A/D subgroup length=3 (ADSUBL=2) and sequence length=8 (ADSEQL=7), channels to be
converted=2, 4, 7, 5, 6, 3, 0 and 1 – specific converting sequence as defined in the ADCLSTn
registers.
● Trigger 1: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG
flag being asserted after subgroup EOC.
● Trigger 2: subgroup channels to be converted are CH5, CH6 and CH3 with the ADIRAWG
flag being asserted after subgroup EOC.
● Trigger 3: subgroup channels to be converted are CH0 and CH1 with the ADIRAWG flag
being asserted after subgroup EOC. Also a Cycle end of conversion (EOC) interrupt raw flag
ADIRAWC will be asserted.
● Trigger 4: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG
flag being asserted – conversion sequence restarts from the beginning.
Discontinuous Conversion Mode
(ex: Sequence Length=8, Subgroup Length=3 )
CH2
CH4
CH7
Subgroup 0
Cycle
Cycle
CH5
CH6
CH3
Subgroup 1
CH0
CH1
Subgroup 2
CH2
CH4
CH7
Subgroup 0
Start of
Conversion
Single sample
End of
Conversion
Subgroup End
of Conversion
Cycle End of
Conversion
Figure 28. Discontinuous Conversion Mode
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
Discontinuous Conversion Mode
The A/D converter will operate in the Discontinuous Conversion Mode for regular groups when the
A/D conversion mode bit field ADMODE [1:0] in the ADCCONV register is set to 0x3. The regular
group to be converted can have up to 8 channels and can be arranged in a specific sequence by
configuring the ADCLSTn registers where n ranges from 0 to 1. This mode is provided to convert
data for the regular group with a short sequence, named as the A/D regular conversion subgroup,
each time a trigger event occurs. The subgroup length is defined in the ADSUBL [2:0] field to
specify the subgroup length. In the Discontinuous Conversion Mode the A/D converter can be
started by a software trigger, an external EXTI event or a TM event for regular groups determined
by the Trigger Control Register ADCTCR and the Trigger Source Register ADCTSR.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Start Conversion Trigger Sources
Data conversion can be initiated by a software trigger, a General-Purpose Timer Module (GPTM)
event, a Motor Control Timer Module (MCTM) event, a Basic Function Timer Module (BFTM)
event or an external trigger. Each trigger source can be enabled by setting the corresponding enable
control bit in the ADCTCR register and then selected by configuring the associated selection bits in
the ADCTSR register to start a group channel conversion.
The A/D converter can also be triggered to start a regular channel conversion by a TM event. The
TM events include a GPTM or MCTM master trigger output MTO, four GPTM or MCTM channel
outputs CH0~CH3 and a BFTM trigger output. If the corresponding TM trigger enable bit is set to 1
and the trigger output or the TM channel event is selected via the relevant TM event selection bits, the
A/D converter will start a conversion when a rising edge of the selected trigger event occurs.
In addition to the internal trigger sources, the A/D converter can be triggered to start a conversion
by an external trigger event. The external trigger event is derived from the external lines EXTIn.
If the external trigger enable bit ADEXTI is set to 1 and the corresponding EXTI line is selected
by configuring the ADEXTIS for regular group, the A/D converter will start a conversion when an
EXTI line rising edge occurs.
Sampling Time Setting
Each conversion channel can be sampled with a different sampling time. By modifying the
ADSTn [7:0] bits in the ADCSTRn (n=0~7) registers, the sampling time of the analog input signal
can be determined.
The total conversion time (Tconv) is calculated using the following formula:
Tconv=TSampling + TLatency
Where the minimum sampling time TSampling=1.5 cycles (when ADST [7:0]=0) and the minimum
channel conversion latency TLatency=12.5 cycles.
Example:
With the A/D Converter clock CK_ADC=14MHz and a sampling time=1.5 cycles:
Tconv=1.5 + 12.5=14 cycles=1μs
Data Alignment
The ADC converted result has a right aligned and unsigned output format as follows:
"0000_d11_d10_d9_d8_d7_d6_d5_d4_d3_d2_d1_d0".
If it is required to turn off the A/D converter, the A/D clock enable bit ADCEN should be cleared
to 0 for at least two A/D clock cycles to disable the A/D converter function.
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
An A/D converter conversion can be started by setting the software trigger bit, ADSC, in the
ADCTSR register for the regular group channel when the software trigger enable bit, ADSW, in
the ADCTCR register is set to 1. After the A/D converter starts converting the analog data, the
corresponding enable bit ADSC will be cleared to 0 automatically.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Analog Watchdog
Interrupts
When an A/D conversion is completed, an End of Conversion EOC event will occur. There are
three kinds of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC
for A/D conversion. A single sample EOC event will occur and the single sample EOC interrupt
raw flag, ADIRAWS bits in the ADCIRAW register, will be asserted when a single channel
conversion has completed. A subgroup EOC event will occur and the subgroup EOC interrupt
raw flag, ADIRAWG in the ADCIRAW register, will be asserted when a subgroup conversion has
completed. A cycle EOC event will occur and the cycle EOC interrupt raw flag, ADIRAWC bits in
the ADCIRAW register, will be asserted when a cycle conversion is finished. When a single sample
EOC, a subgroup EOC or a cycle EOC raw flag is asserted and the corresponding interrupt enable
bit, ADIMC, ADIMG or ADIMS bit in the ADCIMR register, is set to 1, the associated interrupt
will be generated.
After a conversion has completed, the 12-bit digital data will be stored in the associated ADCDRn
register and the value of the data valid flag named as ADVLDn will be changed from low to high.
The converted data should be read by the application program, after which the data valid flag
ADVLDn will be automatically changed from high to low. Otherwise, a data overwrite event will
occur and the data overwrite interrupt raw flag ADIRAWO bit in the ADCIRAW register will be
asserted. When the related data overwrite raw flag is asserted, the data overwrite interrupt will be
generated if the interrupt enable bit ADIMO in the ADCIMR register is set to 1.
If the A/D watchdog monitor function is enabled and the data after a channel conversion is less than
the lower threshold or higher than the upper threshold, the watchdog lower or upper threshold interrupt
raw flag ADIRAWL or ADIRAWU in the ADCIRAW register will be asserted. When the ADIRAWL
or ADIRAWU flag is asserted and the corresponding interrupt enable bit, ADIML or ADIMU in the
ADCIMR register, is set a watchdog lower or upper threshold interrupt will be generated.
The A/D Converter interrupt clear bits are used to clear the associated A/D converter interrupt
raw and masked status bits. Writing 1 into the specific A/D converter interrupt clear bit in the A/D
converter interrupt clear register ADCICLR will clear the corresponding A/D converter interrupt
raw and masked status bits. These bits are automatically cleared to 0 by hardware after being set to 1.
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
The A/D converter includes a watchdog function to monitor the converted data. There are two
kinds of thresholds for the watchdog monitor function, known as the watchdog upper threshold
and watchdog lower threshold, which are specified in the Watchdog Upper and Lower Threshold
Registers respectively. The watchdog monitor function is enabled by setting the watchdog upper and
lower threshold monitor function enable bits, ADWUE and ADWLE, in the watchdog control register
ADCWCR. The channel to be monitored can be specified by configuring the ADWCH and ADWALL
bits. When the converted data is less or higher than the lower or upper threshold, as defined in the
ADCLTR or ADCUTR registers respectively, the watchdog lower or upper threshold interrupt raw
flags, ADIRAWL or ADIRAWU in the ADCIRAW register, will be asserted if the watchdog lower
or upper threshold monitor function is enabled. If the lower or upper threshold interrupt raw flag
is asserted and the corresponding interrupt is enabled by setting the ADIML or ADIMU bit in the
ADCIME register, the A/D watchdog lower or upper threshold interrupt will be generated.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
PDMA Request
The converted channel value will be stored in the corresponding data register. The A/D Converter
can inform the MCU using the A/D Converter EOC interrupt if a new conversion data is already
stored in the ADCDRn register. Users also can determine the PDMA request is asserted by setting
the ADDMAC, ADDMAG or ADDMAS bits in the ADCDMAR register. A PDMA request will
be automatically generated at the end of each ADC conversion. The detail description will be
introduced in the ADCDMAR register description.
The following table shows the A/D Converter registers and reset values.
Table 26. A/D Converter Register Map
Register
Offset
Description
Reset Value
ADC Base Address=0x4001_0000
ADCRST
0x004
ADC Reset Register
0x0000_0000
ADCCONV
0x008
ADC Regular Conversion Mode Register
0x0000_0000
ADCLST0
0x010
ADC Regular Conversion List Register 0
0x0000_0000
ADCLST1
0x014
ADC Regular Conversion List Register 1
0x0000_0000
ADCOFR0
0x030
ADC Input 0 Offset Register
0x0000_0000
ADCOFR1
0x034
ADC Input 1 Offset Register
0x0000_0000
ADCOFR2
0x038
ADC Input 2 Offset Register
0x0000_0000
ADCOFR3
0x03C
ADC Input 3 Offset Register
0x0000_0000
ADCOFR4
0x040
ADC Input 4 Offset Register
0x0000_0000
ADCOFR5
0x044
ADC Input 5 Offset Register
0x0000_0000
ADCOFR6
0x048
ADC Input 6 Offset Register
0x0000_0000
ADCOFR7
0x04C
ADC Input 7 Offset Register
0x0000_0000
ADCSTR0
0x070
ADC Input 0 Sampling Time Register
0x0000_0000
ADCSTR1
0x074
ADC Input 1 Sampling Time Register
0x0000_0000
ADCSTR2
0x078
ADC Input 2 Sampling Time Register
0x0000_0000
ADCSTR3
0x07C
ADC Input 3 Sampling Time Register
0x0000_0000
ADCSTR4
0x080
ADC Input 4 Sampling Time Register
0x0000_0000
ADCSTR5
0x084
ADC Input 5 Sampling Time Register
0x0000_0000
ADCSTR6
0x088
ADC Input 6 Sampling Time Register
0x0000_0000
ADCSTR7
0x08C
ADC Input 7 Sampling Time Register
0x0000_0000
ADCDR0
0x0B0
ADC Regular Conversion Data Register 0
0x0000_0000
ADCDR1
0x0B4
ADC Regular Conversion Data Register 1
0x0000_0000
ADCDR2
0x0B8
ADC Regular Conversion Data Register 2
0x0000_0000
ADCDR3
0x0BC
ADC Regular Conversion Data Register 3
0x0000_0000
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
Register Map
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register
Offset
Description
Reset Value
0x0C0
ADC Regular Conversion Data Register 4
0x0000_0000
ADCDR5
0x0C4
ADC Regular Conversion Data Register 5
0x0000_0000
ADCDR6
0x0C8
ADC Regular Conversion Data Register 6
0x0000_0000
ADCDR7
0x0CC
ADC Regular Conversion Data Register 7
0x0000_0000
ADCTCR
0x100
ADC Regular Trigger Control Register
0x0000_0000
ADCTSR
0x104
ADC Regular Trigger Source Register
0x0000_0000
ADCWCR
0x120
ADC Watchdog Control Register
0x0000_0000
ADCLTR
0x124
ADC Watchdog Lower Threshold Register
0x0000_0000
ADCUTR
0x128
ADC Watchdog Upper Threshold Register
0x0000_0000
ADCIMR
0x130
ADC Interrupt Mask Enable register
0x0000_0000
ADCIRAW
0x134
ADC Interrupt Raw Status Register
0x0000_0000
ADCIMASK
0x138
ADC Interrupt Masked Status Register
0x0000_0000
ADCICLR
0x13C
ADC Interrupt Clear Register
0x0000_0000
ADCDMAR
0x140
ADC PDMA Request Register
0x0000_0000
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
ADCDR4
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
ADC Reset Register – ADCRST
This register is used to reset the A/D Converter by software.
Offset:
0x004
Reset value: 0x0000_0000
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
RW
Bits
Field
Descriptions
[0]
ADRST
ADC Software Reset
0: No reset
1: Reset A/D converter except for the A/D Converter registers
Rev. 1.00
ADRST
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0
August 13, 2012
Analog to Digital Converter (ADC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Regular Conversion Mode Register – ADCCONV
This register specifies the mode setting, sequence length and subgroup length of A/D Converter regular
group conversion. Note that once the contents of the ADCCONV register have changed, any regular
conversion presently in progress will be aborted and the A/D Converter will be reset. The application
program has to wait for at least one A/D converter clock CK_ADC before issuing the next command.
Offset:
0x008
Reset value: 0x0000_0000
30
29
28
27
26
25
24
18
17
16
Reserved
Type/Reset
23
22
21
20
19
Reserved
ADSUBL
Type/Reset
RW
15
14
13
12
11
0
10
RW
0
8
ADSEQL
RW
6
0
9
Reserved
Type/Reset
7
RW
5
4
3
0
RW
2
0
1
0
0
Reserved
Type/Reset
RW
ADMODE
RW
0
RW
0
Bits
Field
Descriptions
[18:16]
ADSUBL[2:0]
A/D Converter Regular Conversion Subgroup Length
The ADSUBL field specifies the conversion channel length of each subgroup for the
regular group in the discontinuous mode. The subgroup length is equal to ADSUB
value plus 1. If the regular sequence length is not a multiple of the regular subgroup
length, the last subgroup will be the rest of the regular group channels that have not
been converted.
[10:8]
ADSEQL[2:0]
A/D Converter Regular Conversion Sequence Length
The ADSEQL field specifies the conversion length of the whole sequence for the
regular group. The sequence length is equal to the ADSEQL value plus 1.
[1:0]
ADMODE
A/D Converter Regular Conversion Mode
Regular channels for the whole sequence continuously until the conversion mode is
changed.
ADMODE [1:0]
00
One shot mode
01
Reserved
10
11
Rev. 1.00
Mode
Descriptions
After a start trigger, the conversion will be
executed on the whole sequence of the
regular channels once.
—
Continuous mode
After a start trigger, the conversion will be
executed on the regular channels for the
whole sequence continuously until the
conversion mode is changed.
Discontinuous mode
After a start trigger, the conversion will be
executed on the current regular subgroup.
When the last subgroup is finished, the
conversion restarts from the first subgroup.
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Analog to Digital Converter (ADC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Regular Conversion List Register 0 – ADCLST0
This register specifies the conversion sequence order No.0~No.3 of the A/D Converter regular group.
Offset:
0x010
Reset value: 0x0000_0000
31
30
29
28
27
26
ADSEQ3
Type/Reset
RW
23
22
21
0
20
RW
0
19
13
0
12
RW
0
11
5
0
4
RW
0
3
Rev. 1.00
RW
0
RW
0
16
RW
0
9
RW
0
2
Reserved
Type/Reset
0
RW
0
8
ADSEQ1
RW
6
RW
17
10
Reserved
Type/Reset
7
0
ADSEQ2
RW
14
RW
18
Reserved
Type/Reset
15
24
RW
0
1
RW
0
0
ADSEQ0
RW
0
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RW
0
RW
0
RW
0
RW
0
August 13, 2012
Analog to Digital Converter (ADC)
Reserved
25
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[28:24]
ADSEQ3
A/D Converter Regular Conversion Sequence No.3
Define the A/D Converter input channel order No.3 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may cause
abnormal ADC operation
[20:16]
ADSEQ2
A/D Converter Regular Conversion Sequence No.2
Define the A/D Converter input channel order No.2 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may cause
abnormal ADC operation
[12:8]
ADSEQ1
A/D Converter Regular Conversion Sequence No.1
Define the A/D Converter input channel order No.1 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may cause
abnormal ADC operation
[4:0]
ADSEQ0
A/D Converter Regular Conversion Sequence No.0
Define the A/D Converter input channel order No.0 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may cause
abnormal ADC operation
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Regular Conversion List Register 1 – ADCLST1
This register specifies the conversion sequence order No.4~No.7 of the A/D Converter regular group.
Offset:
0x014
Reset value: 0x0000_0000
31
30
29
28
27
26
ADSEQ7
Type/Reset
RW
23
22
21
0
20
RW
0
19
13
0
12
RW
0
11
5
0
4
RW
0
3
Rev. 1.00
RW
0
RW
0
16
RW
0
9
RW
0
2
Reserved
Type/Reset
0
RW
0
8
ADSEQ5
RW
6
RW
17
10
Reserved
Type/Reset
7
0
ADSEQ6
RW
14
RW
18
Reserved
Type/Reset
15
24
RW
0
1
RW
0
0
ADSEQ4
RW
0
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RW
0
RW
0
RW
0
RW
0
August 13, 2012
Analog to Digital Converter (ADC)
Reserved
25
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[28:24]
ADSEQ7
A/D Converter Regular Conversion Sequence No.7
Define the A/D Converter input channel order No.7 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may
cause abnormal ADC operation
[20:16]
ADSEQ6
A/D Converter Regular Conversion Sequence No.6
Define the A/D Converter input channel order No.6 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may
cause abnormal ADC operation
[12:8]
ADSEQ5
A/D Converter Regular Conversion Sequence No.5
Define the A/D Converter input channel order No.5 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may
cause abnormal ADC operation
[4:0]
ADSEQ4
A/D Converter Regular Conversion Sequence No.4
Define the A/D Converter input channel order No.4 of the regular conversion sequence.
0x00~0x07: ADC_IN0~ADC_IN7
0x08~0x0F: Reserved
0x10: Analog ground, VSSA (VREF-)
0x11: Analog power, VDDA (VREF+)
0x12~0x1F: Invalid setting. These values must not be selected as they may
cause abnormal ADC operation
Rev. 1.00
225 of 628
August 13, 2012
Analog to Digital Converter (ADC)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Input n Offset Register – ADCOFRn, n=0~7
This register specifies the A/D Converter input channel n offset together with the offset cancellation
function enable control.
Offset:
0x030~04C
Reset value: 0x0000_0000
30
29
28
27
26
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
ADOFEn
Type/Reset
RW
12
11
Reserved
ADOFn
0
7
RW
6
5
4
0
3
RW
0
2
RW
0
1
RW
0
0
ADOFn
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[15]
ADOFEn
ADC Input Channel n Offset Cancellation Enable (n=0~7)
0: ADC_INn offset cancellation function disabled
1: ADC_INn offset cancellation function enabled
[11:0]
ADOFn
ADC Input Channel n Offset Value (n=0~7)
This field is used to store the A/D Converter input channel n offset value. If the
offset cancellation function is enabled, the data stored in the corresponding data
register ADCDRn will be the result derived from the raw conversion data from ADC
conversion engine minus the input Channel n offset specified in this field.
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Input Sampling Time Register n – ADCSTRn, n=0~7
This register specifies the sampling time of A/D Converter channel n.
Offset:
0x070~08C
Reset value: 0x0000_0000 (0x0000_0002) Note
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
ADSTn
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[7:0]
ADSTn
A/D Converter Input Channel n Sampling Time (n=0~7)
Sampling time=(ADSTn [7:0] + 1.5) A/D Conversion clock cycles.
Note: The reset default value of the A/D Converter input channel 5 input sampling
time is 0x02.
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Regular Conversion Data Register n – ADCDRn, n=0~7
This register is used to store the conversion data of the regular conversion sequence No.n.
Offset:
0x0B0~0CC
Reset value: 0x0000_0000
31
30
29
28
27
RC
25
24
18
17
16
10
9
8
Reserved
0
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
ADDn
Type/Reset
RO
0
7
RO
0
RO
6
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
ADDn
Type/Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bits
Field
Descriptions
[31]
ADVLDn
A/D Converter Regular Conversion Data of the sequence No.n Valid Bit (n=0~7)
0: Data is invalid or has been read
1: New data are valid
[15:0]
ADDn
A/D Converter Regular Conversion Data of the sequence No.n (n=0~7)
The regular channel conversion result of the sequence No.n defined in the ADCLST
register.
Rev. 1.00
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August 13, 2012
Analog to Digital Converter (ADC)
ADVLDn
Type/Reset
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Regular Trigger Control Register – ADCTCR
This register contains the A/D start conversion trigger enable bits of the regular conversion.
Offset:
0x100
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
Reserved
3
BFTM
Type/Reset
RW
0
TM
RW
0
ADEXTI
ADSW
RW
RW
0
Bits
Field
Descriptions
[3]
BFTM
A/D Converter Regular Conversion BFTM Event Trigger Enable control
0: Disable regular conversion triggered by BFTM event
1: Enable regular conversion triggered by BFTM event
[2]
TM
A/D Converter Regular Conversion GPTM or MCTM Event Trigger Enable control
0: Disable regular conversion triggered by GPTM or MCTM event
1: Enable regular conversion triggered by GPTM or MCTM event
[1]
ADEXTI
A/D Converter Regular Conversion EXTI Event Trigger Enable control
0: Disable regular conversion triggered by EXTI lines
1: Enable regular conversion triggered by EXTI lines
[0]
ADSW
A/D Converter Regular Conversion Software Trigger Enable control
0: Disable regular conversion triggered by software trigger bit
1: Enable regular conversion triggered by software trigger bit
Rev. 1.00
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0
August 13, 2012
Analog to Digital Converter (ADC)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Regular Trigger Source Register – ADCTSR
This register contains the trigger source selection and the software trigger bit of the regular
conversion.
Offset:
0x104
Reset value: 0x0000_0000
30
29
28
27
26
25
Reserved
TME
Type/Reset
RW
23
22
21
20
Reserved
19
RW
14
13
0
18
12
0
11
5
RW
0
16
0
10
RW
0
9
RW
0
8
ADEXTIS
RW
6
0
TMS
RW
Reserved
Type/Reset
7
RW
17
BFTMS
Type/Reset
15
24
4
3
0
RW
2
0
RW
0
1
RW
0
0
Reserved
ADSC
Type/Reset
RW
0
Bits
Field
Descriptions
[26:24]
TME
GPTM or MCTM Trigger Event Selection of the A/D Converter Regular Conversion
000: GPTM or MCTM MTO rising edge
001: GPTM or MCTM CH0O rising edge
010: GPTM or MCTM CH1O rising edge
011: GPTM or MCTM CH2O rising edge
100: GPTM or MCTM CH3O rising edge
Others: Reserved – Should not be used, otherwise, the conversion results will
be unpredictable
[19]
BFTMS
BFTM Trigger Timer Selection of the A/D Converter Regular Conversion
0: BFTM0
1: BFTM1
[18:16]
TMS
GPTM or MCTM Trigger Timer Selection of the A/D Converter Regular Conversion
000: MCTM
010: GPTM0
011: GPTM1
Others: Reserved – Should not be used, otherwise, the conversion results will
be unpredictable.
[11:8]
ADEXTIS
EXTI Trigger Source Selection of A/D Converter Regular Conversion
0x0: EXTI line 0
0x1: EXTI line 1
…
0xF: EXTI line 15
[0]
ADSC
A/D Converter Regular Conversion Software Trigger Bit
0: No effect
1: Start the regular conversion
This bit is set by software to start the regular conversion manually and then
cleared by hardware automatically at the next A/D Converter clock cycle.
Rev. 1.00
230 of 628
August 13, 2012
Analog to Digital Converter (ADC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Watchdog Control Register – ADCWCR
This register provides the control bits and status of the A/D Converter watchdog function.
Offset:
0x120
Reset value: 0x0000_0000
31
30
29
28
27
26
25
ADUCH
Type/Reset
RO
23
22
21
20
0
19
RO
0
18
13
12
0
11
RO
0
10
5
4
Reserved
3
0
RW
0
2
0
RO
0
8
RW
231 of 628
RW
0
1
ADWALL
Type/Reset
Rev. 1.00
RO
ADWCH
RW
6
0
16
9
Reserved
Type/Reset
7
RO
ADLCH
RO
14
0
17
Reserved
Type/Reset
15
RO
0
RW
0
0
ADWUE
ADWLE
RW
RW
0
0
August 13, 2012
Analog to Digital Converter (ADC)
Reserved
24
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[27:24]
ADUCH
Channel Upper Threshold Status
0000: ADC_IN0 converted data is higher than the threshold ADUT defined in the
ADCUTR register
0001: ADC_IN1 converted data is higher than the threshold ADUT defined in the
ADCUTR register
...
0111: ADC_IN7 converted data is higher than the threshold ADUT defined in the
ADCUTR register
Others: Reserved
If one of these statuses is set to 1 by the watchdog monitor function, the status field
must be stored in the user-defined memory location first in the corresponding ISR.
Otherwise, the ADUCH field will be changed if another channel upper threshold
event occurs.
[19:16]
ADLCH
Channel Lower Threshold Status
0000: ADC_IN0 converted data is lower than the threshold ADLT defined in the
ADCLTR register
0001: ADC_IN1 converted data is lower than the threshold ADLT defined in the
ADCLTR register
...
0111: ADC_IN7 converted data is lower than the threshold ADLT defined in the
ADCLTR register
Others: Reserved
If one of these statuses is set to 1 by the watchdog monitor function, the status field
must be stored in the user-defined memory location first in the corresponding ISR.
Otherwise, the ADLCH field will be changed if another channel lower threshold event
occurs.
[11:8]
ADWCH
A/D Converter Channel Selection for Watchdog function
0000: ADC_IN0 is monitored
0001: ADC_IN1 is monitored
...
0111: ADC_IN7 is monitored
Others: Reserved
[2]
ADWALL
A/D Converter Specific or All Channel control for watchdog function
0: Only the channel specified by the ADWCH field is monitored
1: All channels are monitored
[1]
ADWUE
A/D Converter Watchdog Upper Threshold Monitor Enable Bit
0: Disable the upper threshold monitor function
1: Enable the upper threshold monitor function
[0]
ADWLE
A/D Converter Watchdog Lower Threshold Monitor Enable Bit
0: Disable the lower threshold monitor function
1: Enable the lower threshold monitor function
Rev. 1.00
232 of 628
August 13, 2012
Analog to Digital Converter (ADC)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Watchdog Lower Threshold Register – ADCLTR
This register specifies the lower threshold of the A/D Converter watchdog function.
Offset:
0x124
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
ADLT
Type/Reset
RW
7
6
5
4
0
3
RW
0
2
RW
0
1
RW
0
0
ADLT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[11:0]
ADLT
A/D Converter Watchdog Lower Threshold Value
Specify the lower threshold of the A/D Conversion data.
Rev. 1.00
233 of 628
0
RW
0
RW
0
August 13, 2012
Analog to Digital Converter (ADC)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Watchdog Upper Threshold Register – ADCUTR
This register specifies the upper threshold of the A/D Converter watchdog function.
Offset:
0x128
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
ADUT
Type/Reset
RW
7
6
5
4
0
3
RW
0
2
RW
0
1
RW
0
0
ADUT
Type/Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[11:0]
ADUT
A/D Converter Watchdog Upper Threshold Value
Specify the upper threshold of the A/D Conversion data.
Rev. 1.00
234 of 628
0
RW
0
RW
0
August 13, 2012
Analog to Digital Converter (ADC)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Interrupt Mask Enable Register – ADCIMR
This register contains the A/D Converter interrupt enable bits.
Offset:
0x130
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
ADIMO
RW
23
22
21
20
19
18
17
Reserved
Type/Reset
15
14
13
12
0
16
ADIMU
ADIML
RW
RW
0
11
10
9
8
3
2
1
0
0
Reserved
Type/Reset
7
6
5
4
Reserved
Type/Reset
ADIMC
ADIMG
ADIMS
RW
RW
RW
0
0
Bits
Field
Descriptions
[24]
ADIMO
A/D Converter Regular Data Register Overwrite Interrupt Mask
0: A/D Converter regular data register overwrite interrupt is masked
1: A/D Converter regular data register overwrite interrupt is not masked
[17]
ADIMU
A/D Converter Watchdog Upper Threshold Interrupt Mask
0: A/D Converter watchdog upper threshold interrupt is masked
1: A/D Converter watchdog upper threshold interrupt is not masked
[16]
ADIML
A/D Converter Watchdog Lower Threshold Interrupt Mask
0: A/D Converter watchdog lower threshold interrupt is masked
1: A/D Converter watchdog lower threshold interrupt is not masked
[2]
ADIMC
A/D Converter Regular Cycle EOC Interrupt Mask
0: A/D Converter regular cycle end of conversion interrupt is masked
1: A/D Converter regular cycle end of conversion interrupt is not masked
[1]
ADIMG
A/D Converter Regular Subgroup EOC Interrupt Mask
0: A/D Converter regular subgroup end of conversion interrupt is masked
1: A/D Converter regular subgroup end of conversion interrupt is not masked
[0]
ADIMS
A/D Converter Regular Single EOC Interrupt Mask
0: A/D Converter regular single end of conversion interrupt is masked
1: A/D Converter regular single end of conversion interrupt is not masked
Rev. 1.00
235 of 628
0
August 13, 2012
Analog to Digital Converter (ADC)
Reserved
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Interrupt Raw Status Register – ADCIRAW
This register contains the A/D Converter interrupt raw status bits.
Offset:
0x134
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
ADIRAWO
RO
23
22
21
20
19
18
17
Reserved
RO
14
13
12
16
ADIRAWU ADIRAWL
Type/Reset
15
0
0
RO
11
10
9
8
3
2
1
0
0
Reserved
Type/Reset
7
6
5
4
Reserved
ADIRAWC ADIRAWG ADIRAWS
Type/Reset
RO
0
RO
0
RO
0
Bits
Field
Descriptions
[24]
ADIRAWO
A/D Converter Regular Data Register Overwrite Interrupt Raw Status
0: A/D Converter regular data register overwrite event does not occur
1: A/D Converter regular data register overwrite event occurs
The A/D Converter regular data overwrite event will occur at the end of the 3rd
regular conversion if the 1st regular conversion data has not been read by the
application program.
[17]
ADIRAWU
A/D Converter Watchdog Upper Threshold Interrupt Raw Status
0: A/D Converter watchdog upper threshold event does not occur
1: A/D Converter watchdog upper threshold event occurs
[16]
ADIRAWL
A/D Converter Watchdog Lower Threshold Interrupt Raw Status
0: A/D Converter watchdog lower threshold event does not occur
1: A/D Converter watchdog lower threshold event occurs
[2]
ADIRAWC
A/D Converter Regular Cycle EOC Interrupt Raw Status
0: A/D Converter regular cycle end of conversion event does not occur
1: A/D Converter regular cycle end of conversion event occurs
[1]
ADIRAWG
A/D Converter Regular Subgroup EOC Interrupt Raw Status
0: A/D Converter regular subgroup end of conversion event does not occur
1: A/D Converter regular subgroup end of conversion event occurs
[0]
ADIRAWS
A/D Converter Regular Single EOC Interrupt Raw Status
0: A/D Converter regular single sample end of conversion event does not occur
1: A/D Converter regular single sample end of conversion event occurs
Rev. 1.00
236 of 628
August 13, 2012
Analog to Digital Converter (ADC)
Reserved
Type/Reset
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Interrupt Masked Status Register – ADCIMASK
This register contains the A/D Converter interrupt masked status bits. The corresponding masked
status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.
Offset:
0x138
Reset value: 0x0000_0000
30
29
28
27
26
25
24
Reserved
ADIMASKO
Type/Reset
RO
23
22
21
20
19
18
17
Reserved
RO
14
13
12
16
ADIMASKU ADIMASKL
Type/Reset
15
0
0
RO
11
10
9
8
3
2
1
0
0
Reserved
Type/Reset
7
6
5
4
Reserved
ADIMASKC ADIMASKG ADIMASKS
Type/Reset
Rev. 1.00
RO
237 of 628
0
RO
0
RO
0
August 13, 2012
Analog to Digital Converter (ADC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Field
Descriptions
[24]
ADIMASKO
A/D Converter Regular Data Register Overwrite Interrupt Masked Status
0: A/D Converter regular data register overwrite event does not occur or the
related interrupt control is disabled
1: A/D Converter regular data register overwrite interrupt occurs as the related
interrupt control is enabled
[17]
ADIMASKU
A/D Converter Watchdog Upper Threshold Interrupt Masked Status
0: A/D Converter watchdog upper threshold event does not occur or the related
interrupt control is disabled
1: A/D Converter watchdog upper threshold interrupt occurs as the related
interrupt control is enabled
[16]
ADIMASKL
A/D Converter Watchdog Lower Threshold Interrupt Masked Status
0: A/D Converter watchdog lower threshold event does not occur or the related
interrupt control is disabled
1: A/D Converter watchdog lower threshold interrupt occurs as the related
interrupt control is enabled
[2]
ADIMASKC
A/D Converter Regular Cycle EOC Interrupt Masked Status
0: A/D Converter regular cycle end of conversion event does not occur or the
related interrupt control is disabled
1: A/D Converter regular cycle end of conversion interrupt occurs as the related
interrupt control is enabled
[1]
ADIMASKG
A/D Converter Regular Subgroup EOC Interrupt Masked Status
0: A/D Converter regular subgroup end of conversion event does not occur or the
related interrupt control is disabled
1: A/D Converter regular subgroup end of conversion interrupt occurs as the
related interrupt control is enabled
[0]
ADIMASKS
A/D Converter Regular Single EOC Interrupt Masked Status
0: A/D Converter regular single sample end of conversion event does not occur or
the related interrupt control is disabled
1: A/D Converter regular single sample end of conversion interrupt occurs as the
related interrupt control is enabled
Rev. 1.00
238 of 628
August 13, 2012
Analog to Digital Converter (ADC)
Bits
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC Interrupt Clear Register – ADCICLR
This register provides the clear bits used to clear the interrupt raw and masked status of the A/D
Converter. These bits are set to 1 by software to clear the interrupt status and automatically cleared
to 0 by hardware after being set to 1.
Offset:
0x13C
Reset value: 0x0000_0000
30
29
28
27
26
25
24
Reserved
ADICLRO
Type/Reset
WO
23
22
21
20
19
18
17
Reserved
WO
15
14
13
12
16
ADICLRU
Type/Reset
0
0
ADICLRL
WO
11
10
9
8
3
2
1
0
0
Reserved
Type/Reset
7
6
5
4
Reserved
ADICLRC
Type/Reset
WO
0
ADICLRG
WO
0
Bits
Field
Descriptions
[24]
ADICLRO
A/D Converter Regular Data Register Overwrite Interrupt Status Clear Bit
0: No effect
1: Clear ADIRAWO and ADIMASKO bits
[17]
ADICLRU
A/D Converter Watchdog Upper Threshold Interrupt Status Clear Bit
0: No effect
1: Clear ADIRAWU and ADIMASKU bits
[16]
ADICLRL
A/D Converter Watchdog Lower Threshold Interrupt Status Clear Bit
0: No effect
1: Clear ADIRAWL and ADIMASKL bits
[2]
ADICLRC
A/D Converter Regular Cycle EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIRAWC and ADIMASKC bits
[1]
ADICLRG
A/D Converter Regular Subgroup EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIRAWG and ADIMASKG bits
[0]
ADICLRS
A/D Converter Regular Single EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADIRAWS and ADIMASKS bits
Rev. 1.00
239 of 628
ADICLRS
WO
0
August 13, 2012
Analog to Digital Converter (ADC)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
ADC PDMA Request Register – ADCDMAR
This register contains the A/D Converter PDMA request enable bits.
Offset:
0x140
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
11
10
9
8
3
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
Reserved
Type/Reset
7
6
5
4
Reserved
ADDMAC
Type/Reset
RW
ADDMAG
0
RW
Bits
Field
Descriptions
[2]
ADDMAC
A/D Converter Regular Cycle EOC PDMA Request Enable Bit
0: Cycle end of conversion PDMA request is disabled
1: Cycle end of conversion PDMA request is enabled
[1]
ADDMAG
A/D Converter Regular Subgroup EOC PDMA Request Enable Bit
0: Subgroup end of conversion PDMA request is disabled
1: Subgroup end of conversion PDMA request is enabled
[0]
ADDMAS
A/D Converter Regular Single EOC PDMA Request Enable Bit
0: Single end of conversion PDMA request is disabled
1: Single end of conversion PDMA request is enabled
Rev. 1.00
240 of 628
0
ADDMAS
RW
0
August 13, 2012
Analog to Digital Converter (ADC)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
13
Operational Amplifier/Comparator (OPA/CMP)
Introduction
DATA IN
INCTRLEN
OPAnEN
AOUT PAD
DATA OUT
CP
CN
Figure 29. Simplied Block Diagram of OPA/CMP with Digital I/O
Features
▀
▀
▀
▀
▀
▀
Rev. 1.00
Operational Amplifier or Comparator function determined by software
Supply Voltage Range: 2.5V~3.6V
Typical Operating Current: 230μA (@VDD=3.3V and Room Temperature=25˚C)
Power Down Supply Current (OPAnEN=0 and AnOFM=0): < 0.1μA
Comparator Offset (After Calibration): < ±1mV
Comparator Response Time: < 2μs (@ overdrive voltage=10mV)
241 of 628
August 13, 2012
Operational Amplifier/Comparator (OPA/CMP)
Two Operational Amplifiers/Comparators, OPA/CMP, are implemented within the devices. They
can be configured either as Operational Amplifiers or Analog Comparators. When configured as
comparators, they are capable of asserting interrupts to the NVIC.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Functional Descriptions
Functional Diagram
CPn
SW2
+
OPA/CMP
AOUTn
_
AnOFM
AnRS
AnOF[5:0]
OPCnMS
OPAnEN
Figure 30. OPA/CMP Functional Diagram
Table 27. OPA/CMP Functional Signal Definition
AnOFM
AnRS
SW1
SW2
SW3
0
X
ON
ON
OFF
1
0
OFF
ON
ON
1
1
ON
OFF
ON
Interrupts and Status
The analog comparator can generate an interrupt when its output waveform generates a rising or
falling edge and its corresponding interrupt enables control bit is also set.
For example, when a comparator output rising edge occurs, the comparator rising edge raw flag
CRnRAW in the Comparator Raw Status Register CMPRSRn will be set. If the comparator output
rising edge interrupt enable control bit CRnIEN in the Comparator Interrupt Enable Register
CMPIERn is enabled, the comparator output rising edge masked interrupt status bit CRnIS in the
Comparator Masked Interrupt Status Register CMPISRn, will be set when the comparator output
rising edge occurs. An interrupt will then be generated and sent to the NVIC unit. Writing 1 into
the comparator output rising edge interrupt clear bit CRnICLR in the Comparator Interrupt Clear
Register CMPICLRn will clear the CRnIS and CRnRAW status bits. The comparator output falling
edge interrupt also has the same corresponding interrupt setting.
Rev. 1.00
242 of 628
August 13, 2012
Operational Amplifier/Comparator (OPA/CMP)
CNn
SW1
SW3
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Offset Cancellation Procedures
The device provides an offset cancellation function. Users can cancel the input voltage offset by
using a specific procedure by configuring the corresponding registers. The offset cancellation
procedure is shown in the following steps.
Note that the reference input voltage must be in the range from (V DDA-1.2V) to (VSSA+0.5V) to
obtain a more accurate cancellation result.
Register Map
The following table shows the OPA/CMP registers and reset values.
Table 28. OPA/CMP Register Map
Register
Offset
Description
Reset Value
OPACMP Base Address=0x4001_8000
Rev. 1.00
OPACR0
0x000
Operational Amplifier Control Register 0
OFVCR0
0x004
Comparator Input Offset Voltage Cancellation Register 0 0x0000_0000
CMPIER0
0x008
Comparator Interrupt Enable Register 0
0x0000_0000
CMPRSR0
0x00C
Comparator Raw Status Register 0
0x0000_0000
CMPISR0
0x010
Comparator Masked Interrupt Status Register 0
0x0000_0000
CMPICLR0
0x014
Comparator Interrupt Clear Register 0
NA
OPACR1
0x100
Operational Amplifier Control Register 1
0x0000_0000
OFVCR1
0x104
Comparator Input Offset Voltage Cancellation Register 1 0x0000_0000
CMPIER1
0x108
Comparator Interrupt Enable Register 1
0x0000_0000
CMPRSR1
0x10C
Comparator Raw Status Register 1
0x0000_0000
CMPISR1
0x110
Comparator Masked Interrupt Status Register 1
0x0000_0000
CMPICLR1
0x114
Comparator Interrupt Clear Register 1
NA
243 of 628
0x0000_0000
August 13, 2012
Operational Amplifier/Comparator (OPA/CMP)
Cancellation procedure:
1. Set the AnOFM bit in the OPACRn register to 1 to enter the offset cancellation mode.
2. Configure the AnRS bit in the OPACRn register to select whether the reference voltage input
comes from the comparator negative or positive input pin. If the AnRS bit is set to 1, the
reference voltage input will come from the comparator positive input pin. Otherwise, the
reference voltage input will come from the comparator negative input pin when the AnRS bit is
cleared to 0.
3. Specify the OFVCRn register with a value of 0x00 to start the cancellation procedure.
4. If the CMPnS bit in the OPACRn register is equal to 0, then increase the OFVCRn register
content, AnOF, by 1 and check whether the CMPnS bit state has changed from 0 to 1. If not, then
keep increasing the register content until the CMPnS bit state changes from 0 to 1.
5. When the CMPnS bit changes to 1, then the AnOF data which is equal to N or (N-1) is the
specific value written into the OFVCRn register to cancel the comparator input offset voltage.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Descriptions
Operational Amplifier Control Register n – OPACRn, n=0 or 1
This register contains the OPA/CMP enable control, the OPA/CMP mode selection, input offset
cancellation control bits and the comparator digital output status.
Offset:
0x000 (0), 0x100 (1)
Reset value: 0x0000_0000
30
29
28
27
26
25
24
18
17
16
10
9
8
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
CMPnS
Type/Reset
RO
7
6
5
4
Reserved
Type/Reset
0
3
2
1
0
AnRS
AnOFM
OPCnMS
OPAnEN
RW
0
RW
0
RW
0
RW
0
Bits
Field
Descriptions
[8]
CMPnS
Comparator Digital Output Status
This bit is read only and has the same polarity as Comparator output. It can be used
for software monitor the Comparator output in the input offset voltage cancellation
mode.
[3]
AnRS
Operational Amplifier Input Offset Cancellation Reference Voltage Selection
0: Comparator negative input is selected as the reference input
1: Comparator positive input is selected as the reference input
[2]
AnOFM
Operational Amplifier/Comparator Mode or Input Offset Voltage Cancellation Mode
Selection
0: Operational Amplifier/Comparator mode
1: Input offset voltage cancellation mode
[1]
OPCnMS
Operational Amplifier or Comparator Mode Selection
0: Operational Amplifier mode
1: Comparator mode
[0]
OPAnEN
Operational Amplifier/Comparator Enable Control
0: Disable Operational Amplifier/Comparator (entering the power down mode)
1: Enable Operational Amplifier/Comparator
Rev. 1.00
244 of 628
August 13, 2012
Operational Amplifier/Comparator (OPA/CMP)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Comparator Input Offset Voltage Cancellation Register n – OFVCRn, n=0 or 1
The register is used to cancel the comparator n input offset voltage.
Offset:
0x004 (0), 0x104 (1)
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
AnOF
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Bits
Field
Descriptions
[5:0]
AnOF
Operational Amplifier/Comparator Input Offset Voltage Cancellation Control
000000: Minumun
...
100000: Center
...
111111: Maxumun
Rev. 1.00
245 of 628
0
August 13, 2012
Operational Amplifier/Comparator (OPA/CMP)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Comparator Interrupt Enable Register n – CMPIERn, n=0 or 1
This register provides the comparator n output transition interrupt enable control bits.
Offset:
0x008 (0), 0x108 (1)
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
3
Reserved
Type/Reset
Bits
Field
Descriptions
[1]
CRnIEN
Comparator Output Rising Edge Interrupt Enable Control
0: Comparator output rising edge interrupt is disabled
1: Comparator output rising edge interrupt is enabled
[0]
CFnIEN
Comparator Output Falling Edge Interrupt Enable Control
0: Comparator output falling edge interrupt is disabled
1: Comparator output falling edge interrupt is enabled
Rev. 1.00
246 of 628
CRnIEN
CFnIEN
RW
RW
0
0
August 13, 2012
Operational Amplifier/Comparator (OPA/CMP)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Comparator Raw Status Register n – CMPRSRn, n=0 or 1
This register contains the comparator n output transition event raw status.
Offset:
0x00C (0), 0x10C (1)
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
Reserved
Type/Reset
3
CRnRAW
RO
0
CFnRAW
RO
0
Bits
Field
Descriptions
[1]
CRnRAW
Comparator Output Rising Edge Raw Flag
0: No Comparator output rising edge occurs
1: Comparator output rising edge occurs
This bit can be cleared by writing 1 into the CRnICLR bit in the CMPICLRn register
via the application software.
[0]
CFnRAW
Comparator Falling Edge Interrupt Raw Flag
0: No Comparator output falling edge occurs
1: Comparator output falling edge occurs
This bit can be cleared by writing 1 into the CFnICLR bit in the CMPICLRn register
via the application software.
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Operational Amplifier/Comparator (OPA/CMP)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Comparator Masked Interrupt Status Register n – CMPISRn, n=0 or 1
This register contains the comparator n transition event masked interrupt status.
Offset:
0x010 (0), 0x110 (1)
Reset value: 0x0000_0000
31
30
29
28
27
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
Reserved
Type/Reset
3
CRnIS
CFnIS
RO
RO
0
0
Bits
Field
Descriptions
[1]
CRnIS
Comparator Output Rising Edge Masked Interrupt Flag
0: No Comparator output rising edge occurs or the Comparator output rising edge
interrupt is disabled
1: Comparator output rising edge occurs and the Comparator output rising edge
interrupt is enabled
[0]
CFnIS
Comparator Output Falling Edge Masked Interrupt Flag Bit
0: No Comparator output falling edge occurs or the Comparator output falling
edge interrupt is disabled
1: Comparator output falling edge occurs and the Comparator output falling edge
interrupt is enabled
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Operational Amplifier/Comparator (OPA/CMP)
26
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Comparator Interrupt Clear Register n – CMPICLRn, n=0 or 1
The register provides the interrupt status clear bits used to indicate the comparator n output transition
interrupt raw and masked status. These bits are set to 1 by software to clear the associated interrupt
raw and masked status bits and cleared to 0 by hardware automatically after being set to 1.
Offset:
0x014 (0), 0x114 (1)
Reset value: 0x0000_0000
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
Reserved
Type/Reset
23
22
21
20
19
Reserved
Type/Reset
15
14
13
12
11
Reserved
Type/Reset
7
6
5
4
Reserved
Type/Reset
3
CRnICLR
WO
0
CFnICLR
WO
0
Bits
Field
Descriptions
[1]
CRnICLR
Comparator Output Rising Edge Interrupt status Clear Control
0: No effect
1: Comparator output rising edge interrupt raw status and masked status is cleared
[0]
CFnICLR
Comparator Output Falling Edge Interrupt status Clear Control Bit
0: No effect
1: Comparator output falling edge interrupt raw status and masked status is cleared
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Operational Amplifier/Comparator (OPA/CMP)
31
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
14
General-Purpose Timers (GPTM0 & GPTM1)
Introduction
TME
UEVG
TEV
fCLKIN
fsampling
ETIFED
TRCED
start/stop/reset
UEV
CH0OREF
TI1S1ED
TI0S1ED
TI1S0ED
TI0S0ED
TI1S1
TM_CNT
CEV0
MEVx
CH0CCR
CH0PSC
GTn_CH0
MTO
fCLKIN
fCLKIN
TI0S0
TI1S1ED
TI0S0ED
TI1S1
TI0BED
TI0S0
Clock
UP_CNT
Quadrature
Controller
DecoderfCLKIN DOWN_CNT
Master
Controller
CH3OREF
Slave
Controller
CH2OREF
GTn_ETI
STIED
CH1OREF
STI
Trigger Controller
ITI2
CEV0
ITI1
UEV
MEV0
ITI0
GTn_CH0
CEV1
CH1PSC
GTn_CH1
Input Stage Block
CEV2
CH2PSC
GTn_CH2
Channel
Controller
CH1CCR
CH2CCR
Output Stage
Block
GTn_CH1
GTn_CH2
CEV3
GTn_CH3
fsampling
CEVx : Channel x Capture Event
CH3PSC
UEV : Update Event
fCLKIN
TEV : Trigger Event
CH3CCR
fCLKIN
GTn_CH3
MEVx : Channel x Compare Match Event
ITI0~ITI2 : Internal Trigger Inputs
Figure 31. GPTM Block Diagram
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General-Purpose Timers (GPTM0 & GPTM1)
The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare
Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers.
It can be used for a variety of purposes including general timer, input signal pulse width
measurement or output waveform generation such as single pulse generation or PWM output. The
GPTM supports an encoder interface using a quadrature decoder with two inputs.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Features
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General-Purpose Timers (GPTM0 & GPTM1)
▀ 16-bit up/down auto-reload counter
▀ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor
between 1 and 65536
▀ Up to 4 independent channels for:
● Input Capture function
● Compare Match Output
● Generation of PWM waveform – Edge and Center-aligned Mode
● Single Pulse Mode Output
Encoder
interface controller with two inputs using quadrature decoder
▀
▀ Synchronization circuit to control the timer with external signals and to interconnect several
timers together
▀ Interrupt/PDMA generation with the following events:
● Update event
● Trigger event
● Input capture event
● Output compare match event
▀ GPTM Master/Slave mode controller
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Functional Descriptions
Counter Mode
When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter
value will also be initialized to 0.
CK_PSC
CNT_EN
CK_CNT
CNTR
CRR
F2
F3
0
F5
3
2
1
F5
36
36
F5
CRR Shadow Register
PSCR
F4
1
0
PSCR Shadow Register
0
PSC_CNT
0
1
0
1
0
1
0
1
0
1
Counter Overflow
Update Event Flag
Write a new value
Update the new value
Software clearing
Figure 32. Up-counting Example
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General-Purpose Timers (GPTM0 & GPTM1)
Up-Counting
In this mode the counter counts continuously from 0 to the counter-reload value, which is defined
in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value,
the Timer Module generates an overflow event and the counter restarts to count once again from
0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register
should be set to 0 for the up-counting mode.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Down-Counting
In this mode the counter counts continuously from the counter-reload value, which is defined in
the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module
generates an underflow event and the counter restarts to count once again from the counter-reload
value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register
should be set to 1 for the down-counting mode.
CK_PSC
CNT_EN
CK_CNT
CNTR
CRR
3
2
35
36
0
33
34
36
F5
CRR Shadow Register
PSCR
1
36
F5
1
0
PSCR Shadow Register
0
PSC_CNT
0
1
0
1
0
1
0
1
0
1
Counter Underflow
Update Event Flag
Software clearing
Write a new value
Update a new value
Figure 33. Down-counting Example
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General-Purpose Timers (GPTM0 & GPTM1)
When the update event is set by the UEVG bit in the EVGR register, the counter value will also be
initialized to the counter-reload value.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Center-Align Counting
In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value
and then counts down to 0 alternatively. The Timer module generates an overflow event when the
counter counts to the counter-reload value in the up-counting mode and generates an underflow
event when the counter counts to 0 in the down-counting mode. The counting direction bit DIR in
the CNTCFR register is read-only and indicates the counting direction when in the center-align
mode. The counting direction is updated by hardware automatically.
The UEVIF bit in the INTSR register can be set to 1 according to the CMSEL field setting in
the CNTCFR register. When CMSEL=0x01, an underflow event will set the UEVIF bit to 1.
When CMSEL=0x10, an overflow event will set the UEVIF bit to 1. When CMSEL=0x11, either
underflow or overflow event will set the UEVIF bit to 1.
CK_PSC
CNT_EN
CK_CNT
CNTR
CRR
CRR Shadow Register
F3
F2
F4
3
4
F5
2
0
1
1
2
3
4
4
F5
Counter Overflow
Counter Underflow
Update Event Flag
Write a new value
Software clearing
Software clearing
Figure 34. Center-aligned Counting Example
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General-Purpose Timers (GPTM0 & GPTM1)
Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of
whether the counter is counting up or down in the center-align counting mode.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Clock Controller
The following describes the Timer Module clock controller which determines the clock source of
the internal prescaler counter.
▀ Quadrature Decoder:
To select Quadrature Decoder mode the SMSEL field should be set to 0x1, 0x2 or 0x3 in the
MDCFR register. The Quadrature Decoder function uses two input states of the GTn_CH0 and
GTn_CH1 pins to generate the clock pulse to drive the counter prescaler. The counting direction
bit DIR is modified by hardware automatically at each transition on the input source signal.
▀ STIED:
The counter prescaler can count during each rising edge of the STI signal. This mode can be
selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act
as an event counter. The input event, known as STI here, can be selected by setting the TRSEL
field to an available value except the value of 0x0. When the STI signal is selected as the clock
source, the internal edge detection circuitry will generate a clock pulse during each STI signal
rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to
0x0 to select the software UEVG bit as the trigger source, then when the SMSEL field is set to
0x7, the counter will be updated instead of counting.
▀ ETIFED:
The counter prescaler can be driven to count during each rising edge on ETIF. This mode can
be selected by setting the ECME bit in the TRCFR register to 1. The other way to select the
ETIF signal as the clock source is to set the SMSEL field to 0x7 and the TRSEL field to 0x3
respectively. When the clock source is selected to come from the ETIF signal, the Trigger
Controller including the edge detection circuitry will generate a clock pulse during each ETIF
signal rising edge to clock the counter prescaler.
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General-Purpose Timers (GPTM0 & GPTM1)
▀ Internal APB clock fCLKIN:
The default internal clock source is the APB clock fCLKIN used to drive the counter prescaler
when the slave mode is disabled. When the slave mode selection bits SMSEL are set to 0x4, 0x5
or 0x6, the internal APB clock fCLKIN is the counter prescaler driving clock source.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
CRR
PSCR
CLKPULSE
(Quadrature Decoder)
fCLKIN
(Internal APB clock)
Update Event
CK_PSC
CK_CNT
CLK
PSC Prescaler
STIED
Reset
TM_CNT
CNTR
Reset
ETIFED
(External GTn_ETI Input)
TRSEL
SMSEL
ECME
Start/Stop
Overflow /
Underflow
UEVG bit
Slave Restart
mode trigger
Figure 35. GPTM Clock Selection Source
Trigger Controller
The trigger controller is used to select the trigger source and setup the trigger level or edge trigger
condition. The active polarity of the external trigger input signal GTn_ETI can be configured by
the External Trigger Polarity control bit ETIPOL in the GPTM Trigger Configuration Register
TRCFR. The frequency of the external trigger input can be divided by configuring the related bits,
named as External Trigger Prescaler control bits ETIPSC, in the TRCFR register. The trigger signal
can also be filtered by configuring the External Trigger Filter ETF selection bits in the TRCFR
register if a filtered signal is necessary for specific applications. For the internal trigger input, it can
be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources
except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock
pulse at each trigger signal rising edge to stimulate some GPTM functions which are triggered by a
trigger signal rising edge.
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General-Purpose Timers (GPTM0 & GPTM1)
(Trigger events)
CLK
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux
External Trigger Controller
GTx_ETI
Prescaler
ETIP
Edge Detection
Filter
fsampling
ITI0
ITI1
ITI2
fCLKIN
ETIPSC
ETF
ETIF
ITI0ED
Edge
Detection
ITI1ED
ITI2ED
fCLKIN
Edge Trigger = External (ETI)+ Internal (ITIx) + Channel input (CHx) + XOR function
0
TI0S0ED
TI1S1ED
ETIFED
Edge Trigger Mux
000
001
010
Reserved
TI0BED
ITI0ED
ITI1ED
ITI2ED
000
011
others
TRSEL[2:0]
0
001
010
Reserved
STIED_S0
STIED_S1
STIED
1
011
others
TRSEL[3]
TRCED
Level Trigger Source = External (ETI)+ Internal (ITIx) + Channel input (CHx) + Software UEVG bit
SW set
UEVG bit
TI0S0
TI1S1
ETIF
Level Trigger Mux
000
001
010
Reserved
0
ITI0
ITI1
ITI2
000
Reserved
STI_S0
TRSEL[2:0]
001
010
011
others
0
STI_S1
011
others
1
STI
TRSEL[3]
Figure 36. Trigger Control Block
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General-Purpose Timers (GPTM0 & GPTM1)
ETIPOL
ETIFED
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Slave Controller
The GPTM can be synchronized with an internal/external trigger in several modes including the
Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the
MDCFR register. The trigger input of these modes comes from the STI signal which is selected by
the TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described
in the accompanying sections.
STI
Trigger Event
Slave
Controller
Reset/Stop/Start Counter
Restart/Pause/Trigger Mode
SMSEL
Figure 37. Slave Controller Diagram
Restart Mode
The counter and its prescaler can be reinitialized in response to a rising edge of the STI signal.
When a STI rising edge occurs, the update event software generation bit named UEVG will
automatically be asserted by hardware and the trigger event flag will also be set. Then the counter
and prescaler will be reinitialized. Although the UEVG bit is set to 1 by hardware, the update event
does not really occur. It depends upon whether the update event disable control bit UEVDIS is set
to 1 or not. If the UEVDIS is set to 1 to disable the update event to occur, there will no update event
be generated, however the counter and prescaler are still reinitialized when the STI rising edge
occurs. If the UEVDIS bit in the CNTCFR register is cleared to enable the update event to occur,
an update event will be generated together with the STI rising edge, then all the preloaded registers
will be updated.
Timer Counter Reload Register CRR = 32
STI source signal
(polarity=0)
STI source signal
(polarity=1)
STI
Sync.
CK_CNT
UEVG bit
(reset counter)
Trigger Event
CNTR
(Up-counting)
27
28
29
30
31
0
1
2
CNTR
(Down-counting)
27
26
25
24
23
32
31
30
TEVIF
Figure 38. GPTM in Restart Mode
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General-Purpose Timers (GPTM0 & GPTM1)
Trigger
Controller
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Pause Mode
In the Pause Mode, the selected STI input signal level is used to control the counter start/stop
operation. The counter starts to count when the selected STI signal is at a high level and stops
counting when the STI signal is changed to a low level, here the counter will maintain its present
value and will not be reset. Since the Pause function depends upon the STI level to control the counter
stop/start operation, the selected STI trigger signal can not be derived from the TI0BED signal.
General-Purpose Timers (GPTM0 & GPTM1)
STI source signal
(polarity=0)
STI source signal
(polarity=1)
Sync
STI
Sync
CK_ CNT
CNT_EN
CNTR
27
28
29
30
31
TEVIF
Software clearing
Figure 39. GPTM in Pause Mode
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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
STI source signal
(polarity=0)
STI source signal
(polarity=1)
STI
Sync
CK_CNT
CNT_EN
CNTR
(Up-counting)
27
28
29
30
31
32
TEVIF
Software clearing
Figure 40. GPTM in Trigger Mode
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General-Purpose Timers (GPTM0 & GPTM1)
Trigger Mode
After the counter is disabled to count, the counter can resume counting when a STI rising edge
signal occurs. When an STI rising edge occurs, the counter will start to count from the current
value in the counter. Note that if the STI signal is selected to be derived from the UEVG bit
software trigger, the counter will not resume counting. When software triggering using the UEVG
bit is selected as the STI source signal, there will be no clock pulse generated which can be used to
make the counter resume counting. Note that the STI signal is only used to enable the counter to
resume counting and has no effect on controlling the counter to stop counting.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Master Controller
The GPTMs and MCTMs can be linked together internally for timer synchronization or chaining.
When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will
generate a Master Trigger Output (MTO) signal which can reset, start, stop the Slave counter or
be a clock source of the Salve counter. This can be selected by the MMSEL field in the MDCFR
register to trigger or drive another GPTM or MCTM, which is configured in the Slave Mode.
MMSEL
TSE
GPTMm/MCTMm Slave
MTO
SMSEL
ITI
TRSEL
Figure 41. Master GPTMn and Slave GPTMm/MCTMm Connection
The Master Mode Selection bits, MMSEL, in the MDCFR register are used to select the MTO
source for synchronizing another slave GPTM or MCTM.
UEVG bit
Counter enable signal
Update Event
CH0OREF
MUX
Channel 0 Capture/Compare event
MTO
CH1OREF
CH2OREF
CH3OREF
MMSEL
Figure 42. MTO Selection
For example, setting the MMSEL field to 0x5 is to select the CH1OREF signal as the MTO signal
to synchronize another slave GPTM or MCTM. For a more detailed description, refer to the related
MMSEL field definitions in the MDCFR register.
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General-Purpose Timers (GPTM0 & GPTM1)
GPTMn Master
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Channel Controller
The GPTM has four independent channels which can be used as capture inputs or compare match
outputs. Each capture input or compare match output channel is composed of a preload register and
a shadow register. Data access of the APB bus is always through the read/write preload register.
When used in the input capture mode, the counter value is captured into the CHxCCR shadow
register first and then transferred into the CHxCCR preload register when the capture event occurs.
APB Bus Interface
CHxCCR
(Preload Register)
CHxPSC
Read CHxCCR
Capture
Controller
Capture Transfer
Write CHxCCR
Compare Transfer
Compare
Controller
Update Event
CHxCCR
(Shadow Register)
CHxCCS
CHxCCG
CHxCCS
Capture
CHxPRE
CHxCCR
CHxE
TM_CNT
Figure 43. Capture/Compare Block Diagram
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General-Purpose Timers (GPTM0 & GPTM1)
When used in the compare match output mode, the contents of the CHxCCR preload register is copied
into the associated shadow register; the counter value is then compared with the register value.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Capture Counter Value Transferred to CHxCCR
When the channel is used as a capture input, the counter value is captured into the Channel
Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the
capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly. If the CHxCCIF
bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on
this channel occurs, the corresponding channel Over-Capture flag, named CHxOCF, will be set.
GTn_CH0
(TI0)
CNTR
CHxCCR
25
26
27
0
28
29
30
26
31
32
34
33
35
32
CHxCCIF
CHxOCF
Figure 44. Input Capture Mode
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General-Purpose Timers (GPTM0 & GPTM1)
fCLKIN
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Pulse Width Measurement
The input capture mode can be also used for pulse width measurement from signals on the
GTn_CHx pins (TIx). The following example shows how to configure the GPTM operated in the
input capture mode to measure the high pulse width and the input period on the GTn_CH0 pin
using channel 0 and channel 1. The basic steps are shown as follows.
Restart mode
Reset counter value
Restart mode
Reset counter value
GTn_CH0
(TI0)
Capture CH1
Capture CH0
CNTR
7
0
1
2
3
4
5
7
6
CH0CCR
7
CH1CCR
4
0
1
2
3
4
5
6
Figure 45. PWM Pulse Width Measurement Example
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General-Purpose Timers (GPTM0 & GPTM1)
Configure the capture channel 0 (CH0CCS=0x1) to select the TI0 signal as the capture input
Configure the CH0P bit to 0 to choose the rising edge of the TI0 input as the active polarity
Configure the capture channel 1 (CH1CCS=0x2) to select the TI0 signal as the capture input
Configure the CH1P bit to 1 to choose the falling edge of the TI0 input as the active polarity
Configure the TRSEL bits to 0x0001 to select TI0S0 as the trigger input
Configure the Slave controller to operate in the Restart mode by setting the SMSEL field in the
MDCFR register to 0x4
▀ Enable the input capture mode by setting the CH0E and CH1E bits in the CHCTR register to 1
As the following diagram shows, the high pulse width on the GTn_CH0 pin will be captured into
the CH1CCR register while the input period will be captured into the CH0CCR register after input
capture operation.
▀
▀
▀
▀
▀
▀
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Input Stage
The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel
prescaler. The channel 0 input signal (TI0) can be chosen to come from the GTn_CH0 signal or
the Excusive-OR function of the GTn_CH0, GTn_CH1 and GTn_CH2 signals. The channel input
signal (TIx) is sampled by a digital filter to generate a filtered input signal TIxFP. Then the channel
polarity and the edge detection block can generate a TIxSxED signal for the input capture function.
The effective input event number can be set by the channel input prescaler register (CHxPSC).
fCLKIN
GTn_CH0
GTn_CH1
XOR
TI0BED
TI0XOR
Edge
Detection
GTn_CH2
TI0
fsampling
Edge
Detection
Filter
TI0FP
CH0CCS
fCLKIN
TI0S0
TI0FN
Edge
Detection
TI0S0ED
CH0PRESCALER
CH0P
TI0F
TI1S0
TI0S1
Edge
Detection
TI1S0ED
Edge
Detection
TI0S1ED
Edge
Detection
TI1S1ED
CH0PSC
CH0CAP Event
CH0PSC
CH1P
TI1
GTn_CH1
fsampling
Filter
TI1FP
TI1FN
TI1S1
CH1PRESCALER
CH1PSC
CH1CAP Event
CH1PSC
TI1F
CH1CCS
Figure 46. Channel 0 and Channel 1 Input Stage
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General-Purpose Timers (GPTM0 & GPTM1)
TRCED
TI0SRC
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
TRCED
GTn_CH2
TI2
fsampling
Filter
fCLKIN
TI2FP
CH2CCS
Edge
Detection
TI2S2
TI2FN
TI2F
CH2PRESCALER
CH2P
TI3S2
TI3
fsampling
Edge
Detection
TI3S2ED
Edge
Detection
TI2S3ED
Edge
Detection
TI3S3ED
CH2PSC
CH2CAP Event
CH2PSC
CH3P
Filter
TI3FP
TI3S3
TI3FN
CH3PRESCALER
CH3PSC
CH3CAP Event
CH3PSC
TI3F
CH3CCS
Figure 47. Channel 2 and Channel 3 Input Stage
Output Stage
The GPTM has four channels for compare match, single pulse or PWM output function. The
channel output GTn_CHx is controlled by the REFxCE, CHxOM, CHxP and CHxE bits in the
corresponding CHxOCFR, CHPOLR and CHCTR registers.
ETI
CNTR
CHxCCR
fCLKIN
CHxOREF
Output
Mode
Controller
Output Enable
Controller
CHxP
GTn_CHx
CHxE
CHxOREF
CHxCMP Event
REFxCE
CHxOM
Figure 48. Output Stage Block Diagram
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General-Purpose Timers (GPTM0 & GPTM1)
TI2S3
GTn_CH3
TI2S2ED
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Channel Output Reference Signal
When the GPTM is used in the compare match output mode, the CHxOREF signal (Channel x
Output Reference signal) is defined by setting the CHxOM bits. The CHxOREF signal has several
types of output function. These include, keeping the original level by setting the CHxOM field to
0x00, set to 0 by setting the CHxOM field to 0x01, set to 1 by setting the CHxOM field to 0x02 or
signal toggle by setting the CHxOM field to 0x03 when the counter value matches the content of
the CHxCCR register.
Another special function of the CHxOREF signal is a forced output which can be achieved by
setting the CHxOM field to 0x04/0x05. Here the output can be forced to an inactive/active level
irrespective of the comparison condition between the counter and the CHxCCR values.
Counter Value
CHxOM=0x03, CHxPRE=0
(Output toggle, preload disable)
CRR
CHxCCR
(New value 2)
CHxCCR
(New value 3)
CHxCCR
(New value 1)
CHxCCR
Update
CHxCCR value
Time
(1)
(2)
(3)
TME
CHxOREF
UEV
(Update Event)
Figure 49. Toggle Mode Channel Output Reference Signal (CHxPRE=0)
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
The PWM mode 1 and PWM mode 2 outputs are also another kind of CHxOREF output which
is setup by setting the CHxOM field to 0x06/0x07. In these modes, the CHxOREF signal level is
changed according to the counting direction and the relationship between the counter value and the
CHxCCR content. With regard to a more detailed description refer to the relative bits definition.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Counter Value
CHxOM=0x03, CHxPRE=1
(Output toggle, preload enable)
CRR
CHxCCR
(New value 2)
CHxCCR
(New value 3)
(New value 1)
CHxCCR
Update
CHxCCR value
Time
(1)
(2)
(3)
TME
CHxOREF
UEV
(Update Event)
Figure 50. Toggle Mode Channel Output Reference Signal (CHxPRE=1)
Counter Value
Counter Value
Counter Value
CHxCCR
CRR
CRR
CRR
CHxCCR
CHxCCR
= 0x00
CHxOM = 0x06
100%
CHxOREF
CHxOREF
CHxOREF
CHxCCIF
CHxCCIF
CHxCCIF
CHxOM = 0x07
CHxOREF
0%
100%
CHxOREF
0%
CHxOREF
Figure 51. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode
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General-Purpose Timers (GPTM0 & GPTM1)
CHxCCR
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Counter Value
Counter Value
CHxCCR
CRR
CRR
CHxCCR
100%
CHxOREF
CHxOREF
CHxCCIF
CHxCCIF
CHxOM = 0x07
CHxOREF
CHxOREF
0%
Figure 52. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode
CMSEL= 0x01
0
Up-counting
1
2
3
CRR = 5
4
5
Down-counting
4
3
2
1
0
1
CHxCCR = 3
CHxCCIF
CHxCCR = 4
CHxCCIF
CHxCCR >= 5
100%
CHxCCIF
CHxCCR = 0
0%
CHxCCIF
Figure 53. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-align Mode
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General-Purpose Timers (GPTM0 & GPTM1)
CHxOM = 0x06
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Update Management
The Update event is used to update the CRR, the PSCR and the CHxCCR values from the actual
registers to the corresponding shadow registers. An update event occurs when the counter
overflows or underflows, the UEVG bit is set or the slave restart mode is triggered.
Update Event Management
Counter Overflow / Underflow
UEVG
UEV (Update PSCR, CRR,
CHxCCR Shadow Registers)
Slave Restart mode
UEVDIS
Update Event Interrupt Management
Counter Overflow / Underflow
UEV interrupt
UEVG
UEVDIS
Slave Restart mode
UGDIS
Figure 54. Update Event Setting Diagram
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General-Purpose Timers (GPTM0 & GPTM1)
The UEVDIS bit in the CNTCFR register can determine whether the update event occurs or
not. When the update event occurs, the corresponding update event interrupt will be generated
depending upon whether the update event interrupt generation function is enabled or not by
configuring the UGDIS bit in the CNTCFR register. For more detail description, refer to the
UEVDIS and UGDIS bit definition in the CNTCFR register.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Quadrature Decoder
TRCED
TI0SRC
fCLKIN
GTn_CH0
GTn_CH1
XOR
TI0BED
TI0XOR
Edge
Detection
GTn_CH2
TI0
fsampling
Edge
Detection
Filter
TI0FP
CH0CCS
fCLKIN
TI0S0
TI0FN
Edge
Detection
TI0S0ED
CH0PRESCALER
CH0P
TI0F
TI1S0
TI0S1
Edge
Detection
TI1S0ED
Edge
Detection
TI0S1ED
CH0PSC
CH1P
TI1
GTn_CH1
fsampling
Filter
TI1FP
TI1FN
CH1PRESCALER
TI1S1
Edge
Detection
CH0PSC
CH0CAP Event
CH1PSC
CH1CAP Event
TI1S1ED
CH1PSC
TI1F
CH1CCS
TI1S0
TI1S1
TI0S0ED
TI1S0ED
TI0S1ED
Quadrature
Decoder
TI1S1ED
SMSEL
Figure 55. Input Stage and Quadrature Decoder Block Diagram
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GTn_CH0
and GTn_CH1 pins respectively to interact to generate the counter value. The DIR bit is modified by
hardware automatically during each input source transition. The counter is countering on TI0 edges
only, TI1 edges only or both TI0 and TI1 edges. The selection is made by setting the SMSEL field
to 0x01, 0x02 or 0x03. The mechanism for changing the counter direction is shown in the following
table. The Quadrature decoder can be regarded as an external clock with a directional selection. This
means that the counter counts continuously in the interval between 0 and the counter-reload value.
Therefore, users must configure the CRR register before the counter starts to count.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Table 29. Counting Direction and Encoding Signals
Counting mode
Level
TI0S0
TI1S1
Rising
Falling
Rising
Falling
TI1S1=High
Down
Up
—
—
TI1S1=Low
Up
Down
—
—
Counting on TI1 only
(SMSEL=0x02)
TI0S0=High
—
—
Up
Down
TI0S0=Low
—
—
Down
Up
TI1S1=High
Down
Up
X
X
TI1S1=Low
Up
Down
X
X
TI0S0=High
X
X
Up
Down
TI0S0=Low
X
X
Down
Up
Counting on TI0 and TI1
(SMSEL=0x03)
NOTE: “—” → means “no counting”; “ X ” → impossible
TI0
TI1
Up
Quadrature Decoder
Counting on Both TI0 & TI1
(CH0P = 0, CH1P = 0)
Down
Figure 56. Both TI0 and TI1 Quadrature Decoder Counting
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
Counting on TI0 only
(SMSEL=0x01)
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Digital Filter
The digital f ilters are embedded in the input stage and clock controller block for the
GTn_CH0~GTn_CH3 and GTn_ETI pins respectively. The digital filter in the GPTM is an N-event
counter where N refers to how many valid transitions are necessary to output a filtered signal. The
N value can be 0, 2, 4, 5, 6 or 8 according to the user selection for each filter.
ETIP
D
No Filtered
Q
D
Q
D
Q
J
Q
Filtered
CK
CK
CK
CK
K
fsampling
Figure 57. GTn_ETI Pin Digital Filter Diagram with N=2
Clearing CHxOREF when ETIF is high
The CHxOREF signal can be forced to 0 when the ETIF signal is set to a high level by setting the
REFxCE bit to 1 in the CHxOCFR register. The CHxOREF signal will not return to its active level
until the next update event occurs.
Counter value
CHxCCR
Time
Update Event
ETIF
CHxOREF
CHxOREF is still low
Until the next Update Event occurs
Figure 58. Clearing CHxOREF by ETIF
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
Digital Filter (N=2)
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Single Pulse Mode
Counter Value
CRR
CHxCCR
Counter
reinitialized
Counter stopped
and held
Time
TME bit
Trigger by STI
Cleared by
Update Event
Trigger by S/W
Cleared by S/W
STI
CHxOREF
(PWM1)
delay
delay
(PWM2)
delay
delay
CHxOREF
min. delay
(PWM2)
min. delay
(PWM1)
UEVIF
CHxCCIF
delay
delay
CHxIMAE=0
CHxIMAE=1
Flag is set by update event
and clear by S/W
Flag is set by compare match
and cleared by S/W
Figure 59. Single Pulse Mode
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable
bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be
sourced from the STI signal rising edge or by setting the TME bit to 1 using software. Setting the
TME bit to 1 or a trigger from the STI signal rising edge can generate a pulse and then keep the
TME bit at a high state until the update event occurs or the TME bit is written to 0 by software.
If the TME bit is cleared to 0 using software, the counter will be stopped and its value held. If the
TME bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Counter Value
CRR
ETIPSC = 0
ETF = 0
CKDIV = 0
Up-Counting Mode
6
5
CHxCCR
4
3
2
1
0
Time
fCLKIN
GTn_ETI
STI
TME
Counter Start Time
CHxIMAE
CHxOREF
(PWM1)
(PWM2)
Minimum delay
Figure 60. Immediate Active Mode Minimum Delay
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter.
However, there exist several clock delays to perform the comparison result between the counter
value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set
the CHxIMAE bit in each CHxOCFR register. After a STI rising edge trigger occurs in the single
pulse mode, the CHxOREF signal will immediately be forced to the state which the CHxOREF
signal will change to as the compare match event occurs without taking the comparison result into
account. The CHxIMAE bit is available only when the output channel is configured to operate in
the PWM1 or PWM2 output mode and the trigger source is derived from the STI signal.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Timer Interconnection
The timers can be internally connected together for timer chaining or synchronization. This can
be implemented by configuring one timer to operate in the Master mode while configuring another
timer to be in the Slave mode. The following figures present several examples of trigger selection
for the master and slave modes.
Master GPTM0
fCLKIN
GPTM0
CH0OREF
GPTM0
CNTR
32
33
36
35
34
00
01
Slave GPTM1
GPTM1
CNTR
FA
FB
FC
FD
GPTM1
TEVIF
Software cleaning
Figure 61. Pausing GPTM1 using the GPTM0 CH0OREF Signal
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
Using one timer to trigger another timer start or stop counting
▀ Configure GPTM0 as the master mode to send its channel 0 Output Reference signal CH0OREF
as a trigger output (MMSEL=0x04)
Configure
GPTM0 CH0OREF waveform
▀
▀ Configure GPTM1 to receive its input trigger source from the GPTM0 trigger output
(TRSEL=0x09)
▀ Configure GPTM1 to operate in the pause mode (SMSEL=0x05)
▀ Enable GPTM1 by writing 1 to the TME bit
▀ Enable GPTM0 by writing 1 to the TME bit
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
fCLKIN
GPTM0
UEVIF
GPTM0
CNTR
GPTM1
CNTR
13
15
14
FA
02
01
00
FB
FC
03
FD
GPTM1
TME bit
GPTM1
TEVIF
Software cleaning
Figure 62. Triggering GPTM1 with GPTM0 Update Event
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
Using one timer to trigger another timer start counting
▀ Configure GPTM0 to operate in the master mode to send its Update Event UEV as the trigger
output (MMSEL=0x02)
▀ Configure the GPTM0 period by setting the CHxCRR register
▀ Configure GPTM1 to get the input trigger source from the GPTM0 trigger output (TRSEL=0x09)
▀ Configure GPTM1 to be in the slave trigger mode (SMSEL=0x06)
▀ Start GPTM0 by writing 1 to the TME bit
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Master GPTM0
fDTS=fCLKIN
TI0
TI0FP
TI0S0ED
GPTM0 (TME bit)
GPTM0 (TEVIF)
TSE=1
Delay
GPTM0 CK_PSC
GPTM0 CNTR
34
0
Write UEVG bit
1
2
3
4
5
1
2
3
4
5
ITI
Slave GPTM1
GPTM1 (TME bit)
GPTM1 (TEVIF)
GPTM1 CK_PSC
GPTM1 CNTR
11
0
0
Write UEVG bit
Figure 63. Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
Starting two timers synchronously in response to an external trigger
▀ Configure GPTM0 to operate in the master mode to send its enable signal as a trigger output
(MMSEL=0x01)
▀ Configure GPTM0 slave mode to receive its input trigger source from GTn_CH0 pin
(TRSEL=0x01)
Configure
GPTM0 to be in the slave trigger mode (SMSEL=0x06)
▀
▀ Enable the GPTM0 master timer synchronization function by setting the TSE bit in the MDCFR
register to 1 to synchronize the slave timer
▀ Configure GPTM1 to receive its input trigger source from the GPTM0 trigger output
(TRSEL=0x09)
Configure
GPTM1 to be in the slave trigger mode (SMSEL=0x06)
▀
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Trigger ADC Start
To interconnect with the Analog-to-Digital Converter, the GPTM can output the MTO signal or
the channel output GTn_CHx (x=0~3) signal to be used as the Analog-to-Digital Converter input
trigger signal.
PDMA Request
CHCCDS
CH0CCDE
CH0_EV
0
UEV_EV
1
CH0 PDMA Request
CH1CCDE
CH1_EV
0
UEV_EV
1
CH2_EV
0
UEV_EV
1
CH1 PDMA Request
CH2CCDE
CH2 PDMA Request
CH3CCDE
CH3_EV
0
UEV_EV
1
CH3 PDMA Request
UEV_EV
UEV PDMA Request
UEVDE
TRIG_EV
Trigger PDMA Request
TEVDE
Figure 64. GPTM PDMA Mapping Diagram
Rev. 1.00
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General-Purpose Timers (GPTM0 & GPTM1)
The GPTM supports the interface for PDMA data transfer. There are certain events which
can generate the PDMA requests if the corresponding enable control bits are set to 1 to enable
the PDMA access. These events are the GPTM update events, trigger events and channel
capture/compare events. When the PDMA request is generated from the GPTM channel, it can be
derived from the channel capture/compare event or the GPTM update event selected by the channel
PDMA selection bit, CHCCDS, for all channels. For more detailed PDMA configuring information,
refer to the corresponding section in the PDMA chapter.
32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755
Register Map
The following table shows the GPTM registers and reset values.
Table 30. GPTM Register Map
Register
Offset
Description
Reset Value
GPTMn Base Address=0x4006_E000 (0); 0x4006_F000 (1)
0x000
Timer Counter Configuration Register
0x0000_0000
MDCFR
0x004
Timer Mode Configuration Register
0x0000_0000
TRCFR
0x008
Timer Trigger Configuration Register
0x0000_0000
CTR
0x010
Timer Control Register
0x0000_0000
CH0ICFR
0x020
Channel 0 Input Configuration Register
0x0000_0000
CH1ICFR
0x024
Channel 1 Input Configuration Register
0x0000_0000
CH2ICFR
0x028
Channel 2 Input Configuration Register
0x0000_0000
CH3ICFR
0x02C
Channel 3 Input Configuration Register
0x0000_0000
CH0OCFR
0x040
Channel 0 Output Configuration Register
0x0000_0000
CH1OCFR
0x044
Channel 1 Output Configuration Register
0x0000_0000
CH2OCFR
0x048
Channel 2 Output Configuration Register
0x0000_0000
CH3OCFR
0x04C
Channel 3 Output Configuration Register
0x0000_0000
CHCTR
0x050
Channel Control Register
0x0000_0000
CHPOLR
0x054
Channel Polarity Configuration Register
0x0000_0000
DICTR
0x074
Timer PDMA/Interrupt Control Register
0x0000_0000
EVGR
0x078
Timer Event Generator Register
0x0000_0000
INTSR
0x07C
Timer Interrupt Status Register
0x0000_0000
CNTR
0x080
Timer Counter Register
0x0000_0000
PSCR
0x084
Timer Prescaler Register
0x0000_0000
CRR
0x088
Timer Counter Reload Register
0x0000_FFFF
CH0CCR
0x090
Channel 0 Capture/Compare Register