2SJ549(L), 2SJ549(S) Silicon P Channel MOS FET REJ03G0896-0400 Rev.4.00 Jun 05, 2006 Description High speed power switching Features • Low on-resistance RDS (on) = 0.11 Ω typ. • Low drive current • 4 V gate drive devices • High speed switching Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) D 4 4 1. Gate 2. Drain 3. Source 4. Drain G 1 1 2 2 3 3 S Rev.4.00 Jun 05, 2006 page 1 of 8 2SJ549(L), 2SJ549(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Symbol VDSS VGSS ID Value –60 ±20 –12 –48 –12 –12 12 50 150 –55 to +150 ID (pulse) Note 1 IDR IAP Note 3 EAR Note 3 Pch Note 2 Tch Tstg Unit V V A A A A mJ W °C °C Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body to drain diode forward voltage Body to drain diode reverse recovery time Note: 4. Pulse test Rev.4.00 Jun 05, 2006 page 2 of 8 Symbol V (BR) DSS V (BR) GSS IDSS IGSS VGS (off) RDS (on) RDS (on) |yfs| Ciss Coss Crss td (on) tr td (off) tf VDF trr Min –60 ±20 — — –1.0 — — 5 — — — — — — — — — Typ — — — — — 0.11 0.16 8 580 300 85 10 55 85 60 –1.2 60 Max — — –10 ±10 –2.0 0.15 0.23 — — — — — — — — — — Unit V V µA µA V Ω Ω S pF pF pF ns ns ns ns V ns Test Conditions ID = –10 mA, VGS = 0 IG = ±100 µA, VDS = 0 VDS = –60 V, VGS = 0 VGS = ±16 V, VDS = 0 ID = –1 mA, VDS = –10 V ID = –6 A, VGS = –10 V Note 4 ID = –6 A, VGS = –4 V Note 4 ID = –6 A, VDS = –10 V Note 4 VDS = –10 V VGS = 0 f = 1 MHz VGS = –10 V ID = –6 A RL = 6 Ω IF = –12 A, VGS = 0 IF = –12 A, VGS = 0 diF/dt = 50 A/µs 2SJ549(L), 2SJ549(S) Main Characteristics Power vs. Temperature Derating Maximum Safe Operation Area –100 ID (A) 40 0 50 100 Case Temperature –3 –1 –0.3 Tc (°C) –3.5 V –10 –30 –100 VDS (V) –4 V Pulse Test VDS = –10 V Pulse Test –8 –6 –3 V –4 –2.5 V –2 Drain Current Drain Current –3 –4 –2 25°C Tc = 75°C VGS = –2 V 0 –2 –4 –6 –8 Drain to Source Voltage –25°C 0 –10 VDS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage –1.0 Pulse Test –0.8 ID = –5 A –0.6 –0.4 –2 A –0.2 –1 A 0 0 –4 –8 –12 Gate to Source Voltage Rev.4.00 Jun 05, 2006 page 3 of 8 –16 –20 VGS (V) 0 –1 –2 –3 –4 –5 VGS (V) Gate to Source Voltage Static Drain to Source on State Resistance vs. Drain Current Static Drain to Source on State Resistance RDS (on) (Ω) Drain to Source Saturation Voltage VDS (on) (V) sh ot ) –10 –10 V –5 V –6 0 µs Typical Transfer Characteristics ID (A) ID (A) –8 0 s m s( 1 Drain to Source Voltage Typical Output Characteristics –10 10 m Operation in this area is limited by RDS (on) Ta = 25°C –0.1 –0.1 –0.3 –1 200 150 –10 = 1 ) °C 25 0 PW c= (T 20 10 –30 n tio ra pe O Drain Current 60 10 µs DC Channel Dissipation Pch (W) 80 1 Pulse Test 0.5 0.2 VGS = –4 V 0.1 –10 V 0.05 0.02 0.01 –0.1 –0.3 –1 –3 Drain Current –10 –30 ID (A) –100 2SJ549(L), 2SJ549(S) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) (Ω) Static Drain to Source on State Resistance vs. Temperature 0.5 Pulse Test 0.4 –2 A 0.3 ID = –5 A VGS = –4 V 0.2 –1 A –5 A 0.1 –1 A, –2 A –10 V 0 –40 0 40 80 Case Temperature 120 160 20 10 1 VDS = –10 V Pulse Test 0.2 –0.1 –0.2 –0.5 –1 –2 –5 –10 Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage 2000 Pulse Test 1000 200 Capacitance C (pF) Reverse Recovery Time trr (ns) 75°C 0.5 Tc (°C) 500 100 50 20 di / dt = 50 A / µs VGS = 0, Ta = 25°C 10 5 –0.1 –0.2 –0.5 –1 –2 Reverse Drain Current –5 200 50 Coss 20 VGS = 0 f = 1 MHz 10 0 –10 –10 –8 VDS –60 –12 VDD = –50 V –25 V –10 V –80 –16 ID = –12 A –100 0 8 16 Gate Charge Rev.4.00 Jun 05, 2006 page 4 of 8 24 32 Qg (nc) –20 40 VGS (V) –4 VGS –40 –50 1000 Switching Time t (ns) –40 –30 Switching Characteristics Gate to Source Voltage –20 –20 Drain to Source Voltage VDS (V) 0 VDD = –10 V –25 V –50 V Crss 100 IDR (A) 0 Ciss 500 Dynamic Input Characteristics VDS (V) 25°C 2 Body-Drain Diode Reverse Recovery Time Drain to Source Voltage Tc = –25°C 5 300 td(off) 100 tf 30 tr td(on) 10 3 VGS = –10 V, VDD = –30 V PW = 5 µs, duty ≤ 1 % 1 –0.1 –0.2 –0.5 –1 Drain Current –2 –5 ID (A) –10 2SJ549(L), 2SJ549(S) Reverse Drain Current vs. Source to Drain Voltage Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current IDR (A) –10 –8 –10 V –6 –5 V –4 VGS = 0, 5 V –2 Pulse Test 0 0 –0.4 –0.8 –1.2 –1.6 Source to Drain Voltage –2.0 20 IAP = –12 A VDD = –25 V duty < 0.1 % Rg ≥ 50 Ω 16 12 8 4 0 25 50 75 100 125 150 Channel Temperature Tch (°C) VSD (V) Normalized Transient Thermal Impedance γ s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C D=1 1 0.5 0.3 0.2 0.1 0.1 0.05 θch – c (t) = γ s (t) • θch – c θch – c = 2.5°C/W, Tc = 25°C 0.02 PDM 0.03 0.0 1s 1 t ho pu D= lse 0.01 10 µ PW T PW T 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (S) Avalanche Test Circuit VDS Monitor Avalanche Waveform L EAR = 1 • L • IAP2 • 2 VDSS VDSS – VDD IAP Monitor Rg V(BR)DSS IAP D.U.T VDD VDS ID Vin –15 V 50 Ω 0 Rev.4.00 Jun 05, 2006 page 5 of 8 VDD 2SJ549(L), 2SJ549(S) Switching Time Test Circuit Waveform Vin Vout Monitor Vin Monitor 10% D.U.T. 90% RL 90% 90% Vin –10 V 50 Ω VDD = –30 V Vout td(on) Rev.4.00 Jun 05, 2006 page 6 of 8 10% tr 10% td(off) tf 2SJ549(L), 2SJ549(S) Package Dimensions RENESAS Code PRSS0004AE-A MASS[Typ.] 1.40g 4.44 ± 0.2 1.3 ± 0.15 1.3 ± 0.2 1.37 ± 0.2 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 JEITA Package Code SC-83 RENESAS Code PRSS0004AE-B 2.49 ± 0.2 11.0 ± 0.5 0.2 0.86 +– 0.1 Package Name LDPAK(S)-(1) Unit: mm 10.2 ± 0.3 8.6 ± 0.3 11.3 ± 0.5 0.3 10.0 +– 0.5 Previous Code LDPAK(L) / LDPAK(L)V Previous Code LDPAK(S)-(1) / LDPAK(S)-(1)V 0.4 ± 0.1 MASS[Typ.] 1.30g (1.5) 10.0 Rev.4.00 Jun 05, 2006 page 7 of 8 2.54 ± 0.5 0.4 ± 0.1 0.3 3.0 +– 0.5 2.54 ± 0.5 0.2 0.86 +– 0.1 7.8 7.0 2.49 ± 0.2 0.2 0.1 +– 0.1 1.37 ± 0.2 1.3 ± 0.2 7.8 6.6 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 Unit: mm 1.7 JEITA Package Code (1.4) Package Name LDPAK(L) 2.2 2SJ549(L), 2SJ549(S) Ordering Information Part Name 2SJ549L-E 2SJ549STL-E Quantity 500 pcs 1000 pcs Shipping Container Box (Sack) Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.4.00 Jun 05, 2006 page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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