2SJ529(L), 2SJ529(S) Silicon P Channel MOS FET REJ03G0879-0300 (Previous: ADE-208-654A) Rev.3.00 Sep 07, 2005 Description High speed power switching Features • Low on-resistance RDS (on) = 0.12 Ω typ. • 4 V gate drive devices • High speed switching Outline RENESAS Package code: PRSS0004ZD-B (Package name: DPAK (L)-(2) ) RENESAS Package code: PRSS0004ZD-C (Package name: DPAK (S) ) 4 4 D 1 1 2 3 Rev.3.00 Sep 07, 2005 page 1 of 8 2 3 1. Gate 2. Drain 3. Source 4. Drain G S 2SJ529(L), 2SJ529(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Value –60 Unit V VGSS ID ±20 –10 V A –40 –10 A A ID (pulse) IDR Note 1 Note 3 Avalanche current Avalanche energy IAP Note 3 EAR –10 8.5 A mJ Channel dissipation Channel temperature Pch Tch Note 2 20 150 W °C –55 to +150 °C Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Tstg Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit V (BR) DSS V (BR) GSS –60 ±20 — — — — V V ID = –10 mA, VGS = 0 IG = ±100 µA, VDS = 0 IDSS IGSS — — — — –10 ±10 µA µA VDS = –60 V, VGS = 0 VGS = ±16 V, VDS = 0 Gate to source cutoff voltage Static drain to source on state resistance VGS (off) RDS (on) –1.0 — — 0.12 –2.0 0.16 V Ω ID = –1 mA, VDS = –10 V Note 4 ID = –5 A, VGS = –10 V Static drain to source on state resistance Forward transfer admittance RDS (on) |yfs| — 4.5 0.17 7.5 0.24 — Ω S ID = –5 A, VGS = –4 V Note 4 ID = –5 A, VDS = –10 V Input capacitance Output capacitance Ciss Coss — — 580 300 — — pF pF Reverse transfer capacitance Turn-on delay time Crss td (on) — — 85 10 — — pF ns VDS = –10 V VGS = 0 f = 1 MHz Rise time Turn-off delay time tr td (off) — — 40 85 — — ns ns Fall time Body to drain diode forward voltage tf VDF — — 60 –1.2 — — ns V trr — 60 — ns Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Body to drain diode reverse recovery time Note: 4. Pulse test Rev.3.00 Sep 07, 2005 page 2 of 8 Test Conditions Note 4 VGS = –10 V ID = –5 A RL = 6 Ω IF = –10 A, VGS = 0 IF = –10 A, VGS = 0 diF/dt = 50 A/µs 2SJ529(L), 2SJ529(S) Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating –100 ID (A) Drain Current 20 10 0 0 50 100 150 Case Temperature –3 –1 –0.3 Tc (°C) –3.5 V –4 V Pulse Test –100 VDS (V) –8 –6 –3 V –4 –2.5 V –2 –4 25°C –2 Tc = 75°C VGS = –2 V 0 –2 –4 –6 Drain to Source Voltage –25°C 0 –10 –8 Drain to Source Saturation Voltage vs. Gate to Source Voltage –1.0 Pulse Test –0.8 ID = –5 A –0.6 –0.4 –2 A –0.2 –1 A 0 0 –4 –8 –12 Gate to Source Voltage Rev.3.00 Sep 07, 2005 page 3 of 8 –16 –20 VGS (V) 0 –1 –2 –3 –4 Gate to Source Voltage VDS (V) –5 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Static Drain to Source on State Resistance RDS (on) (Ω) Drain to Source Saturation Voltage VDS (on) (V) –30 VDS = –10 V Pulse Test Drain Current Drain Current –10 –10 –10 V –5 V –6 0 10 Typical Transfer Characteristics ID (A) ID (A) –8 –3 = Drain to Source Voltage Typical Output Characteristics –10 1 m s O m pe s ra (1 tio sh n ot (T ) c= 25 °C Operation in ) this area is limited by RDS (on) DC –10 Ta = 25°C –0.1 –0.1 –0.3 –1 200 PW µs 30 0 Channel Dissipation 10 µs –30 10 Pch (W) 40 1 0.5 0.2 VGS = –4 V 0.1 –10 V 0.05 0.02 Pulse Test 0.01 –0.1 –0.3 –1 –3 Drain Current –10 –30 ID (A) –100 2SJ529(L), 2SJ529(S) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) (Ω) Static Drain to Source on State Resistance vs. Temperature 0.5 Pulse Test 0.4 –2 A 0.3 ID = –5 A VGS = –4 V –1 A 0.2 0.1 –1 A, –2 A –5 A –10 V 0 –40 0 40 80 Case Temperature 120 160 20 10 5 0.5 VDS = –10 V Pulse Test 0.2 –0.1 –0.2 –0.5 –1 –2 –5 –10 Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage 2000 Pulse Test 1000 200 Capacitance C (pF) Reverse Recovery Time trr (ns) 75°C 1 Tc (°C) 500 100 50 20 10 di / dt = 50 A / µs VGS = 0, Ta = 25°C 5 –0.1 –0.2 –0.5 –1 –2 Reverse Drain Current –5 200 100 50 Coss IDR (A) –12 VDD = –10 V –25 V –50 V –80 –16 –100 0 8 16 Gate Charge Rev.3.00 Sep 07, 2005 page 4 of 8 24 32 Qg (nc) –40 –50 –20 40 VGS (V) 1000 Switching Time t (ns) VGS –60 Gate to Source Voltage –4 –8 VDS –30 Switching Characteristics ID = –10 A –40 –20 Drain to Source Voltage VDS (V) 0 –20 Crss 20 VGS = 0 f = 1 MHz 10 0 –10 –10 0 VDD = –10 V –25 V –50 V Ciss 500 Dynamic Input Characteristics VDS (V) 25°C 2 Body-Drain Diode Reverse Recovery Time Drain to Source Voltage Tc = –25°C 300 td(off) 100 tf 30 tr td(on) 10 3 VGS = –10 V, VDD = –30 V PW = 5 µs, duty ≤ 1 % 1 –0.1 –0.2 –0.5 –1 Drain Current –2 ID (A) –5 –10 2SJ529(L), 2SJ529(S) Reverse Drain Current vs. Source to Drain Voltage Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current IDR (A) –10 Pulse Test –8 –10 V –6 –5 V –4 VGS = 0, 5 V –2 0 0 –0.4 –0.8 –1.2 –1.6 Source to Drain Voltage –2.0 20 IAP = –10 A VDD = –25 V duty < 0.1 % Rg ≥ 50 Ω 16 12 8 4 0 25 50 75 100 125 150 Channel Temperature Tch (°C) VSD (V) Normalized Transient Thermal Impedance γ s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C D=1 1 0.5 0.3 0.2 0.1 0.1 θch – c (t) = γ s (t) • θch – c θch – c = 6.25°C/W, Tc = 25°C 0.05 0.02 D= PDM 1 e 0.0 uls tp o h 1s 0.03 0.01 10 µ PW T PW T 100 µ 10 m 1m 100 m 1 10 Pulse Width PW (S) Avalanche Test Circuit VDS Monitor Avalanche Waveform L EAR = 1 • L • IAP2 • 2 VDSS VDSS – VDD IAP Monitor Rg V(BR)DSS IAP D.U.T VDD VDS ID Vin –15 V 50 Ω 0 Rev.3.00 Sep 07, 2005 page 5 of 8 VDD 2SJ529(L), 2SJ529(S) Switching Time Test Circuit Waveform Vin Vout Monitor Vin Monitor 10% D.U.T. 90% RL 90% 90% Vin –10 V 50 Ω VDD = –30 V Vout td(on) Rev.3.00 Sep 07, 2005 page 6 of 8 10% tr 10% td(off) tf 2SJ529(L), 2SJ529(S) Package Dimensions RENESAS Code Package Name MASS[Typ.] PRSS0004ZD-B DPAK(L)-(2) / DPAK(L)-(2)V 0.42g Unit: mm 1.7 ± 0.5 JEITA Package Code 2.3 ± 0.2 0.55 ± 0.1 1.2 ± 0.3 16.2 ± 0.5 3.1 ± 0.5 1.15 ± 0.1 0.8 ± 0.1 (0.7) 4.7 ± 0.5 5.5 ± 0.5 6.5 ± 0.5 5.4 ± 0.5 0.55 ± 0.1 0.55 ± 0.1 2.29 ± 0.5 2.29 ± 0.5 RENESAS Code Package Name MASS[Typ.] SC-63 PRSS0004ZD-C DPAK(S) / DPAK(S)V 0.28g 6.5 ± 0.5 5.4 ± 0.5 (0.1) Unit: mm 2.3 ± 0.2 0.55 ± 0.1 0 – 0.25 2.5 ± 0.5 (1.2) 1.0 Max. 2.29 ± 0.5 Rev.3.00 Sep 07, 2005 page 7 of 8 (5.1) (5.1) (0.1) 1.2 Max 5.5 ± 0.5 1.5 ± 0.5 JEITA Package Code 0.8 ± 0.1 2.29 ± 0.5 0.55 ± 0.1 2SJ529(L), 2SJ529(S) Ordering Information Part Name 2SJ529L-E 2SJ529STL-E Quantity 3200 pcs 3000 pcs Shipping Container Box (Sack) Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.3.00 Sep 07, 2005 page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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