MAX8958

MAX8958
RELIABILITY REPORT
FOR
MAX8958EWW+T
WAFER LEVEL PRODUCTS
October 10, 2011
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR.
SUNNYVALE, CA 94086
Approved by
Richard Aburano
Quality Assurance
Manager, Reliability Engineering
Maxim Integrated Products. All rights reserved.
Page 1
MAX8958
Conclusion
The MAX8958EWW+T successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's
continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards.
Table of Contents
I. ........Device Description
V. ........Quality Assurance Information
II. ........Manufacturing Information
VI. .......Reliability Evaluation
III. .......Packaging Information
IV. .......Die Information
.....Attachments
I. Device Description
A. General
The MAX8958 provides a complete power-management solution for the latest portable application devices using a central processing unit (CPU) and
system controller unit (SCU). The IC powers both the CPU and SCU along with some peripherals. The power-management subsystem has five stepdown converters and 13 LDOs. Two step-down converters (VCC, VNN) are designed with 7-bit parallel bus VID control and differential remote
output voltage sensing. The VCC and VNN converters provide power to the CPU core and the graphics controller core. The parallel VID bus
between the IC and the CPU processor enables the converters to support dynamic output voltage changes required for efficient power management.
Slew rate control minimizes surge currents to and from the battery. The VID for VCC and VNN are multiplexed onto the same set of pins to optimize
the pin count.
Both these step-down converters use the Quick-PWM
TM
architecture. In addition, three hysteretic, high-efficiency, step-down
converters in the IC provide power for linear dropout regulators (LDOs) in this IC. The IC also features 13 LDOs to power RF, CPU, SCU, and
peripherals. The IC also has a real-time clock/calendar (RTC) that provides 32.768kHz 1.8V buffered outputs, seconds, minutes, hours, day, date,
month and year information as well as a time user-programmable alarm. The RTC supports both 12/24 hour time setting formats with AM/PM for the
12-hour mode and supports BCD and binary. A backup battery charger is also included. The IC is available in a space-efficient, 5.4mm x 5.7mm,
169-bump WLP package (0.4mm pitch)
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MAX8958
II. Manufacturing Information
A. Description/Function:
Complete Power Management IC for Intel's Next-Generation Atom
Processor-Based Platform
B. Process:
S45
C. Number of Device Transistors:
146860
D. Fabrication Location:
California, Texas or Japan
E. Assembly Location:
Japan
F. Date of Initial Production:
May 25, 2011
III. Packaging Information
A. Package Type:
169-bump WLP 13x13 array
B. Lead Frame:
N/A
C. Lead Finish:
N/A
D. Die Attach:
None
E. Bondwire:
N/A (N/A mil dia.)
F. Mold Material:
None
G. Assembly Diagram:
#05-9000-4318
H. Flammability Rating:
Class UL94-V0
I. Classification of Moisture Sensitivity per
JEDEC standard J-STD-020-C
Level 1
J. Single Layer Theta Ja:
°C/W
K. Single Layer Theta Jc:
°C/W
L. Multi Layer Theta Ja:
29°C/W
M. Multi Layer Theta Jc:
°C/W
IV. Die Information
A. Dimensions:
224 X 214 mils
B. Passivation:
Si3N4/SiO2 (Silicon nitride/ Silicon dioxide)
C. Interconnect:
Al/0.5%Cu with Ti/TiN Barrier
D. Backside Metallization:
None
E. Minimum Metal Width:
Metal1 = 0.5 / Metal2 = 0.6 / Metal3 = 0.6 microns (as drawn)
F. Minimum Metal Spacing:
Metal1 = 0.45 / Metal2 = 0.5 / Metal3 = 0.6 microns (as drawn)
G. Bondpad Dimensions:
H. Isolation Dielectric:
SiO2
I. Die Separation Method:
Wafer Saw
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MAX8958
V. Quality Assurance Information
A. Quality Assurance Contacts:
Richard Aburano (Manager, Reliability Engineering)
Don Lipps (Manager, Reliability Engineering)
Bryan Preeshl (Vice President of QA)
B. Outgoing Inspection Level:
0.1% for all electrical parameters guaranteed by the Datasheet.
0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate:
< 50 ppm
D. Sampling Plan:
Mil-Std-105D
VI. Reliability Evaluation
A. Accelerated Life Test
The results of the 135°C biased (static) life test are shown in Table 1. Using these results, the Failure Rate ( ) is calculated as follows:
=
1
MTTF
=
= 22.9 x 10
1.83
(Chi square value for MTTF upper limit)
192 x 4340 x 48 x 2
(where 4340 = Temperature Acceleration factor assuming an activation energy of 0.8eV)
-9
= 22.9 F.I.T. (60% confidence level @ 25°C)
The following failure rate represents data collected from Maxim's reliability monitor program. Maxim performs quarterly life test
monitors on its processes. This data is published in the Reliability Report found at http://www.maxim-ic.com/qa/reliability/monitor.
Cumulative monitor data for the S45 Process results in a FIT Rate of 0.06 @ 25C and 0.99 @ 55C (0.8 eV, 60% UCL)
B. E.S.D. and Latch-Up Testing (lot EV2WAQ002A, D/C 1052)
The PR81-3 die type has been found to have all pins able to withstand a HBM transient pulse of +/- 1000V per
JEDEC JESD22-A114, except bumps OUTVCCPAOAC, OUTVCCPDDR, OUTVCCP, OUTVMM and OUTVAON which
pass +/- 500V.
Latch-Up testing has shown that this device withstands a current of +/- 100mA and overvoltage per JEDEC
JESD78, except bump RS-VNN which passes +/- 50mA.
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MAX8958
Table 1
Reliability Evaluation Test Results
MAX8958EWW+T
TEST ITEM
TEST CONDITION
Static Life Test (Note 1)
Ta = 135°C
Biased
Time = 192 hrs.
FAILURE
IDENTIFICATION
SAMPLE SIZE
NUMBER OF
FAILURES
COMMENTS
DC Parameters
& functionality
48
0
EV2WAQ002A, D/C 1052
Note 1: Life Test Data may represent plastic DIP qualification lots.
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