MAX14950A Single-Lane PCIe Equalizer/Redriver General Description Benefits and Features The MAX14950A dual equalizer/redriver improves PCI Express® (PCIe) signal integrity by providing programmable input equalization. This feature reduces deterministic jitter and redrives circuitry to reestablish deemphasis, which compensates for circuit-board loss at high frequencies. The device permits optimal placement of key PCIe components and allows for longer runs of stripline, microstrip, or cable. SInnovative Design Eliminates Need for Costly External Components Single +3.3V Supply Operation The device contains two identical channels capable of equalizing PCIe Gen III (8GT/s), Gen II (5GT/s), and Gen I (2.5GT/s) signals and features electrical idle and receiver detection. SHigh Level of Integration for Performance Random Jitter: 0.5psRMS, Deterministic Jitter: 7psp-p Four-Level-Programmable Input Equalization Eight-Level-Programmable Output Emphasis Electrical Idle Detection Receiver Detection Permits Completely Transparent Operation SIncreased Design Flexibility for BackwardCompatible Applications Optimized for PCIe Gen III (8GT/s) and Gen II (5GT/s) Signals and Compatible with Gen I (2.5GT/s) Signals The MAX14950A is available in a small, 40-pin, 5.0mm x 5.0mm TQFN package with flow-through traces for optimal layout and minimal space requirements. It is specified over the 0NC to +70NC commercial operating temperature range. SIdeal for Space-Sensitive Applications On-Chip 50I Input/Output Terminations 40-Pin, 5.0mm x 5.0mm TQFN Packaging Applications Servers Ordering Information appears at end of data sheet. Test Equipment External Graphics Applications For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14950A.related. Communications Switchers Storage Area Networks Typical Operating Circuit REMOTE BOARD MAIN BOARD MIDPLANE Tx SINGLE DIFFERENTIAL PAIR Rx MAX14950A PCIe PCIe Rx SINGLE DIFFERENTIAL PAIR Tx CONNECTORS PCI Express is a registered service mark of PCI-SIG Corporation. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-5965; Rev 1; 4/13 MAX14950A Single-Lane PCIe Equalizer/Redriver ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VCC........................................................................-0.3V to +4.0V All Other Pins (Note 1).............................. -0.3V to (VCC + 0.3V) Continuous Current IN_P, IN_M, OUT_P, OUT_M............................................................ Q30mA Peak Current IN_P, IN_M, OUT_P, OUT_M (pulsed for 1Fs, 1% duty cycle)................................. Q100mA Continuous Power Dissipation (TA = +70NC) TQFN (derate 35.7mW/NC above +70NC)..................2857mW Operating Temperature Range.............................. 0NC to +70NC Junction Temperature Range............................ -40NC to +150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: All I/O pins are clamped by internal diodes. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 2) TQFN Junction-to-Ambient Thermal Resistance (BJA).......... 28NC/W Junction-to-Case Thermal Resistance (BJC)..................2NC/W Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, CCL = 200nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.0 3.3 3.6 V OEQ_2 = OEQ_1 = OEQ_0 = GND 102 135 OEQ_2 = OEQ_1 = GND, OEQ_0 = VCC 106 140 OEQ_2 = OEQ_0 = GND, OEQ_1 = VCC 107 140 OEQ_2 = GND, OEQ_1 = OEQ_0 = VCC 125 160 OEQ_2 = VCC, OEQ_1 = OEQ_0 = GND 106 140 OEQ_2 = OEQ_0 = VCC, OEQ_1 = GND 132 170 OEQ_2 = OEQ_1 = VCC, OEQ_0 = GND 140 180 OEQ_2 = OEQ_1 = OEQ_0 = VCC 165 210 DC PERFORMANCE Power-Supply Range Supply Current Maxim Integrated VCC ICC EN = VCC mA 2 MAX14950A Single-Lane PCIe Equalizer/Redriver ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CCL = 200nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3) PARAMETER Standby Current SYMBOL ISTBY Differential Input Impedance ZRX-DIFF- Differential Output Impedance ZTX-DIFF- Common-Mode Resistance to GND, Input Termination Not Powered Common-Mode Resistance to GND, Input Termination Powered DC DC ZRX-HIGHIMP-DC ITX-SHORT Common-Mode Delta, Between Active and Idle States VTX-CMDC-ACTIVEIDLE-DELTA DC Output Offset, During Electrical Idle Maxim Integrated EN = GND TYP MAX OEQ_2 = OEQ_1 = OEQ_0 = GND 57 80 OEQ_2 = OEQ_1 = GND, OEQ_0 = VCC 61 85 OEQ_2 = OEQ_0 = GND, OEQ_1 = VCC 62 85 OEQ_2 = GND, OEQ_1 = OEQ_0 = VCC 75 100 OEQ_2 = VCC, OEQ_1 = OEQ_0 = GND 62 80 OEQ_2 = OEQ_0 = VCC, OEQ_1 = GND 85 110 OEQ_2 = OEQ_1 = VCC, OEQ_0 = GND 92 120 OEQ_2 = OEQ_1 = OEQ_0 = VCC 120 150 VTXACTIVEDIFF-DC VTX-IDLEDIFF-DC MIN UNITS mA DC 80 100 120 I DC 80 100 120 I -150mV P VIN_CM P +200mV 50 ZRX-DC Output Short-Circuit Current DC Output Offset, During Active State CONDITIONS 20 Single-ended (Note 4) kI 25 30 90 I mA 100 mV |(VOUT_P - VOUT_M)| 65 mV |(VOUT_P - VOUT_M)| 65 mV 3 MAX14950A Single-Lane PCIe Equalizer/Redriver ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CCL = 200nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC PERFORMANCE (Note 4) Input Return Loss, Differential RLRX-DIFF Input Return Loss, Common Mode RLRX-CM Output Return Loss, Differential RLTX-DIFF Output Return Loss, Common Mode RLTX-CM Redriver-Operation Differential Input-Signal Range VRX-DIFF- Full-Swing Differential Output Voltage (No Deemphasis) VTX-DIFF- Output Deemphasis Ratio, 0dB Output Deemphasis Ratio, 3.5dB f = 0.05GHz to 1.25GHz 9 dB f = 1.25GHz to 2.5GHz 8 dB f = 2.5GHz to 4GHz 5 dB f = 0.05GHz to 2.5GHz 6 dB f = 2.5GHz to 4GHz 4 dB f = 0.05GHz to 1.25GHz 10 dB f = 1.25GHz to 2.5GHz 8 dB f = 2.5GHz to 4GHz 4 dB f = 0.05GHz to 2.5GHz 6 dB f = 2.5GHz to 4GHz 4 dB 100 PP PP VTX-DERATIO-0dB VTX-DERATIO3.5dB OEQ_2 = OEQ_1 = OEQ_0 = GND OEQ_2 = OEQ_1 = OEQ_0 = GND, Figure 1 800 1000 1400 mVP-P 1400 mVP-P 0 dB OEQ_2 = OEQ_1 = GND, OEQ_0 = VCC, Figure 1 3.5 dB Output Deemphasis Ratio, 6dB VTX-DERATIO-6dB OEQ_2 = OEQ_0 = GND, OEQ_1 = VCC, Figure 1 6 dB Output Deemphasis Ratio, 6dB with Higher Amplitude VTX-DE-HA- OEQ_2 = GND, OEQ_1 = OEQ_0 = VCC, RATIO-6dB Figure 1 6 dB 3.5 dB Output Deemphasis Ratio, 3.5dB with Preshoot VTX-DEPS-RATIO3.5dB OEQ_2 = VCC, OEQ_1 = OEQ_0 = GND, Figure 1 Output Deemphasis Ratio, 6dB with Preshoot VTX-DE-PS- OEQ_2 = OEQ_0 = VCC, OEQ_1 = GND, RATIO-6dB Figure 1 6 dB Output Deemphasis Ratio, 9dB with Preshoot VTX-DE-PS- OEQ_2 = OEQ_1 = VCC, OEQ_0 = GND, RATIO-9dB Figure 1 9 dB Output Deemphasis Ratio, 9dB with Preshoot and Higher Amplitude VTX-DE-PS- OEQ_2 = OEQ_1 = OEQ_0 = VCC, Figure 1 9 dB INEQ_1 = INEQ_0 = GND (Note 5) 5 dB Input Equalization, 5dB Maxim Integrated HA-RATIO9dB VRX-EQ5dB 4 MAX14950A Single-Lane PCIe Equalizer/Redriver ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CCL = 200nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3) PARAMETER SYMBOL Input Equalization, 8dB VRX-EQ- Input Equalization, 12dB VRX-EQ- Input Equalization, 16dB VRX-EQ- Output Common-Mode Voltage VTX-CM- Propagation Delay Rise/Fall Time Rise/Fall Time Mismatch 8dB 12dB 16dB AC-PP CONDITIONS FALL tTX-RFMISMATCH INEQ_1 = VCC, INEQ_0 = GND (Note 5) 12 dB INEQ_1 = INEQ_0 = VCC (Note 5) 16 dB MAX(VOUT_P + VOUT_M)/2 - MIN(VOUT_P + VOUT_M)/2 90 (Note 6) Random Jitter tTX-RJ-DD D10.2 pattern, no deemphasis, no preshoot, data rate = 8GT/s Electrical Idle Exit Delay Electrical Idle Detect Threshold tTX-IDLETO-DIFFDATA VTX-IDLETHRESH Output Voltage During Electrical Idle (AC) VTX-IDLEDIFF-AC-P Receiver-Detect Pulse Amplitude VTX-RCV- Maxim Integrated DETECT 160 100 mVP-P 240 ps 20 ps (Note 6) K28.5 pattern, AC-coupled, RL = 50I, no deemphasis, no preshoot, data rate = 8GT/s SET-TOIDLE UNITS dB tTX-DJ-DD tTX-IDLE- MAX 8 Deterministic Jitter Electrical Idle Entry Delay TYP INEQ_1 = GND, INEQ_0 = VCC (Note 5) tPD tTX-RISE- MIN 20 ps 7 23.5 psP-P 0.5 1.5 psRMS From input to output, D10.2 pattern, data rate = 1GT/s 5 ns From input to output, D10.2 pattern, data rate = 1GT/s 5 ns D10.2 pattern, data rate = 1GT/s (Note 3) 50 112 190 mVP-P D10.2 pattern, data rate = 1GT/s to 8GT/s 112 |(VOUT_P - VOUT_M)| Voltage change in positive direction 20 600 mVP-P mV 5 MAX14950A Single-Lane PCIe Equalizer/Redriver ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CCL = 200nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Receiver-Detect Pulse Width 100 ns Receiver-Detect Retry Period 200 ns CONTROL LOGIC Input-Logic Level Low VIL Input-Logic Level High VIH Input-Logic Hysteresis VHYST Input Pulldown Resistance 0.6 1.4 RPD 200 V V 0.1 V 375 kI ±4 kV ESD PROTECTION ESD Voltage Human Body Model (HBM) Note 3: All devices are 100% production tested at TA = +70NC. Specifications over operating temperature range are guaranteed by design. Note 4: Guaranteed by design, unless otherwise noted. Note 5: Equivalent to same amount of deemphasis driving the input. Note 6: Rise and fall times are measured using 20% and 80% levels. VLOW_P-P DE(dB) = 20 log VHIGH_P-P VHIGH_P- P VLOW_P-P Figure 1. Illustration of Output Deemphasis Maxim Integrated 6 MAX14950A Single-Lane PCIe Equalizer/Redriver Typical Operating Characteristics (VCC = +3.3V, TA = +25NC, unless otherwise noted.) INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 0, OEQ2 = 0, DATA RATE = 5GT/s INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 0, OEQ2 = 0, DATA RATE = 5GT/s MAX14950A toc01 INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 1, OEQ2 = 0, DATA RATE = 5GT/s MAX14950A toc02 MAX14950A toc03 600 600 0 -200 -400 400 400 200 200 VOLTAGE (mV) 200 VOLTAGE (mV) VOLTAGE (mV) 400 0 -200 -600 -600 -200 -150 -100 -50 0 50 TIME (ps) -200 -150 -100 -50 0 50 TIME (ps) 100 150 INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 1, OEQ2 = 0, DATA RATE = 5GT/s 100 150 -200 -150 -100 -50 0 50 TIME (ps) INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 0, OEQ2 = 1, DATA RATE = 5GT/s MAX14950A toc04 100 150 INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 0, OEQ2 = 1, DATA RATE = 5GT/s MAX14950A toc05 MAX14950A toc06 600 600 400 VOLTAGE (mV) 200 0 -200 -400 400 200 VOLTAGE (mV) 400 VOLTAGE (mV) -200 -400 -400 -600 0 0 -200 200 0 -200 -400 -400 -600 -600 -600 -200 -150 -100 -50 0 50 TIME (ps) Maxim Integrated 100 150 -200 -150 -100 -50 0 50 TIME (ps) 100 150 -200 -150 -100 -50 0 50 TIME (ps) 100 150 7 MAX14950A Single-Lane PCIe Equalizer/Redriver Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25NC, unless otherwise noted.) INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 1, OEQ2 = 1, DATA RATE = 5GT/s INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 1, OEQ2 = 1, DATA RATE = 5GT/s MAX14950A toc07 MAX14950A toc08 800 600 INEQ0 = 1, INEQ1 = 0, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 6in. MICROSTRIP ON INPUT, DATA RATE = 5GT/s MAX14950A toc09 600 600 400 400 0 -200 200 VOLTAGE (mV) 200 VOLTAGE (mV) VOLTAGE (mV) 400 0 -200 -400 -400 100 150 -200 -150 -100 -50 0 50 TIME (ps) INEQ0 = 1, INEQ1 = 0, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 12in. MICROSTRIP ON INPUT, DATA RATE = 5GT/s 100 150 -200 -150 -100 -50 0 50 TIME (ps) INEQ0 = 0, INEQ1 = 1, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 18in. MICROSTRIP ON INPUT, DATA RATE = 5GT/s MAX14950A toc10 MAX14950A toc12 600 600 400 400 400 200 200 200 -200 VOLTAGE (mV) 600 0 0 -200 0 -200 -400 -400 -400 -600 -600 -600 -200 -150 -100 -50 0 50 TIME (ps) Maxim Integrated 100 150 -200 -150 -100 -50 0 50 TIME (ps) 100 150 100 150 INEQ0 = 1, INEQ1 = 1, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 24in. MICROSTRIP ON INPUT, DATA RATE = 5GT/s MAX14950A toc11 VOLTAGE (mV) VOLTAGE (mV) -200 -600 -800 -200 -150 -100 -50 0 50 TIME (ps) 0 -400 -600 -600 200 -200 -150 -100 -50 0 50 TIME (ps) 100 150 8 MAX14950A Single-Lane PCIe Equalizer/Redriver Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25NC, unless otherwise noted.) 200 VOLTAGE (mV) 100 0 -100 -200 250 100 200 150 VOLTAGE (mV) 200 DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 MAX14950A toc14 300 MAX14950A toc13 300 0 -100 -200 -250 -300 50 100 150 -200 -150 -100 -50 0 50 100 150 -200 -150 -100 -50 0 50 100 150 TIME (ps) TIME (ps) DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 MAX14950A toc16 200 VOLTAGE (mV) 100 300 0 -100 100 0 -100 -200 -150 -100 -50 0 TIME (ps) Maxim Integrated 50 100 150 100 0 -100 -300 -300 -300 200 -200 -200 -200 300 VOLTAGE (mV) 200 MAX14950A toc17 TIME (ps) 300 VOLTAGE (mV) 0 -50 -150 -200 0 50 -100 -300 -200 -150 -100 -50 100 MAX14950A toc18 VOLTAGE (mV) DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 MAX14950A toc15 DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 -200 -150 -100 -50 0 TIME (ps) 50 100 150 -200 -150 -100 -50 0 50 100 150 TIME (ps) 9 MAX14950A Single-Lane PCIe Equalizer/Redriver Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25NC, unless otherwise noted.) DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 DATA RATE = 5Gbps, OUTPUT AFTER 19in STRIP LINE, INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 0, OEQ2 = 0, DATA RATE = 8GT/s MAX14950A toc21 300 VOLTAGE (mV) 100 400 50 0 -50 600 400 200 VOLTAGE (mV) 150 MAX14950A toc20 200 VOLTAGE (mV) 500 MAX14950A toc19 250 100 0 -100 200 0 -200 -100 -200 -150 -300 -400 -200 -400 -600 -250 -500 -200 -150 -100 -50 0 50 100 150 -200 -150 -100 -50 TIME (ps) 0 50 -100 100 150 -50 TIME (ps) MAX14950A toc22 600 50 MAX14950A toc24 MAX14950A toc23 600 100 INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 1, OEQ2 = 0, DATA RATE = 8GT/s INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 1, OEQ2 = 0, DATA RATE = 8GT/s INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 0, OEQ2 = 0, DATA RATE = 8GT/s 0 TIME (ps) 200 200 0 -200 400 VOLTAGE (mV) 400 VOLTAGE (mV) VOLTAGE (mV) 600 400 0 -200 -400 -400 -600 -600 200 0 -200 -400 -600 -100 Maxim Integrated -50 0 TIME (ps) 50 100 -100 -50 0 TIME (ps) 50 100 -100 -50 0 TIME (ps) 50 100 10 MAX14950A Single-Lane PCIe Equalizer/Redriver Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25NC, unless otherwise noted.) INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 0, OEQ2 = 1, DATA RATE = 8GT/s INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 0, OEQ2 = 1, DATA RATE = 8GT/s MAX14950A toc25 MAX14950A toc26 200 VOLTAGE (mV) VOLTAGE (mV) 400 0 -200 -400 MAX14950A toc27 600 600 400 400 200 200 VOLTAGE (mV) 600 INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 1, OEQ2 = 1, DATA RATE = 8GT/s 0 -200 0 -200 -400 -400 -600 -600 -600 -100 -50 0 TIME (ps) 50 -100 100 INEQ0 = INEQ1 = 0, VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 1, OEQ2 = 1, DATA RATE = 8GT/s -50 0 TIME (ps) 50 -400 -600 -100 Maxim Integrated -50 0 TIME (ps) 50 100 0 TIME (ps) 50 MAX14950A toc30 600 600 400 400 200 200 0 -200 0 -200 -400 -400 -600 -600 -100 -50 0 TIME (ps) 50 100 100 INEQ0 = 1, INEQ1 = 0, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 12in. MICROSTRIP ON INPUT, DATA RATE = 8GT/s VOLTAGE (mV) VOLTAGE (mV) VOLTAGE (mV) 400 -200 -50 MAX14950A toc29 600 0 -100 INEQ0 = 0, INEQ1 = 0, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 6in. MICROSTRIP ON INPUT, DATA RATE = 8GT/s MAX14950A toc28 200 100 -100 -50 0 TIME (ps) 50 100 11 MAX14950A Single-Lane PCIe Equalizer/Redriver Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25NC, unless otherwise noted.) 300 400 400 200 200 200 100 0 -200 VOLTAGE (mV) 600 0 -200 0 -100 -400 -400 -200 -600 -600 -300 -50 0 TIME (ps) 50 100 -100 DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 200 0 TIME (ps) 50 100 -100 250 200 150 -100 50 0 -100 -150 -100 -200 -250 -100 -50 0 TIME (ps) Maxim Integrated 50 100 100 200 100 0 -100 -200 -200 -300 50 300 VOLTAGE (mV) VOLTAGE (mV) 0 0 DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 100 100 -50 TIME (ps) DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 MAX14950A toc34 300 -50 MAX14950A toc35 -100 MAX14950A toc33 MAX14950A toc32 600 VOLTAGE (mV) VOLTAGE (mV) MAX14950A toc31 VOLTAGE (mV) DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 INEQ0 = 1, INEQ1 = 1, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 24in. MICROSTRIP ON INPUT, DATA RATE = 8GT/s MAX14590A toc36 INEQ0 = 0, INEQ1 = 1, VIN = 500mVP-P, OEQ0 = OEQ1 = OEQ2 = 0, 18in. MICROSTRIP ON INPUT, DATA RATE = 8GT/s -300 -100 -50 0 TIME (ps) 50 100 -100 -50 0 50 100 TIME (ps) 12 MAX14950A Single-Lane PCIe Equalizer/Redriver Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25NC, unless otherwise noted.) MAX14950A toc37 250 DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 200 150 300 200 VOLTAGE (mV) 0 -100 -150 -100 0 -100 -200 -200 -300 -250 -100 -50 0 50 100 -100 0 50 100 TIME (ps) DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 500 MAX14950A toc39 200 150 400 300 200 VOLTAGE (mV) 100 50 0 -100 100 0 -100 -150 -200 -100 -300 -200 -400 -250 -500 -100 -50 0 TIME (ps) Maxim Integrated -50 TIME (ps) 250 VOLTAGE (mV) 100 MAX14950A toc40 VOLTAGE (mV) 100 50 MAX14950A toc38 DATA RATE = 8Gbps, OUTPUT AFTER 19in STRIPLINE, INEQ_0 = INEQ_1 = 0, VIN = 200mVP-P, 0EQ_0 = 1, OEQ_1 = 0, OEQ_2 = 0 50 100 -100 -50 0 50 100 TIME (ps) 13 MAX14950A Single-Lane PCIe Equalizer/Redriver 24 23 22 21 INBP GND 26 25 GND RXDET GND OUTAM 28 27 INBM 30 29 OUTAP I.C. TOP VIEW GND Pin Configuration GND 31 20 I.C. I.C. 32 19 I.C. VCC 33 18 VCC I.C. 34 17 I.C. OEQA0 35 16 INEQB0 MAX14950A OEQA1 36 15 INEQB1 14 OEQB0 OEQA2 37 INEQA0 38 13 OEQB1 *EP + INEQA1 39 12 OEQB2 11 VCC 6 7 8 9 10 GND OUTBM GND INAP 5 OUTBP GND 4 EN 3 GND 2 INAM 1 GND VCC 40 TQFN (5mm x 5mm) *CONNECT EXPOSED PAD TO GND. Pin Description PIN NAME 1, 2, 5, 7, 10, 21, 24, 26, 29, 31 GND FUNCTION Ground 3 INAP Noninverting Input, Channel A 4 INAM Inverting Input, Channel A 6 EN Enable Input. Drive EN low for standby mode. Drive EN high for normal mode. EN has a 375kI (typ) internal pulldown resistor. 8 OUTBP Noninverting Output, Channel B 9 OUTBM Inverting Output, Channel B 11, 18, 33, 40 VCC Maxim Integrated Power-Supply Input. Bypass VCC to GND with 0.1FF and 0.01FF capacitors in parallel as close as possible to the device. 14 MAX14950A Single-Lane PCIe Equalizer/Redriver Pin Description (continued) PIN NAME 12 OEQB2 Output Deemphasis Control MSB, Channel B. OEQB2 has a 375kI (typ) internal pulldown resistor. FUNCTION 13 OEQB1 Output Deemphasis Bit 1, Channel B. OEQB1 has a 375kI (typ) internal pulldown resistor. 14 OEQB0 Output Deemphasis Control LSB, Channel B. OEQB0 has a 375kI (typ) internal pulldown resistor. 15 INEQB1 Input Equalization Control MSB, Channel B. INEQB1 has a 375kI (typ) internal pulldown resistor. 16 INEQB0 Input Equalization Control LSB, Channel B. INEQB0 has a 375kI (typ) internal pulldown resistor. 17, 19, 20, 30, 32, 34 I.C. Internally connected. Leave I.C. unconnected. 22 INBM Inverting Input, Channel B 23 INBP Noninverting Input, Channel B 25 RXDET 27 OUTAM Inverting Output, Channel A 28 OUTAP Noninverting Output, Channel A Receiver Detection Control Bit. Toggle RXDET to initiate receiver detection. RXDET has a 375kI (typ) internal pulldown resistor. 35 OEQA0 Output Deemphasis Control LSB, Channel A. OEQA0 has a 375kI (typ) internal pulldown resistor. 36 OEQA1 Output Deemphasis Control Bit 1, Channel A. OEQA1 has a 375kI (typ) internal pulldown resistor. 37 OEQA2 Output Deemphasis Control MSB, Channel A. OEQA2 has a 375kI (typ) internal pulldown resistor. 38 INEQA0 Input Equalization Control LSB, Channel A. INEQA0 has a 375kI (typ) internal pulldown resistor. 39 INEQA1 — Maxim Integrated EP Input Equalization Control MSB, Channel A. INEQA1 has a 375kI (typ) internal pulldown resistor. Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to maximize thermal performance and ground conductivity to the device. Do not use EP as the only GND connection. 15 MAX14950A Single-Lane PCIe Equalizer/Redriver Functional Diagram EN RXDET OEQ_2 RECEIVER DETECT MANAGER EQUALIZER IN_P IN_M OUT_P EQUALIZER INEQ_0 INEQ_1 OUT_M OUTPUT ENABLE RHI MAX14950A ELECTRICAL IDLE DETECTOR OEQ_0 OEQ_1 Detailed Description The MAX14950A dual equalizer/redriver supports Gen III (8GT/s), Gen II (5GT/s), and Gen I (2.5GT/s) PCIe data rates. The device contains two identical drivers with idle/receive detect on each lane and equalization/ deemphasis/preshoot to compensate for circuit board loss. Programmable input equalization circuitry reduces deterministic jitter, improving signal integrity. The device features programmable output deemphasis/preshoot, permitting optimal placement of key PCIe components and longer runs of stripline, microstrip, or cable. Maxim Integrated Programmable Input Equalization Programmable input equalization for channel A is controlled by two bits: INEQA1 and INEQA0 and for channel B is controlled by two bits: INEQB1 and INEQB0 (Table 1.) Table 1. Input Equalization INEQ_1 INEQ_0 INPUT EQUALIZATION (dB) 0 0 5 0 1 8 1 0 12 1 1 16 16 MAX14950A Single-Lane PCIe Equalizer/Redriver Programmable Output Deemphasis the receiver detection repeats indefinitely on each channel. If a channel detects a receiver, the other channel is limited to a few retries. Upon receiver detection, input common-mode termination and electrical idle detection are enabled (Table 3.) Programmable output deemphasis/preshoot for channel A is controlled by the three bits: OEQA2, OEQA1, OEQA0 and channel B is controlled by the three bits: OEQB2, OEQB1, OEQB0 (Table 2.) Electrical Idle Detection Receiver Detection The device features electrical idle detection to prevent unwanted noise from being redriven at the output. When the device detects the differential input has fallen below the electrical idle low threshold, it squelches the output. For differential input signals that are above the electrical idle high threshold, the device turns on the output and redrives the signal. The device features receiver detection on each channel. Upon initial power-up, if EN is high, receiver detection initializes. Receiver detection can also be initiated on a rising or falling edge of the RXDET input when EN is high. During this time, the part remains in low-power standby mode and the outputs are squelched, despite the logichigh state of EN. Until a channel has detected a receiver, Table 2. Output Deemphasis/Preshoot OEQ_2 OEQ_1 OEQ_0 OUTPUT DEEMPHASIS RATIO (dB) PEAK-TO-PEAK SWING (V) PRESHOOT 0 0 0 0 1.0 No 0 0 1 3.5 1.0 No 0 1 0 6 1.0 No 0 1 1 6 1.2 No 1 0 0 3.5 1.0 Yes 1 0 1 6 1.0 Yes 1 1 0 9 0.9 Yes 1 1 1 9 1.0 Yes Table 3. Receiver Detection Input Function RXDET EN X 0 Receiver detection is inactive DESCRIPTION X 1 Following a rising edge of EN signal, indefinite retry until a receiver is detected for at least one channel. Retries stop a few times after any channel is detected. Rising/Falling Edge 1 Initiate receiver detection X = Don’t care. Maxim Integrated 17 MAX14950A Single-Lane PCIe Equalizer/Redriver Applications Information Layout Circuit board layout and design can significantly affect the performance of the device. Use good high-frequency design techniques, including minimizing ground inductance and using controlled-impedance transmission lines on data signals. Power-supply decoupling capacitors must be placed as close as possible to VCC. Always connect VCC to a power plane. It is recommended to run receive and transmit on different layers to minimize crosstalk. Ordering Information PART TEMP RANGE PIN-PACKAGE MAX14950ACTL+ 0NC to +70NC 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Chip Information PROCESS: BiCMOS Package Information Exposed-Pad Package The exposed-pad, 40-pin TQFN package incorporates features that provide a very low thermal resistance path for heat removal from the IC. The exposed pad on the device must be soldered to the circuit board ground plane for proper thermal performance. For more information on exposed-pad packages, refer to Maxim Application Note HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages. Power-Supply Sequencing For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 40 TQFN-EP T4055+2 21-0140 90-0002 Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings could cause permanent damage to the device. Proper power-supply sequencing is recommended for all devices. Always apply GND then VCC before applying signals, especially if the signal is not current limited. Maxim Integrated 18 MAX14950A Single-Lane PCIe Equalizer/Redriver Revision History REVISION NUMBER REVISION DATE 0 6/11 Initial release 1 4/13 Updated Benefits and Features section, Electrical Characteristics table; replaced Typical Operating Characteristics 1–12 and 21–32, updated Pin Configuration and Pin Description. Updated Tables 1 and 2. Deleted Table 4. DESCRIPTION PAGES CHANGED — 1, 3, 4, 5, 7, 8, 10–12, 14–17 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2013 Maxim Integrated Products, Inc. 19 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. MAX14950A Single-Lane PCIe Equalizer/Redriver Maxim Integrated 20