9N25 Series

9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
N-Channel Power MOSFET
(8.8A, 250Volts)
DESCRIPTION
D
The Nell 9N25 are N-channel enhancement mode
silicon gate power field effect transistors.
They are designed, tested and guaranteed to
minimize on-state resistance, provide superior
switching performance, and withstand high energy
pulse in the avalanche and commutation mode.
G
These devices are well suited for high efficiency
switching DC/DC converters, switching mode power
supplies, DC-AC converters for uninterrupted power
supplies (UPS) and motor controls.
D
GD
S
S
TO-220AB
(9N25A)
TO-220F
(9N25AF)
D (Drain)
FEATURES
RDS(ON) = 0.43Ω @ VGS = 10V
Ultra low gate charge(35nC max.)
G
(Gate)
Low reverse transfer capacitance
(C RSS = 45pF typical)
S (Source)
Fast switching capability
100% avalanche energy specified
Improved dv/dt capability
150°C operation temperature
PRODUCT SUMMARY
ID (A)
8.8
VDSS (V)
250
RDS(ON) (Ω)
0.45 @ V GS = 10V
QG(nC) max.
35
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise specified)
SYMBOL
TEST CONDITIONS
PARAMETER
VALUE
VDSS
Drain to Source voltage(Note 1)
T J =25°C to 150°C
250
V DGR
Drain to Gate voltage
R GS =20KΩ
250
±30
V GS
ID
Gate to Source voltage
V GS =10V, T C =25°C
Continuous Drain Current
V GS =10V, T C =100°C
UNIT
V
8.8
5.6
35.2
A
I DM
Pulsed Drain current (Note 1)
I AR
Repetitive avalanche current (Note 1)
E AR
Repetitive avalanche energy(Note 1)
I AR =8.8A, R GS =50Ω, V GS =10V
7.4
mJ
E AS
Single pulse avalanche energy (Note 2)
I AS =8.8A, L=5.9mH
285
mJ
5.5
V /ns
dv/dt
PD
TJ
T STG
TL
8.8
Peak diode recovery dv/dt(Note 3)
Total power dissipation ( Derating factor above 25 ° C )
T C =25°C
TO-220AB
TO-220F
74 (0.59)
38 (0.3)
Operation junction temperature
-55 to 150
Storage temperature
-55 to 150
Maximum soldering temperature, for 10 seconds
Mounting torque, #6-32 or M3 screw
3 . I SD ≤ 8.8A, di/dt ≤ 3 0 0A/µs, V DD ≤ V (BR)DSS , T J ≤ 150°C.
Page 1 of 8
ºC
300
10 (1.1)
Note: 1. Repetitive rating: pulse width limited by junction temperature.
2 . V DD =50V, L=5.9mH, I AS =8.8A, R G =25Ω,starting T J =25˚C
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1.6mm from case
W( W / ° C )
lbf . in (N . m)
9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
THERMAL RESISTANCE
SYMBOL
PARAMETER
Min.
Typ.
Max.
TO-220AB
1.69
TO-220F
3.29
Rth(j-c)
Thermal resistance, junction to case
Rth(c-s)
Thermal resistance, case to heatsink
TO-220AB, TO-220F
Rth(j-a)
Thermal resistance, junction to ambient
TO-220AB, TO-220F
0.5
UNIT
ºC/W
62.5
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)
SYMBOL
TEST CONDITIONS
PARAMETER
Min.
Typ.
Max.
UNIT
STATIC
V(BR)DSS
▲V (BR)DSS/▲T J
I DSS
I GSS
Drain to source breakdown voltage
V GS = 0V, I D = 250µA
Breakdown voltage temperature coefficient
I D = 1mA, referenced to 25°C
Drain to source leakage current
T C =125°C
V GS = -30V, V DS = 0V
V GS = 10V, l D = 4.4A (Note 1)
Gate threshold voltage
Forward transconductance
V GS =V DS , I D =250μA
V DS =40V, I D =4.4A
Output capacitance
C RSS
Reverse transfer capacitance
t d(ON)
Turn-on delay time
Rise time
Turn-off delay time
0.35
2
V DS = 25V, V GS = 0V, f =1MHz
Ω
4
V
S
150
60
15
40
V DD = 125V, I D = 8.8A, R G = 25Ω,
V GS = 10V, (Note 1)
85
180
90
190
140
Between lead, 6mm from
package and center of die
65
LS
Internal source inductance
Gate to drain charge (Miller charge)
0.43
46
4.5
Q GD
nA
710
Internal drain inductance
Gate to source charge
100
-100
115
Fall time
Total gate charge
μA
545
tf
QG
10
100
7
LD
Q GS
V/ºC
0.30
Input capacitance
C OSS
t d(OFF)
V DS =200V, V GS =0V
V GS = 30V, V DS = 0V
Static drain to source on-state resistance
tr
T C = 25°C
Gate to source reverse leakage current
V GS(TH)
g fS
DYNAMIC
C ISS
V DS =250V, V GS =0V
Gate to source forward leakage current
R DS(ON)
V
250
35
nC
3.5
V DS = 200V, V GS = 10V, I D = 8.8A
ns
nH
7.5
26.5
pF
13.5
SOURCE TO DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25°C unless otherwise specified)
SYMBOL
VSD
I s (I SD )
PARAMETER
TEST CONDITIONS
Min.
Typ.
Max.
UNIT
V
Diode forward voltage
I SD = 8.8A, V GS = 0V
1.5
Continuous source to drain current
Integral reverse P-N junction
diode in the MOSFET
8.8
D (Drain)
I SM
Pulsed source current
35.2
A
G
(Gate)
S (Source)
218
ns
1.6
μC
t rr
Reverse recovery time
Q rr
Reverse recovery charge
I SD = 8.8A, V GS = 0V,
dI F /dt = 100A/µs
t ON
Forward turn-on time
Intrinsic turn-on time is negligible (turn-on is domonated by LS+LD)
Note: 1. Pulse test: Pulse width ≤ 300μs, duty cycle ≤ 2% .
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Page 2 of 8
9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
ORDERING INFORMATION SCHEME
9
N 25
A
Current rating, ID
9 = 8.8A
MOSFET series
N = N-Channel
Voltage rating, VDS
25 = 250V
Package type
A = TO-220AB
AF = TO-220F (ITO-220AB)
Fig.2 Transfer characteristics
V GS
Top: 15.0V
10.0V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
Bottorm: 4.5V
10 1
Drain Current (A), l D
Drain Current (A),l D
Fig.1 On-region characteristics
10 0
10 1
150ºC
25ºC
-55ºC
10 0
Note:
1. 250µs Pulse Test
2. T C = 25°C
10 0
10 -1
10 1
6
4
2
8
10
Drain-Source voltage , V DS (V)
Gate-to-Source voltage , V GS (V)
Fig.3 On-Resistance variation vs. drain
current and gate voltage
Fig.4 Body diode forward voltage variation
with Source current and Temperatue
1.25
Note:
T J = 25°C
Reverse drain current, l DR (A)
Drain-Source On-Resistance, R DS(ON) (Ω)
10 -1
10 -1
Note:
1. V DS = 40V
2. 250µs Pulse Test
1.00
V GS = 10V
0.75
0.50
V GS = 20V
0.25
0.00
0
10
20
10 0
150ºC
25ºC
Note:
1. V GS = 0V
2. 250µs Pulse Test
10 -1
0.2
30
Drain current, I D (A)
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10 1
0.4
0.6
0.8
1.0
1.2
Source-Drain voltage, V SD (V)
Page 3 of 8
1.4
9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
Fig.5 Capacitance characteristics
Fig.6 Gate charge characteristics
12
Capacitance, (pF)
C iss = C gs +C gd ( C gs = shorted )
C oss = C ds +C gd
C rss = C gd
1500
C ISS
1000
C OSS
C RSS
500
Notes:
1. V GS = 0V
Gate-Source voltage,V GS (V)
2000
V DS = 50V
10
V DS = 125V
V DS = 200V
8
6
4
2
Note: l D = 8.8A
2. f = 1MH z
0
0
10 -1
10 0
10 1
5
0
Drain-Source voltage, V DS (V)
25
30
3.0
Drain-Source On-Resistance,
R Ds(ON) , (Normalized)
Drain-Source breakdown voltage,
BV Dss (Normalized)
20
Fig.8 On-Resistance variation vs.
.
Temperature
1.2
1.1
1.0
0.9
Note:
1. V GS = 0V
2. l D = 250μA
0.8
-100
-50
0
50
100
150
2.5
2.0
1.5
1.0
Note:
1. V GS = 10V
2. l D = 4.4A
0.5
0.0
-100
200
Junction temperature, T j (°C)
-50
0
50
100
150
Fig.9-2 Maximum safe operating area
for 9N25AF
10 2
10 2
Operation in This Area is Limited by R DS(on)
Operation in This Area is Limited by R DS(on)
1ms
10ms
DC
10 0
Note:
1.T C = 25°C
10µs
Drain current, l D , (A)
100µs
10 1
100µs
10 1
1ms
10ms
10 0
DC
Note:
1.T C = 25°C
2.T J = 150°C
2.T J = 150°C
3.Sing Pulse
3.Sing Pulse
10 -1
10 0
10 1
10 2
10 0
Drain-Source voltage, V DS (V)
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200
Junction temperature, T J (°C)
Fig.9-1 Maximum safe operating area
for 9N25A
Drain current, l D , (A)
15
Total gate charge, Q G (nC)
Fig.7 Breakdown voltage variation vs.
Temperature
10 -1
10
10 1
10 2
Drain-Source voltage, V DS (V)
Page 4 of 8
9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
Fig.10 Maximum drain current vs
Case temperature
10
Drain current ,l D (A)
8
6
4
2
0
25
50
75
100
125
150
Case temperature, T j (°C)
Thermal response zθJC (t)
Fig.11-1 Transient thermal response curve for 9N25A
10 0 D = 0.5
0.2
0.1
10 -1
PDM
0.05
t1
Single pulse
t2
0.02
0.01
Notes:
1. ZθJC (t) = 1.69 °C/W Max.
2. Duty = Factor, D = t1/t2
3. TJM - TC = PDM x ZθJC (t)
10 -2
10 -5
10 -4
10 -3
10 -2
10 -1
10 -0
10 1
Square wave pulse duration , t 1 (seconds)
Thermal response zθJC (t)
Fig.11-2 Transient thermal response curve for 9N25AF
D = 0.5
10 0
0.2
0.1
PDM
0.05
10 -1
Single pulse
t1
0.02
t2
0.01
Notes:
1. ZθJC (t) = 1.69 °C/W Max.
2. Duty = Factor, D = t1/t2
3. TJM - TC = PDM x ZθJC (t)
10 -2
10 -5
10 -4
10 -3
10 -2
10 -1
Square wave pulse duration , t 1 (seconds)
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Page 5 of 8
10 -0
10 1
9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
Fig.12a. Switching time test circuit
Fig.12b. Switching time waveforms
RD
V DS
V DS
90%
V GS
RG
D.U.T.
+
- V DD
10V
V GS
Pulse width ≤ 1µs
Duty Factor ≤ 0.1%
10%
t d(ON)
Fig.13a. Unclamped lnductive test circuit
tF
Fig.13b. Unclamped lnductive waveforms
E AS =
L
V DS
t d(OFF)
tR
1
L l AS 2
2
BV DSS
BV DSS - V DD
BV DSS
l AS
RG
D.U.T.
l AS
+
V
- DD
l D(t)
A
V DS(t)
V DD
10V
0.01Ω
tP
Time
tp
Vary t p to obtain required I AS
Fig.14a. Basic gate charge waveform
Fig.14b. Gate charge test circuit
Current Regulator
Same Type as D.U.T.
V GS
50KΩ
QG
12V
10V
0.2µF
0.3µF
Q GS
+
Q GD
D.U.T.
V GS
3mA
RG
Charge
RD
Current Sampling Resistors
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Page 6 of 8
-
V DS
9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
Fig.15 Peak diode recovery dv/dt test circuit for N-Channel MOSFET
D.U.T.
Driver Gate Drive
+
Circuit Layout Considerations
• Low Stray lnductance
• Ground Plane
• Low Leakage lnductance
Current Transformer
D=
Period
P.W.
P.W.
Period
VGS=10V
-
*
D.U.T. I SD Waveform
+
-
-
RG
Reverse
Recovery
Current
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
•
•
•
•
dv/dt controlled by R G
Driver same type as D.U.T.
l SD controlled by Duty Factor " D "
D.U.T. -Device Under Test
Re-Applied
Voltage
+
-
V DD
Diode Recovery
dv/dt
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
*V GS = 5V for Logic Level Devices and 3V for drive devices
Case Style
TO-220AB
10.54 (0.415) MAX.
9.40 (0.370)
9.14 (0.360)
4.70 (0.185)
4.44 (0.1754)
3.91 (0.154)
3.74 (0.148)
1.39 (0.055)
1.14 (0.045)
2.87 (0.113)
2.62 (0.103)
3.68 (0.145)
3.43 (0.135)
1
PIN
2
16.13 (0.635)
15.87 (0.625)
3
4.06 (0.160)
3.56 (0.140)
15.32 (0.603)
14.55 (0.573)
8.89 (0.350)
8.38 (0.330)
29.16 (1.148)
28.40 (1.118)
2.79 (0.110)
2.54 (0.100)
1.45 (0.057)
1.14 (0.045)
2.67 (0.105)
2.41 (0.095)
2.65 (0.104)
2.45 (0.096)
14.22 (0.560)
13.46 (0.530)
0.90 (0.035)
0.70 (0.028)
5.20 (0.205)
4.95 (0.195)
0.56 (0.022)
0.36 (0.014)
D (Drain)
G
(Gate)
S (Source)
All dimensions in millimeters(inches)
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Page 7 of 8
9N25 Series
SEMICONDUCTOR
RoHS
RoHS
Nell High Power Products
Case Style
TO-220F
10.6
10.4
3.4
3.1
2.8
2.6
3.7
3.2 7.1
6.7
16.0
15.8
16.4
15.4
2
1
3
10°
3.3
3.1
13.7
13.5
2.54
TYP
0.9
0.7
0.48
0.44
2.54
TYP
2.85
2.65
4.8
4.6
D (Drain)
G
(Gate)
S (Source)
All dimensions in millimeters
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Page 8 of 8